KR100192363B1 - Structure of thin film transistor and manufacture thereof - Google Patents

Abstract

The present invention relates to a thin film transistor and a method of manufacturing the same, the process of forming a lower body layer on the insulating film on the substrate to reduce the off current of the thin film transistor, a process of forming a lower gate insulating film on the lower body layer, Forming a gate electrode on the lower gate insulating layer, implanting impurities into the lower body layer on one side of the gate electrode, and forming a light doped offset (LDO) region; Selectively etching a gate insulating film to form a contact hole, depositing polysilicon on the entire surface of the resultant to form an upper body layer connected to the lower body layer through the contact hole, and Forming a source region and a drain region in the upper body layer, respectively. Provided are a transistor and a method of manufacturing the same.

According to the present invention, as the channel length of the thin film transistor can be increased, the size of the device can be reduced, which is advantageous for high integration. It is possible to implement a thin film transistor having a characteristic.

Description

Structure of thin film transistor and its manufacturing method

1 is a process flowchart showing a method of manufacturing a thin film transistor according to the prior art.

2 is a process flowchart showing a method of manufacturing a thin film transistor according to the present invention.

1 insulating film 6 lower body layer

7: lower gate insulating film 8: gate electrode

9, 13 photoresist pattern 10: upper gate insulating film

11 contact hole 12 upper body layer

E: LDO region F: source region

G: drain area

* Explanation of symbols for main parts of the drawings

1 insulating film 6 lower body layer

7: lower gate insulating film 8: gate electrode

9, 13 photoresist pattern 10: upper gate insulating film

11 contact hole 12 upper body layer

E: LDO region F: source region

G: drain area

TECHNICAL FIELD The present invention relates to a structure of a thin film transistor and a method of manufacturing the same, and more particularly, to a structure of a p-MOS thin film transistor adapted to reduce off current and a method of forming the same.

A conventional thin film transistor manufacturing method will be described with reference to FIG. 1 as follows.

First, as shown in FIG. 1A, a conductive material, for example, polysilicon is deposited on the insulating film 1 formed on a substrate (not shown), and then patterned by a photolithography process to form the gate electrode 2. do.

Subsequently, as shown in FIG. 1A, the gate oxide film 3 and the body polysilicon layer 4 are sequentially formed on the entire surface of the insulating film 1 on which the gate electrode 2 is formed by CVD (Chemical Vapor Deposition). .

Next, as shown in FIG. 1C, the photoresist 5 is coated on the body polysilicon layer 4, and then patterned by a photolithography process to define a channel region and an offset region. The portion covered by the photoresist 5 is a channel region and an osset region.

Subsequently, BF (subscript 2) is ion implanted using the photoresist pattern 5 defining the channel region and the offset region as a mask, and the source region A and the drain region D as shown in FIG. By forming, a thin film transistor having a channel region B and an offset region C is completed.

In the conventional thin film transistor fabrication, in order to reduce the off current of the thin film transistor, a method of increasing the channel length or applying an offset drain structure is employed. As the size of the device increases, the cell size increases when applied to static random access memory (SRAM).

In addition, in the above-described prior art, since the offset region is formed by ion implantation using a mask during the ion implantation process for forming the offset region, there is a problem in that the characteristic changes depending on the degree of alignment of the mask.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to increase the channel length by forming the body layers of the thin film transistors at the top and bottom thereof.

The structure of the thin film transistor of the present invention for achieving the above object is a gate electrode, a first insulating film surrounding the gate electrode, and the first insulating film between the upper, lower, one side and another of the gate electrode A channel region portion formed at a portion of one side, a source region portion connected to one end of the channel region portion, a drain region portion connected to another end of the channel region portion, the source region portion and the drain And a second insulating film formed between the region portions and connected to the first insulating film. The method of manufacturing a thin film transistor having the above structure includes forming a lower body layer on the insulating film on a substrate. And forming a lower gate insulating film on the lower body layer, and a gate on the lower gate insulating film. Forming a pole, implanting impurities into the lower body layer on one side of the gate electrode to form a light doped offset (LDO) region, and selectively etching the upper gate insulating film and the lower gate insulating film on the entire surface of the resultant Forming a contact hole, depositing polysilicon on the entire surface of the resultant, forming an upper body layer connected to the lower body layer through the contact hole, and in the upper body layer of the LDO region It is characterized by consisting of a step of forming a source region and a drain region.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The structure of the thin film transistor according to the present invention includes a gate electrode 8, a lower gate insulating film 7 and an upper gate insulating film 10 formed around the gate electrode 8, and an upper gate insulating film of the lower gate insulating film 7. The lower body layer 6 and the upper body layer 12 and the lower body are formed in a portion of the upper, lower, one side, and another side of the gate electrode 8 with the interposed portion 10 interposed therebetween. It consists of a source region E and a drain region G formed in a predetermined region of the body layer 6 and the upper body layer 12.

Here, the upper body layer 12 and the lower body layer 6 are connected to each other and surround the gate electrode 8 to form a channel region of the thin film transistor, and the upper gate insulating layer 10 and the lower gate insulating layer 7 Are connected to each other.

Such a method of manufacturing the thin film transistor of the present invention is as follows.

2 shows a method of manufacturing a thin film transistor according to the present invention according to the process sequence.

First, polysilicon is deposited as the lower body layer 6 on the insulating film 1 formed on the substrate (not shown) as shown in FIG. 2A, and thereafter, as the lower gate insulating film 7 thereon. For example, an oxide film is formed.

Subsequently, as illustrated in FIG. 2B, a conductive material is deposited on the lower gate insulating layer 7, and then patterned into a predetermined gate electrode pattern to form the gate electrode 8.

Subsequently, after the photoresist is applied to the entire surface of the resultant, the photoresist is patterned by a photolithography process so that only one side of the formed lower body layer 6 is exposed to form a photoresist pattern 9, and then the photoresist pattern ( BF ₂ is ion-implanted with a dose of 1 to 50E12 using 9) as a mask to form an LDO (Light Doped Offset) region (E).

At this time, the LDO region E is self-aligned by the formed gate electrode 8.

Next, as shown in FIG. 2C, the photoresist pattern is removed, and then the upper gate insulating layer 10 and the lower gate insulating layer 7 are selectively etched on the entire surface of the resulting lower body polysilicon layer ( 6) and a contact hole 11 for connecting the upper body layer formed in a subsequent process.

Subsequently, as shown in FIG. 2D, polysilicon is deposited on the entire surface of the resultant to form the upper body layer 12, and then a photoresist is applied thereon, and then patterned through photolithography to form a source and a drain. After forming the mask pattern 13 at the time of ion implantation, BF ₃ is ion-implanted to form a source region F in the upper body layer 12 and a drain region G in the lower body layer 6. do.

At this time, the drain region G is self-aligned to the upper gate insulating layer 10 and the upper body layer 12 formed on the gate electrode 8 and the side surface of the gate electrode.

As described above, the present invention reduces the off current by forming a thin film transistor having a long channel surrounding the upper and lower portions of the gate by forming a body layer on the upper and lower portions of the gate electrode, respectively.

In addition, since the LDO region and the source and drain regions are defined by self-alignment, the characteristic change according to the degree of mask alignment does not occur.

As described above, according to the present invention, the channel length of the thin film transistor can be formed longer than that of the conventional thin film transistor in the same area, so that the size of the device can be reduced, which is advantageous for high integration. By forming self-alignment between the and LDO regions, it is possible to realize a thin film transistor having a certain characteristic regardless of the process change.

Claims (5)

Forming a lower body layer 6 on the insulating film 1 on the substrate, forming a lower gate insulating film 7 on the lower body layer 6, and forming a lower gate insulating film 7 on the lower gate insulating film 7 Forming a gate electrode (8), implanting impurities into the lower body layer (6) on one side of the gate electrode (8), and forming a light doped offset (LDO) region (E); Selectively etching the upper gate insulating film 10 and the lower gate insulating film 7 to form a contact hole 11, depositing polysilicon on the entire surface of the resultant, and forming the contact hole 11 through the contact hole 11. Forming an upper body layer 12 connected to the layer 6, and forming a source region E and a drain region G in the upper body layer 12 in the LDO region E region, respectively. A thin film transistor manufacturing method comprising a step of making. The method of claim 1, wherein the dose of impurities is 1 to 50E12 during the ion implantation process to form the LDO region (E). The method of claim 1, wherein the LDO region is formed to be self-aligned to the gate electrode (8). The method of claim 1, wherein the drain region is formed to be self-aligned to the gate electrode (8), the upper gate insulating film (10), and the upper body layer (12). A channel region formed on a portion of an upper side, a lower side, one side, and another side of the gate electrode with the gate electrode and the first insulating layer surrounding the gate electrode interposed therebetween; A source region formed in connection with one end, a drain region formed in connection with the channel region and another end, and formed between the source region and the drain region and connected to the first insulating layer. A thin film transistor structure comprising a second insulating film.