JPS63161625A - Manufacture of field-effect transistor - Google Patents
Manufacture of field-effect transistorInfo
- Publication number
- JPS63161625A JPS63161625A JP31139386A JP31139386A JPS63161625A JP S63161625 A JPS63161625 A JP S63161625A JP 31139386 A JP31139386 A JP 31139386A JP 31139386 A JP31139386 A JP 31139386A JP S63161625 A JPS63161625 A JP S63161625A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- effect transistor
- substrate
- film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000008021 deposition Effects 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 7
- 230000005684 electric field Effects 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 8
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電界効果トランジスタ（ＦＥＴ）の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing field effect transistors (FETs).
従来の技術
従来、電極間分離膜や層間絶縁膜に用いられている膜は
、堆積中に膜質を変えて堆積しない。BACKGROUND OF THE INVENTION Conventionally, films used for interelectrode separation films and interlayer insulating films do not change their film quality during deposition.
発明が解決しようとする問題点
従来の方法では、膜の熱膨張係数と基板のそれが相異な
るため、基板表面附近にストレスがはいリ、製造工程中
クランクの発生や基板上の各素子に悪影響を及ぼすとい
う問題点がある。Problems that the invention aims to solve In conventional methods, the coefficient of thermal expansion of the film is different from that of the substrate, which creates stress near the surface of the substrate, causing cranking during the manufacturing process and adversely affecting each element on the substrate. There is a problem that it causes
問題点を解決するための手段
本発明は、これらの問題から、膜堆積中に基板界面から
表面に向って膜質を変化させることにより、基板界面の
ストレスを緩和するものである。Means for Solving the Problems The present invention solves these problems by changing the film quality from the substrate interface toward the surface during film deposition, thereby alleviating the stress at the substrate interface.
作 用
本発明の半導体装置の製造方法により、基板と絶縁膜と
の密着が強くなり、基板表面附近のストレスが緩和され
、クラックの発生がなくなり、ウェハ面内の素子特性の
均一性が高まり、半導体装置の歩留りが向上する。Effect: The semiconductor device manufacturing method of the present invention strengthens the adhesion between the substrate and the insulating film, relieves stress near the substrate surface, eliminates the occurrence of cracks, and increases the uniformity of device characteristics within the wafer surface. The yield of semiconductor devices is improved.
実施例 以下本発明の一実施例を説明する。Example An embodiment of the present invention will be described below.
第１図は、ＧａＡｓ電界効果トランジスタ（ＧａＡＢＦ
Ｅ Ｔ ）の製造工程図である。第１図ａにおいてＧ
ａ Ａ ｓ半絶縁性基板１０表面にフォトリソ技術と
イオン注入技術を用い、イオン注入層２を形成する。第
１図すにおいてＧａＡｓ基板表面上にＰＣＶＤ−３ｉＮ
膜３を堆積する。第１図Ｃにおいて、ソース・ドレイン
のオーミック電極４．ゲート電極５を形成し、ＦＥＴが
完成する。Figure 1 shows a GaAs field effect transistor (GaABF).
ET) is a manufacturing process diagram. In Figure 1a, G
The ion implantation layer 2 is formed on the surface of the a As semi-insulating substrate 10 using photolithography and ion implantation techniques. In Figure 1, PCVD-3iN was deposited on the surface of the GaAs substrate.
Deposit film 3. In FIG. 1C, source/drain ohmic electrodes 4. A gate electrode 5 is formed, and the FET is completed.
従来ＰＣＶＤ−５ｉＮ模３の膜質はＳｉ／Ｎ ＝０．７
〜０．７５で膜厚に対してほぼ一定である。The film quality of conventional PCVD-5iN model 3 is Si/N = 0.7
~0.75, which is almost constant with respect to film thickness.
本発明では、この絶縁膜の膜質を膜厚に対して変化させ
ることを特徴としている。The present invention is characterized in that the film quality of this insulating film is changed depending on the film thickness.
第２図は、半絶縁性Ｇａ Ａ ｓ基板上にプラズマＣＶ
Ｄ −Ｓ ｉ Ｎ膜（ＰＣＶＤ−８ｉＮ膜）を堆ｆｆ
１ｔ、り場合ｔ７） ＰＣＶＤ−８ｉ Ｎ 膜中（７）
Ｓ ｉ 、 Ｎ 、Ｏｔ７）量ヲ百分率表示した図で
ある。この図は、ＳｉＮ堆積に用いられるＳ ｔ Ｈ４
，ＮＨ３の全流量を１０８Ｃ；ＣＭ から１１００５Ｃ
Ｃまで連続に増加させ、１ｏｏｖｖ。Figure 2 shows plasma CV on a semi-insulating GaAs substrate.
Deposition of D-SiN film (PCVD-8iN film)
1t, t7) PCVD-8i N film (7)
It is a diagram showing the amount of S i , N , Ot7) as a percentage. This figure shows S t H4 used for SiN deposition.
, the total flow rate of NH3 from 108C; CM to 11005C
Continuously increase to C, 1oovv.
０．３ ｔｏｒｒで堆積した場合である。堆積膜厚は４
２００人で、Ｇ ａ Ａ ｓ基板との界面では比較的酸
素０の量が多く、表面附近では非常にその量は減少して
いる。ＳｉＮ膜はＧ ａ Ａ ｔｓ基板に対して圧縮応
力となりその量はｅｓ ｘ １ｏ ｄｙｎ／ｃ＋＋１
である一方酸素量が多い界面附近では５ｔ−０−Ｎ膜で
あり、この場合Ｇ ａ Ａ ｓ基板に対して２ Ｘ １
０ ｄｙｎ／ ｃａと小さな引張応力となり、全膜厚で
は、Ｇ ａ Ａ ｓ基板に対して応力がほとんどかから
ないようになる。This is the case where deposition was performed at 0.3 torr. Deposited film thickness is 4
200 people, the amount of oxygen 0 is relatively large at the interface with the GaAs substrate, but the amount decreases significantly near the surface. The SiN film exerts compressive stress on the Ga Ats substrate, and the amount of stress is es x 1o dyn/c++1
On the other hand, near the interface where the amount of oxygen is high, it is a 5t-0-N film, and in this case, the film is 2×1 for the GaAs substrate.
The tensile stress is as small as 0 dyn/ca, and almost no stress is applied to the GaAs substrate at the full film thickness.
今回５ｔＨ４，ＮＨ３の全流量で行なった場合を述べた
が、デポ時の圧力を高圧から低圧に変化させた場合、プ
ラズマ電界（パワー）を低電界から高電界に変化させた
場合、基板温度を低温から高温に変化させた場合も同様
、絶縁膜の堆積速度が〜１００へ／諧から〜５００人／
ｍｍ の変化であれば、堆積した絶縁膜は、第１図に
示す絶縁膜が形成される。This time we have described the case where the full flow rate of 5tH4 and NH3 was used, but if the pressure at the time of deposition is changed from high pressure to low pressure, and if the plasma electric field (power) is changed from low electric field to high electric field, the substrate temperature will change. Similarly, when changing from low temperature to high temperature, the deposition rate of the insulating film increases from ~100/scale to ~500/
If the change is in mm 2 , the deposited insulating film will form the insulating film shown in FIG.
第３図は、ＳｉＮ 膜による基板のそり（たわみ）を
２インチウニ・・の中心を基準にして表わした図である
。第２図より、従来のＰＣＶＤ−８ｉＮ膜の場合に比べ
本発明の実施例の場合の方が、そりが小さいことがわか
る。従来のそりは、半導体装置を製造する上で、フォト
リングラフィによる不均一性を生み、半導体装置の歩留
りを悪化させる。このため基板のたわみはできるだけ少
ない方がよい。FIG. 3 is a diagram showing the warp (deflection) of the substrate caused by the SiN film with the center of a 2-inch sea urchin as a reference. From FIG. 2, it can be seen that the warpage is smaller in the case of the example of the present invention than in the case of the conventional PCVD-8iN film. Conventional warpage causes non-uniformity due to photolithography in manufacturing semiconductor devices, which deteriorates the yield of semiconductor devices. For this reason, it is better to minimize the deflection of the substrate.
第４図は、ＳｉＮ膜による基板上のＦＥＴの閾値電圧Ｖ
ヤ、を２インチウェハの中心を基準にして表わした図で
ある。第３図より、従来のＰＣＶＤ−８ｉＮ膜の場合に
比べ本発明の実施例の場合の方が、■や。Figure 4 shows the threshold voltage V of an FET on a substrate made of a SiN film.
FIG. From FIG. 3, it can be seen that compared to the case of the conventional PCVD-8iN film, the case of the embodiment of the present invention is .
の変化は小さいことがわかる。It can be seen that the change in is small.
発明の効果
以上のように本発明によれば、基板と絶縁膜との密着が
強くなり、基板表面附近のストレスが緩和され、クラッ
クの発生がなくなり、ウエノ・面内の素子特性の均一性
が高まり、半導体装置の歩留りが向上した。Effects of the Invention As described above, according to the present invention, the adhesion between the substrate and the insulating film is strengthened, the stress near the substrate surface is alleviated, the occurrence of cracks is eliminated, and the uniformity of device characteristics within the surface of the wafer is improved. As a result, the yield of semiconductor devices has improved.
第１図は本発明の一実施例における電界効果トランジス
タの製造工程を示す断面図、第２図は半絶縁性Ｇ ａ
Ａ ｓ基板上にプラズマＣＶ Ｄ −Ｓ ｉ Ｎ嘆（Ｐ
ＣＶＤ−３ｉ Ｎ 膜） ヲ堆積シタ場合ノＰＣＶＤ−
３ｉ Ｎ膜中のＳｉ、Ｎ、Ｏの量を百分率表示した特性
図、第３図はＳｉＮ 膜により基板のそり（たわみ）を
表わした特性図、第４図はＳｉＮ 膜による基板上のＦ
ＥＴの閾値電圧ｖ＋ｈの分布を表わした特性図である。
１・・・・・・Ｇ ａ Ａ ｓ半絶縁性基板、２・・・
・・・イオン注入層、３・・・・・・ＳｉＮ 絶縁膜、
４，６・・・・・・電極。
、ｉ −） ｚ し’ｌ （Ａｔｏｍｉｃ Ｃｏｎ
ｃｔｒｔｒｅｔ：ｏｎｌｓ）Ｔ ； ： ：FIG. 1 is a cross-sectional view showing the manufacturing process of a field effect transistor according to an embodiment of the present invention, and FIG.
Plasma CVD-S iN (P
CVD-3i N film) PCVD-
3i Characteristic diagram showing the amounts of Si, N, and O in the N film as percentages. Figure 3 is a characteristic diagram showing the warping (deflection) of the substrate due to the SiN film. Figure 4 is the characteristic diagram showing the warping (deflection) of the substrate due to the SiN film.
FIG. 3 is a characteristic diagram showing the distribution of threshold voltage v+h of ET. 1...G a As semi-insulating substrate, 2...
...Ion implantation layer, 3...SiN insulating film,
4, 6... Electrode. , i −) z し'l (Atomic Con
ctrtret:onls)T ; : :
Claims (6)
形成する工程と、前記第１の半導体層をはさんで前記第
１の半導体と同一導電型の高濃度の第２の半導体層を形
成する工程と、前記第１、第２の半導体層表面に被着条
件を連続的に変化させた絶縁膜を被着させる工程と、ゲ
ート部にショットキ電極を、ソースドレイン部にオーミ
ック電極を形成する工程とを含んでなる電界効果トラン
ジスタの製造方法。(1) A step of forming a first semiconductor layer of one conductivity type on one main surface of the semiconductor, and a second semiconductor layer of high concentration of the same conductivity type as the first semiconductor layer sandwiching the first semiconductor layer. a step of depositing an insulating film on the surfaces of the first and second semiconductor layers under successively changing deposition conditions; and a step of forming a Schottky electrode on the gate portion and a Schottky electrode on the source/drain portion. A method for manufacturing a field effect transistor, comprising the step of forming an ohmic electrode.
から低圧に連続的に減圧する特許請求の範囲第１項記載
の電界効果トランジスタの製造方法。(2) The method for manufacturing a field effect transistor according to claim 1, wherein the pressure of a gas in an atmosphere is continuously reduced from high pressure to low pressure during the formation of the insulating film.
ら高電界に連続的にパワーを上昇させる特許請求の範囲
第１項記載の電界効果トランジスタの製造方法。(3) The method for manufacturing a field effect transistor according to claim 1, wherein the power of the plasma electric field during the formation of the insulating film is continuously increased from a low electric field to a high electric field.
る特許請求の範囲第１項記載の電界効果トランジスタの
製造方法。(4) The method for manufacturing a field effect transistor according to claim 1, wherein the total flow rate of gas during the formation of the insulating film is continuously increased.
する特許請求の範囲第１項記載の電界効果トランジスタ
の製造方法。(5) The method for manufacturing a field effect transistor according to claim 1, wherein the substrate temperature is raised continuously from a low temperature during the formation of the insulating film.
ｉｎから〜５００Å／ｍｉｎまで連続的に速くする特許
請求の範囲第１項記載の電界効果トランジスタの製造方
法。(6) Insulating film deposition rate during insulating film formation ~100 Å/m
2. The method of manufacturing a field effect transistor according to claim 1, wherein the speed is continuously increased from in to ~500 Å/min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31139386A JPH07111979B2 (en) | 1986-12-25 | 1986-12-25 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31139386A JPH07111979B2 (en) | 1986-12-25 | 1986-12-25 | Method for manufacturing field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63161625A true JPS63161625A (en) | 1988-07-05 |
| JPH07111979B2 JPH07111979B2 (en) | 1995-11-29 |
Family
ID=18016644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31139386A Expired - Fee Related JPH07111979B2 (en) | 1986-12-25 | 1986-12-25 | Method for manufacturing field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07111979B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248179A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Semiconductor device |
| WO2007091301A1 (en) * | 2006-02-07 | 2007-08-16 | Fujitsu Limited | Semiconductor device and process for producing the same |
| JP2007311464A (en) * | 2006-05-17 | 2007-11-29 | Fujitsu Ltd | Compound semiconductor device and its manufacturing method |
-
1986
- 1986-12-25 JP JP31139386A patent/JPH07111979B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248179A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Semiconductor device |
| WO2007091301A1 (en) * | 2006-02-07 | 2007-08-16 | Fujitsu Limited | Semiconductor device and process for producing the same |
| US7960763B2 (en) | 2006-02-07 | 2011-06-14 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| US8163653B2 (en) | 2006-02-07 | 2012-04-24 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| US8227838B2 (en) | 2006-02-07 | 2012-07-24 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| US8399361B2 (en) | 2006-02-07 | 2013-03-19 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| JP2007311464A (en) * | 2006-05-17 | 2007-11-29 | Fujitsu Ltd | Compound semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07111979B2 (en) | 1995-11-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |