JPS60263437A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS60263437A JPS60263437A JP11905784A JP11905784A JPS60263437A JP S60263437 A JPS60263437 A JP S60263437A JP 11905784 A JP11905784 A JP 11905784A JP 11905784 A JP11905784 A JP 11905784A JP S60263437 A JPS60263437 A JP S60263437A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- film transistor
- gate insulating
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、ＣｄＳｅ ＋ Ｔｏ ＋アモルファスＳｉな
どの半導体膜を用いた薄膜トランジスタの製造方法に関
し、特にゲート絶縁膜にプラズマＣＶＤ（以下、ＰＣＶ
Ｄと略す）ＳｉＯｘ膜を用いる薄膜トランジスタに関す
るものである。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method for manufacturing a thin film transistor using a semiconductor film such as CdSe + To + amorphous Si, and in particular, a method for manufacturing a thin film transistor using a semiconductor film such as CdSe + To + amorphous Si.
(abbreviated as D) relates to a thin film transistor using a SiOx film.
近年、半導体製造技術の進歩に伴って薄膜トランジスタ
の特性や製造時の再現性が良くなシ、この素子をディス
プレイ用の駆動素子として応用する試みがなされている
。In recent years, with the advancement of semiconductor manufacturing technology, the characteristics of thin film transistors and the reproducibility during manufacturing have improved, and attempts have been made to apply this element as a driving element for displays.
第１図に半導体膜としてＣｄ８ｅを用いた薄膜トランジ
スタの基本構造を示す。このＣｄ８ｅ １ｊＪ（）ラン
ジスタは、ガラスなどの絶縁基板１上にｊＩ重積層して
形成されたゲート電極２．ゲート絶縁膜３ 、ｅｄｇｅ
膜４と、この膜４に対してオーム接触式せて形成された
ソースおよびドレイン電極５゜Ｂとから構成されるもの
で、これらソース、ドレイン電極５．６間に設けられる
Ｃｄ８ｅ膜４（チャンネルともいう）に流れる電流をゲ
ート電極２に印加される電圧によって制御する一種の電
界効果形トランジスタである。なお、薄膜トランジスタ
を例えばマトリクス形ディスプレイの駆動系子に用いる
場合は、通常、第１図に示す構成要素を単位素子とし、
各表示エレメントにそれぞれ対応させたマトリクス構造
がとられていて、これをアクティブマトリクスと称して
いる。FIG. 1 shows the basic structure of a thin film transistor using Cd8e as a semiconductor film. This Cd8e 1jJ() transistor has a gate electrode 2.jI layered on an insulating substrate 1 made of glass or the like. Gate insulating film 3, edge
It consists of a film 4 and source and drain electrodes 5°B formed in ohmic contact with this film 4, and a Cd8e film 4 (channel It is a type of field effect transistor in which the current flowing through the gate electrode (also referred to as the gate electrode) is controlled by the voltage applied to the gate electrode 2. Note that when thin film transistors are used, for example, as drive system elements of matrix-type displays, the components shown in FIG. 1 are usually used as unit elements,
A matrix structure is used that corresponds to each display element, and this is called an active matrix.
ところで、このような薄膜トランジスタにおいては、ゲ
ート絶縁膜に使用する＃質によってその特性が大きく影
響されるもので、通常、ＰＣＶＤ別Ｏｘ膜（Ｘは１．０
〜２．０の間の値）が良く用いられている。コ（Ｄ Ｐ
ＣＶＤＳ ｉＯｘ ｐｌｔｉ、一般ニスハッタ５１ｏＸ
や蒸着５ｌＯｘに比べてステップカバレージが良好でピ
ンホール密度が低いという特長を備えている。By the way, the characteristics of such thin film transistors are greatly affected by the quality used for the gate insulating film, and usually a PCVD Ox film (X is 1.0
-2.0) are often used. Ko (D P
CVDS iOx plti, general nishatta 51oX
It has the features of better step coverage and lower pinhole density than 5lOx or vapor-deposited 5lOx.
したがって、ＰＣＶＤＳ ｉｏｘ膜を上述したＣｄ８ｅ
薄膜トランジスタ（第１図参照）のゲート絶縁膜３に用
いると、アクティブマトリクスにおけるゲート短絡を極
めて少なくすることができる。しかしながら、シランガ
ス（５ｉＨ４）と亜酸化窒素（Ｎ２０）または酸素（０
）ガスの分解から得られるＰＣＶＤＳ ｆｏｘ膜は次の
反応から生成されるために膜中に多量の水分あるいは水
素を含んでいる。Therefore, the PCVDS iox film is
When used in the gate insulating film 3 of a thin film transistor (see FIG. 1), gate short circuits in the active matrix can be extremely reduced. However, silane gas (5iH4) and nitrous oxide (N20) or oxygen (0
) The PCVDS fox film obtained from gas decomposition contains a large amount of water or hydrogen in the film because it is produced from the following reaction.
１、ＳｉＨ＊＋４Ｎ２０→Ｓ Ｉ０２＋２Ｈ１ｌＯ＋４
Ｎ２またはＳ ｉＨ４＋２Ｎ２０→５１０２＋２Ｈｚ＋
２Ｎ２２、ＳｉＨ４＋２０ｇ→Ｓ ｉＯｇ ＋２Ｈ２０
またはＳ １Ｈ４−４−０２→Ｓ １０２−１−２Ｈｇ
このため、従来のＳ ｉＨ＋の分解よ９得られる（ Ｐ
ＣＶＤＳ ｆｏｘ膜は電子のトラップ密度が高く、これ
をＣｄＳｅ薄膜トランジスタのゲート絶縁膜として用い
た場合、オン電流が小さくかつその減衰が大きいという
欠点があった。1, SiH*+4N20→S I02+2H11O+4
N2 or SiH4+2N20→5102+2Hz+
2N22, SiH4+20g → SiOg +2H20
or S 1H4-4-02→S 102-1-2Hg
Therefore, compared to the conventional decomposition of SiH+, 9 is obtained (P
The CVDS fox film has a high electron trap density, and when it is used as a gate insulating film of a CdSe thin film transistor, it has the disadvantage that the on-current is small and its attenuation is large.
本発明は、以上の点に鑑み、かかる従来の欠点を除去す
るためになされたものであり、相互コンダクタンスが大
きく安定でゲート短絡の極めて少ない薄膜トランジスタ
の製造方法を提供するものである。In view of the above points, the present invention has been made in order to eliminate such conventional drawbacks, and provides a method for manufacturing a thin film transistor with large and stable mutual conductance and with extremely few gate short circuits.
すなわち、本発明は、８ｉＨ４，ＳｉｍＨａ （ジシラ
ン）等のシラン系カスの分解よ９得られるＰＣＹＤＳ
ｉｏｘ膜をゲート絶縁膜として用いる薄膜トランジスタ
において、前記ＰＣＶＤ８ｉ０ｘＪｌｄｌｆを４００℃
以上の酸化軍団中でアニールすることＫよシ、その膜の
抵抗が著しく増大することに基づいている。以下に実施
例を示しながら本発明の詳細な説明する。That is, the present invention provides PCYDS obtained by decomposing silane-based scum such as 8iH4, SimHa (disilane), etc.
In a thin film transistor using an iox film as a gate insulating film, the PCVD8i0xJldlf is heated at 400°C.
This is due to the fact that annealing in an oxidizing force significantly increases the resistance of the film. The present invention will be described in detail below with reference to Examples.
この実施例では、第１図に示したＣｄ５ｑ薄膜トランジ
スタのゲート絶縁膜３を形成するに際し、基板温度２５
０〜３５０℃、ＳｉＨ４流量２０ＣＣ／分、 ＮＩＯ流
量１０〜２０ＣＣ贋、高周波電力１０Ｗ、圧力１０６〜
０．１Ｔｏｒｒノ成膜条件でＰＣＶＤＳｌＯｘ ％を堆
積した３−
後、このＰＣＶＤＳ１０４を酸化軍団中でアニールしτ
ゲート絶縁層を形成したものである。第２図はこの酸化
雰囲気アニールの前後におけるＰＣＶＤＳｌＯｘ膜の比
抵抗を示し、図中Ａはアニール前の特性を、Ｂはアニー
ル後の特性をそれぞれ示している。同図から明らかなよ
うに、アニール前のＰＣＶＤ！９ｉＯｘ膜の比抵抗Ｃ特
性Ａ）は ３×１００・儒であるが、これを酸化雰囲気
中で４５０℃でアニールすると比抵抗（特性Ｂ）は１０
Ω・ｍ以上となシ、この酸化雰囲気中のアニールによ
ってＰＣＶＤＳ １０ｘ膜の絶縁性が改善されることが
判明した。In this example, when forming the gate insulating film 3 of the Cd5q thin film transistor shown in FIG.
0~350℃, SiH4 flow rate 20CC/min, NIO flow rate 10~20CC fake, high frequency power 10W, pressure 106~
After depositing 3-% of PCVDSlOx under film formation conditions of 0.1 Torr, this PCVDS104 was annealed in an oxidation layer to τ.
A gate insulating layer is formed. FIG. 2 shows the specific resistance of the PCVDSlOx film before and after annealing in an oxidizing atmosphere, where A shows the characteristics before annealing and B shows the characteristics after annealing. As is clear from the figure, PCVD before annealing! The resistivity C characteristic A) of the 9iOx film is 3 x 100 F, but when it is annealed at 450°C in an oxidizing atmosphere, the resistivity (characteristic B) becomes 10.
It has been found that annealing in this oxidizing atmosphere improves the insulation properties of the PCVDS 10x film when the resistance is Ω·m or more.
次に、このようにして作成したＰＣＶＤＳ ｉＯｘ ｇ
を上述したＣｄ８ｅ薄膜トランジスタのゲート絶縁膜３
（第１図参照）に用いてその特性を調べた結果を菓３図
に示す。第３図はゲート電圧ＶＧをパラメータとしたと
きのドレイン電圧ＶＤに対するドレイン電流ＩＤの特性
を示し、酸化雰囲気中でのアニールを施さないＰＣＶＤ
Ｓ ｉ ０ｘ膜をゲート絶縁膜に用いたＣｄＳｅ薄膜ト
ランジスタでは、同図の特性Ｉ（ＶＧ−２０Ｖ）に示す
ように、オン電４−
流ＩＯＮが１μＡ以下と小さく、オン／オフ比は１０以
下である。これはゲート電界によシその５１０ｘ／Ｃｄ
Ｓｅ界面に誘起された電子がゲー）８ｉ０ｘ中に多数存
在するトラップに捕かくされて有効なキャリアとならな
いためである。一方、アニールを施したＰＣＶＤＳ直Ｏ
ｘｇを用いたＣｄ５ｅｉ膜トランジスタは、第３図の特
性ＩＩ （Ｖａ＝２０Ｖ）に示すように、オン電流ＩＯ
Ｎが８０〜１００μＡと大きく、オン／オフ比は１０〜
１０が得られた。酸化雰囲気中でのアニールの効果はＰ
ＣＶＤＳ ｉ０ｘ膜中の５ｉ−Ｈ結合をＳｉ −０結合
に変えて膜中の水分を減少し、トラップ密度の低減と膜
抵抗の増大をもたらすことにあると考えられる。なお、
第３図中■はゲート電圧ＶＧをＯＶとし、ＰＣＶＤＳ盪
ＯＸ膜にアニールを施したときと施さないときの特性を
示している。Next, the PCVDS iOx g created in this way
The gate insulating film 3 of the Cd8e thin film transistor described above
(See Figure 1) to investigate its properties, and Figure 3 shows the results. Figure 3 shows the characteristics of drain current ID with respect to drain voltage VD when gate voltage VG is used as a parameter, and shows the characteristics of PCV without annealing in an oxidizing atmosphere.
In a CdSe thin film transistor using a Si 0x film as the gate insulating film, as shown in characteristic I (VG-20V) in the same figure, the on-current current ION is small at less than 1 μA, and the on/off ratio is less than 10. be. This is due to the gate electric field of 510x/Cd
This is because the electrons induced at the Se interface are trapped by the many traps present in Ge)8i0x and do not become effective carriers. On the other hand, annealed PCVDS direct O
As shown in characteristic II (Va=20V) in FIG. 3, the Cd5ei film transistor using
N is large at 80-100 μA, and on/off ratio is 10-10
10 was obtained. The effect of annealing in an oxidizing atmosphere is P
It is thought that this is because the 5i-H bonds in the CVDS i0x film are changed to Si-0 bonds to reduce the water content in the film, resulting in a reduction in trap density and an increase in film resistance. In addition,
3 shows the characteristics when the gate voltage VG is OV and when the PCVDSOX film is annealed and when it is not annealed.
なお、本発明は、上述した実施例に限定されるものでは
なく、ＰＣＶＤＳ ｉＯｘ膜を４００℃以上の酸化雰囲
気中でアニールしても上記実施例と同様の効果が得られ
るものである。このとき、アニール処理の上限温度は、
基板の軟化温度によって決められ、基板が例えばガラス
の場合は約６００℃程度である。才た、本発明は、Ｃｄ
Ｓｅ薄膜トランジスタ以外にＴｅやアモルファス８１な
どの半導体膜を用いた薄膜トランジスタのゲート絶縁膜
として用いるＰＣＶＤＳ ｉ Ｏｘ膜にも適用したシ、
また薄膜トランジスタの構造も第１図に示した構造以外
のものであっても同様に適用することができるものであ
る。Note that the present invention is not limited to the embodiments described above, and the same effects as in the embodiments described above can be obtained even if the PCVDS iOx film is annealed in an oxidizing atmosphere at 400° C. or higher. At this time, the upper limit temperature of the annealing treatment is
It is determined by the softening temperature of the substrate, which is about 600° C. if the substrate is made of glass, for example. The present invention is based on Cd
In addition to Se thin film transistors, this technology has also been applied to PCVDS iOx films used as gate insulating films for thin film transistors using semiconductor films such as Te and amorphous 81.
Moreover, even if the structure of the thin film transistor is other than that shown in FIG. 1, it can be similarly applied.
以上説明したように、本発明によれば、 ＰＣＶＤＳｉ
Ｏｘ膜をゲート絶縁膜として用いる薄膜トランジスタに
おいて前記ＰＣＶＤｉ９１０ｘ膜の絶縁性を高めかつ半
導体膜界面とのトラップ密度を低減することができるの
で、ゲート短絡の極めて少ない、しかも相互コンダクタ
ンスの大きい安定な薄膜トランジスタが得られ、特にア
クティブマトリクス岨
（１に適用してすぐれた効果がある。As explained above, according to the present invention, PCVDSi
In a thin film transistor using an Ox film as a gate insulating film, it is possible to improve the insulation properties of the PCVDi910x film and reduce the trap density with the semiconductor film interface, resulting in a stable thin film transistor with extremely few gate short circuits and high mutual conductance. It is particularly effective when applied to active matrix filters (1).
第１図はＣｄＳｅ薄膜トランジスタの基本構造を示す断
面図、第２図は本発明の一実施例に供する酸化雰囲気ア
ニール前後のＰＣＶＤＳ ｉｏｘ ％の比抵抗の特性を
示す図、第３図は従来によるＣｄ８ｅ薄膜トランジスタ
のゲート絶縁膜にＰＣＶＤ８１０ｘ膜をそのまま用いた
場合と本発明による酸化雰囲気中でアニールした抜用い
た場合のＣｄＳｅ薄膜トランジスタの特性を対比して示
した図である。
１＠・・・絶縁基板、２・・・拳ゲート電極、３・・参
〇ゲート絶縁膜、４・―・＊ＣｄＳｅＭ％５・・・・ソ
ース電極、６・・Φ・ドレイン電極。
特許出願人 伊勢電子工業株式会社
代理人 山川政樹（ほか２名）Figure 1 is a cross-sectional view showing the basic structure of a CdSe thin film transistor, Figure 2 is a diagram showing the specific resistance characteristics of PCVDS iox % before and after annealing in an oxidizing atmosphere used in an embodiment of the present invention, and Figure 3 is a diagram showing the resistivity characteristics of a conventional Cd8e thin film transistor. FIG. 3 is a diagram comparing the characteristics of a CdSe thin film transistor when a PCVD810x film is used as it is as a gate insulating film of the thin film transistor, and when it is used after being annealed in an oxidizing atmosphere according to the present invention. 1@...Insulating substrate, 2...Fist gate electrode, 3...3 Gate insulating film, 4...*CdSeM%5...Source electrode, 6...Φ・Drain electrode. Patent applicant: Ise Electronics Industry Co., Ltd. Agent: Masaki Yamakawa (and 2 others)
Claims (1)
Ｏｘ膜をゲート絶縁膜として用いる薄膜トランジスタに
おいて、前記ゲート絶縁膜を４００℃以上の酸化雰囲気
中でアニールすることを特徴とする薄膜トランジスタの
製造方法。Plasma CVD obtained by decomposition of silane gas
A method for manufacturing a thin film transistor using an Ox film as a gate insulating film, characterized in that the gate insulating film is annealed in an oxidizing atmosphere at 400° C. or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11905784A JPS60263437A (en) | 1984-06-12 | 1984-06-12 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11905784A JPS60263437A (en) | 1984-06-12 | 1984-06-12 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60263437A true JPS60263437A (en) | 1985-12-26 |
Family
ID=14751835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11905784A Pending JPS60263437A (en) | 1984-06-12 | 1984-06-12 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60263437A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0264774A2 (en) * | 1986-10-23 | 1988-04-27 | International Business Machines Corporation | Improved post-oxidation anneal of silicon dioxide |
| JPH0284768A (en) * | 1988-09-21 | 1990-03-26 | Nec Corp | Manufacture of solid-state image sensing element |
| JPH02234472A (en) * | 1989-03-08 | 1990-09-17 | Sony Corp | Manufacture of thin film transistor |
-
1984
- 1984-06-12 JP JP11905784A patent/JPS60263437A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0264774A2 (en) * | 1986-10-23 | 1988-04-27 | International Business Machines Corporation | Improved post-oxidation anneal of silicon dioxide |
| JPH0284768A (en) * | 1988-09-21 | 1990-03-26 | Nec Corp | Manufacture of solid-state image sensing element |
| JPH02234472A (en) * | 1989-03-08 | 1990-09-17 | Sony Corp | Manufacture of thin film transistor |
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