JPH0855988A - Formation of gate insulation film - Google Patents

Abstract

PURPOSE:To reduce shift of a flat band voltage without performing thermal treatment after formation of a gate insulation film by forming a gate insulation film by a plasma process on a semiconductor substrate by setting a substrate temperature at a specified temperature range. CONSTITUTION:In a formation method of a gate insulation film 26 by a low temperature, the gate insulation film 26 is formed by setting a temperature at a temperature which is specified and lower than a conventional film formation temperature, that is, a substrate temperature. According to the method, a film is formed by a plasma process on a semiconductor substrate 2 by setting a substrate temperature at a temperature range exceeding 100 deg.C and less than 250 deg.C. A gate electrode 27G is applied and formed on the gate insulation film 26 between a source region and a drain region 24S, 24D. Thereby, it is possible to neutralize positive charge caused by defect and impurities in the gate insulation film 28 and to make a flat band voltage which is close to negative close to an OV side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called M type insulated gate field effect transistor having a gate insulating film.
The present invention relates to a method for forming a gate insulating film, which is suitable when applied to an integrated circuit having a thin film transistor (hereinafter referred to as a TFT) having an IS structure or a bulk type MIS transistor as a circuit element.

[0002]

2. Description of the Related Art For example, in an active matrix type liquid crystal display device, a device in which its switching element is composed of a TFT is widely used. In this case, the TFT is generally mounted on a substrate having a low melting point or low heat resistance such as borosilicate glass or a plastic substrate.
Therefore, the formation of this TFT,
Therefore, the gate insulating film is formed at a low temperature.
As a method for forming the gate insulating film, there has been proposed, for example, a plasma CVD (chemical vapor deposition) method in which the substrate temperature is 600 ° C. to 300 ° C. for forming the film.

However, according to the previous knowledge, when the film forming temperature, that is, the substrate temperature, is lowered in the formation of the gate insulating film, the MIS having the desired characteristic is accompanied with this.
It becomes difficult to obtain a transistor. For example, in the n-channel MIS transistor, this is a depletion type operation, and in the p-channel MIS transistor, the phenomenon of increasing the threshold voltage V _th that does not turn on even when a predetermined negative voltage is applied occurs. There is a problem in integrating a circuit using both transistors.

This phenomenon is considered to be due to positive charges due to crystal defects and impurities in the gate insulating film. This positive charge is due to a dunk ring bond (unbonded hand) of Si in, for example, SiO ₂ of the gate insulating film. ) Is believed to be due to. Then, when this positive charge exists near the interface between the gate insulating film and the semiconductor, the flat band voltage moves, which causes the above-described depletion of the n-channel MIS transistor and the on-voltage of the p-channel MIS transistor. It is expected to increase.

Such a shift of the flat band voltage is acceptable when the operating voltage of the MIS transistor is relatively large, for example, about ± 20 V, for example, a shift of the flat band voltage of about +4 V is acceptable. However, in the transition to low voltage driving, for example, ± 5 V, which has been increasingly demanded in recent years, such a shift of the flat band voltage becomes fatal.

As a method for solving this problem, there is proposed a post-annealing method in which after the gate insulating film is formed, a heat treatment is performed in an oxygen atmosphere such as the air to compensate for the defects.
However, even with this method, it is not always possible to make sufficient improvements regarding the shift of the flat band voltage.

[0007]

According to the present invention, the shift of the flat band voltage can be reduced without performing heat treatment after the above-mentioned gate insulating film is formed, and the heat treatment is performed after forming the gate insulating film. The present invention provides a method for forming a gate insulating film, which can reduce the shift of the flat band voltage more than ever before.

That is, according to the present invention, the positive charge due to defects and impurities in the gate insulating film is neutralized, and the flat band voltage approaching the negative is brought close to 0 V to depletion type in the n-channel MIS transistor. To the enhancement type by avoiding the transition to p-channel M
In the IS transistor, the threshold voltage V _th is prevented from increasing and a reliable operation can be performed. For example, low voltage driving in a driving circuit of a liquid crystal display is enabled. In addition, by simultaneously improving the characteristics of both conductivity type channels, for example, a complementary MIS transistor C formed of MIS transistors of both conductivity type channels is used.
MIS facilitates circuit integration such as formation of so-called CMOS.

[0009]

According to the present invention, in the above-described method for forming a gate insulating film at a low temperature, the gate insulating film is set at a temperature lower than a conventional film forming temperature, that is, a substrate temperature, and specified. Film is formed.

In the first aspect of the present invention, a gate insulating film is formed on a semiconductor substrate by a plasma process by selecting the substrate temperature in a temperature range higher than 100 ° C. and lower than 250 ° C.

According to a second aspect of the present invention, the plasma process for forming the gate insulating film in the above-described method of the present invention is a film forming method using a remote plasma method. The remote plasma method is a plasma CVD method in which a plasma generating portion and a film forming portion, that is, an arrangement position of a film formation semiconductor substrate are separated.

In the third aspect of the present invention, heat treatment at 200 ° C. or higher and 400 ° C. or lower is performed after the gate insulating film is formed.

In a fourth aspect of the present invention, the above-mentioned semiconductor is a polycrystalline semiconductor, and the gate insulating film is formed by each of the above-mentioned methods of the present invention.

In a fifth aspect of the present invention, the above-mentioned semiconductor is an amorphous semiconductor, and a gate insulating film is formed by each of the above-mentioned methods of the present invention.

In addition to the case where the semiconductor substrate has a bulk structure in which the whole is made of a semiconductor, a thin film semiconductor layer, that is, the above-described fourth and fifth semiconductor layers is formed on, for example, an insulating or semi-insulating substrate. In each of the present inventions, the term includes a substrate having a structure in which a polycrystalline semiconductor layer or an amorphous semiconductor layer is formed.

[0016]

According to the above-mentioned method of the present invention, the positive charge due to the defects and impurities in the gate insulating film can be neutralized, and the flat band voltage which is negative can be brought close to 0V.

[0017]

EXAMPLES In the present invention, a gate insulating film is formed on a semiconductor substrate by a plasma process by selecting the substrate temperature in the range of more than 120 ° C. and less than 250 ° C.

The plasma process for forming the gate insulating film is preferably a remote plasma CVD method, and an apparatus for performing this is disclosed, for example, in Japanese Patent Laid-Open No. 5-21393 proposed by the present applicant. As described above, the plasma generation part and the arrangement part of the semiconductor substrate are separated from each other, and the mesh-like electrode is arranged between the two, thereby shielding the plasma and electrically neutralized excited atomic species with respect to the semiconductor substrate. Alternatively, a remote plasma CVD apparatus which irradiates molecular species can be used.

According to this remote plasma CVD apparatus, it is possible to reduce plasma damage to the surface of the semiconductor substrate, and thus to the interface with the gate insulating film formed on the semiconductor substrate, and the interface level is small. Generation of positive charges due to the above-mentioned defects can be suppressed to a small level.

FIG. 1 shows a schematic configuration diagram of an example of a remote plasma CVD apparatus. In this example, a parallel plate type electrode configuration is used, but the configuration is not limited to this configuration.

In this example, in the chamber 1, a semiconductor substrate 2 on which a gate insulating film is to be formed is arranged, and a plasma generating portion 4 is arranged opposite to the substrate arrangement portion 3. The plasma generator 4 includes a high frequency (RF) generator 5
From which the high frequency power of, for example, 13.56 MHz is applied, and the first and second mesh-shaped electrodes G ₁ and G ₂ are arranged facing each other.
The electrode G ₁ is composed of a flat plate mesh electrode, the electrode G ₂ is composed of a flat bag-shaped mesh electrode, and predetermined voltages V _G1 and V _G2 are applied to the respective electrodes G ₁ and G ₂ .

The arrangement part 3 of the semiconductor substrate 2 is provided with a heating means 7 so that the semiconductor substrate 2 can be set to a predetermined substrate temperature, that is, in the present invention, a temperature range of more than 100 ° C. and less than 250 ° C. Done.

The chamber 1 has a plasma generating portion 4
The gas inlet 8 is formed in the vicinity of, and the exhaust port 9 is formed in the vicinity of the substrate placement unit 3, for example. Further, the gas introduction port 10 is provided in the mesh electrode G ₂ . Then, oxygen O ₂ and helium He are supplied from the gas introduction port 8, and SiH ₄ and He are supplied from the gas introduction port 10.

In this structure, a discharge is generated by applying RF power between the RF electrode 6 and the substrate arrangement portion 3. In this case, since the mesh electrodes G ₁ and G ₂ are present between the _two , By applying positive predetermined voltages V _G1 and V _G2 to the substrate placement unit 3 to these, plasma generated by this discharge is limited to the RF electrode 6 side by the mesh electrodes G ₁ and G ₂ . That is, the charged particles of electrons and positive and negative ions are blocked from the substrate placement unit 3. In this way, the board placement unit 3
The semiconductor substrate 2 arranged on the substrate is irradiated with neutral radicals, that is, only electrically neutral excited atomic species or excited molecular species, respectively, so that the film formation surface of the semiconductor substrate 2 and the film formation thereon are charged by charged particles. In this example, a gate insulating film made of SiO ₂ is formed without being damaged.

Since the electron density in the plasma is almost proportional to the high frequency power, in order to further suppress the plasma damage to the substrate surface, the high frequency power should be applied to the lowest power in the range where the discharge can be maintained. desirable.

The deposition rate is basically generated in the gas phase.
Electrically neutral precursor SiO_X* (Reaction precursor
Body) should be deposited on the film formation surface of the substrate 2, so that the mesh
Electrode G ₁And G₂ The charged particles are blocked by
Of normal plasma CVD
There is no difference from the case.

The gas species to be used are disilane Si _{2 in} addition to the above-mentioned monosilane SiH ₄ as a silicon raw material.
Any high order silane gas such as H ₈ may be used.
Further, as the oxidizing gas, nitric oxide gas such as N ₂ O can be used in addition to the above O ₂ .

Further, as described above, in addition to He, an inert gas such as Ar can be mixed as a diluent gas. Further, in order to increase the hydrogen concentration in the SiO ₂ film formed as the gate insulating film, H ₂ gas may be added as described above.

The gas pressure in the chamber 1 during the reaction is several tens Torr to 0.1 Torr in the case of high frequency glow discharge.
Discharge becomes easy to be maintained by setting it as a grade.

The heating means 7 may be, for example, a resistance type heater, high frequency induction heating or radiation type heating using an infrared lamp or the like depending on the structure of the substrate 2 and the structure of the substrate disposing portion 3.

An example of forming a TFT, that is, a thin film type MIS transistor by forming a gate insulating film using the method of the present invention will be described with reference to the process charts of FIGS. In this case, when a TFT made of polycrystalline silicon is formed, first, as shown in FIG. 2, B (boron) -doped hydrogen-containing amorphous Si (a) is formed on the glass substrate 21.
The first semiconductor layer 22 of -Si: H, B) or P (phosphorus) -doped hydrogen-containing amorphous Si (a-Si: H, P) was formed by the CVD method. Other portions of the first semiconductor layer 22 are removed by etching, leaving the portions to be the source and drain regions of the TFT finally obtained by photolithography.

As shown in FIG. 3, a portion of the first semiconductor layer 22 where the semiconductor layer 22 is removed between the formation regions of the source region and the drain region is buried and finally the channel of the TFT is entirely formed. Second non-doped hydrogen-containing amorphous Si (a-Si: H) constituting the formation region
The semiconductor layer 23 is formed. In this way, the semiconductor substrate 2 is constructed.

Then, the second semiconductor layer 23 is crystallized by excimer laser annealing for irradiating the second semiconductor layer 23 with excimer laser light, and as shown in FIG. Second semiconductor layer 2
Impurities are diffused to 3 to form the source and drain regions 24S and 24D by the first semiconductor layer 22 and the second semiconductor layer 23 thereon. Then, the channel formation region 25 of the non-doped second semiconductor layer 23 is formed between the regions 24S and 24D thus formed.

As shown in FIG. 5, a gate insulating film 26 is formed by the method of the present invention. The gate insulating film 26 is formed by the remote plasma CVD apparatus shown in FIG. 1 within a temperature range of the substrate temperature higher than 100 ° C. and lower than 250 ° C.

As shown in FIG. 6, photolithography is performed on the gate insulating film 26 to open electrode contact windows on the source and drain regions 24S and 24D, and on the source and drain regions 24S and 24D through these electrode contact windows. The source and drain electrodes 27S and 27D are ohmic-contacted with each other, and the source region and the drain region 24S are contacted with each other.
And the gate electrode 27 on the gate insulating film 26 between 24D
G is deposited. The electrodes 27S, 27D and 27G can be formed simultaneously by, for example, depositing Al over the entire surface and patterning by photolithography.

The TFT formed in this manner is used at 270 ° C.
After annealing in air for 1 hour, drain current I
_{The D} -gate voltage V _G characteristic was measured. FIG. 7 shows a drain current _ID -gate voltage V of a p-channel TFT in which a gate insulating film is formed at a substrate temperature of 200 ° C. by the method of the present invention.
_G characteristics are shown.

FIG. 8 shows a p-channel TFT in the case where the same substrate temperature for forming the gate insulating film is used at 250 ° C. by the method described in FIGS.
The drain current I _D - a gate voltage V _G characteristics.

Both of FIGS. 7 and 8 show the case where the channel width W and the channel length L are each 10 μm and the drain voltage V _{D is} −1V.

As is clear from comparing FIGS. 7 and 8, the TFT obtained by forming the gate insulating film according to the present invention when the substrate temperature is 200 ° C. in the temperature range of more than 100 ° C. and less than 250 ° C. Is a TFF due to the gate insulating film formed by the method of the present invention, as compared with the case where the flat band voltage at which the drain region _ID becomes minimum approaches almost 0V.
Then, as shown in FIG. 8, the flat band voltage is largely negatively shifted.

FIG. 9 shows the dependence of the flat band voltage on the formation of the gate insulating film SiO ₂ on the substrate temperature, which shows that it has the same tendency as the single crystal silicon MIS. That is, it is understood that the control of the film forming temperature of SiO ₂ is important for the TFT characteristics, and the flat band voltage shift to the negative becomes small at less than 250 ° C.

Further, the characteristics of the gate insulating film according to the method of the present invention will be considered. For this purpose, a SiO ₂ film as a gate insulating film was formed on a boron-doped p-type Si substrate of 10 ¹⁵ atoms / cm ³ by a remote plasma CVD apparatus shown in FIG. It was formed. Then, Al was vapor-deposited on this to form a gate electrode to form a MOS capacitor. In MOS diode in this configuration, shown in flat band voltage in a state of not performing heat treatment after the deposition of the SiO ₂ film, the substrate temperature dependence of the time of SiO ₂ film formation in Figure 10.

According to FIG. 10, the negative shift of the flat band voltage is small in the temperature range of more than 100 ° C. and less than 250 ° C. when the SiO ₂ film is formed. It can be close to 0, that is, its absolute value can be reduced to 250 ° C.
The flat band voltage shifts to a negative value when the value exceeds, and it can be seen from this that depletion is achieved when forming an n-channel MIS transistor. The negative shift of the flat band voltage is due to the oxide film charge N _eff .

The large shift of the flat band voltage reflects the large number of defect levels which become hole traps in the insulating film at and near the SiO ₂ / Si interface. It is shown that these defects are reduced in the SiO ₂ gate insulating film formed at the substrate temperature lower than 250 ° C.

On the other hand, the heat treatment after film formation, that is, so-called post annealing will be considered. This post-annealing has an effect of reducing water content or OH groups in the SiO ₂ film. FIG. 11 shows the temperature dependence of annealing of the H ₂ O + OH amount (arbitrary unit) in the SiO ₂ film. In this case, thickness 1
The deposition temperature (substrate temperature) of the SiO ₂ film of 00 nm is 200
It was formed at 0 ° C., and annealing was performed in the atmosphere for 15 minutes. The amount of H ₂ O + OH in the film decreases as it is annealed at a higher temperature. Therefore, the improvement of the bulk properties of SiO ₂ is
It can also be performed by selecting the temperature of post-annealing.

FIG. 12 shows two MOS diodes.
It shows the dependence of the oxide film charge density on the substrate temperature at the time of forming the SiO ₂ film when annealed in the atmosphere at 70 ° C. for 1 hour. In this case, the oxide film charge N _eff per unit area
The following equation (Equation 1) was used as the definition of

[0046]

[ _Equation 1] N _eff = C _OX · (φ _MS −V _FB ) / eS

Here, C _OX is the capacitance of the MOS diode −
The capacitance of the oxide film obtained from the voltage characteristics (C-V characteristics), V _FB is the flat band voltage, φ _MS is the difference between the work function of the gate electrode and the electron affinity of Si, e is the elementary charge, and S is the gate electrode. Area.

By this annealing, the oxide film charge density in the temperature region where the oxide film charge was originally small was
Furthermore, a reduction of about one digit is recognized. This indicates that the annealing further reduced the defect density due to the hydrogenation effect and the like. Also in this case, the oxide film charge density is lower when the film is formed at less than 250 ° as compared with when the film is formed at 250 ° C. or more. However, if the temperature is 180 ° C. or lower, the oxide film charge density tends to increase again.

Similarly, a SiO ₂ film was formed on the p-type Si substrate by the above-mentioned remote plasma CVD method at a substrate temperature of 10
A MOS capacitor having a metal film formed thereon was formed by changing the temperature range from 0 ° C to 280 ° C. FIG. 13 shows the substrate temperature dependence of the obtained SiO ₂ / Si interface state density D _it during the formation of the insulating film. This SiO ₂ / Si
The interface state density D _it is also 1 like the oxide film charge density N _eff.
It can be seen that the reduction can be achieved when forming the SiO ₂ film in the temperature range of more than 00 ° C and less than 250 ° C.

As is clear from the above, S
In forming a gate insulating film such as an iO ₂ film, when the substrate temperature is selected in a temperature range higher than 100 ° C. and lower than 250 ° C., it is possible to reduce the charge of the oxide film. Therefore, although the annealing after the film formation is not necessarily performed, the post-annealing after the film formation can further reduce the oxide film charge. However, even if this post-annealing is not particularly provided, in the actual manufacturing of TFTs and the like, in the process after the formation of the gate insulating film, many post-annealing processes such as annealing such as activation treatment after ion implantation are performed. Since this involves steps, the annealing after the above-described formation of the gate insulating film is simultaneously performed during this heating.

In the above example, the case where the semiconductor substrate is Si was mainly described, but the semiconductor substrate may be any one of Ge, SiGe compound, and SiGe-based superlattice thin film. Further, these may be any one of single crystal, polycrystal, and amorphous, and may have a structure in which they are formed on the substrate or a bulk thereof.

The gate insulating film is made of SiO 2.₂If it is
Was mainly described, but SiO₂Limited to
Not formed, but SiON formed below 600 ° C_y, S
iO _xN_y, Or stack of these, stack of superlattice structure
Etc. can be adopted.

The method of forming the insulating film is not limited to the remote plasma method described above, but can be applied to the case where there is a concern about plasma damage. That is, a normal plasma CVD method such as direct current (DC plasma, RF plasma, microwave plasma, ECR (electron cyclotron resonance) plasma, helicon plasma, etc.), RF sputtering method or the like can be used.

The TFT is not limited to the so-called top gate type structure in which the gate insulating film and the gate electrode are formed in the upper layer of the channel forming region 25 shown in FIG. 6, but the gate insulating film and the channel are formed on the gate electrode. The present invention can also be applied to a so-called bottom gate type structure in which a region is formed.

[0055]

According to the above-mentioned method of the present invention, positive charges due to defects and impurities in the gate insulating film are neutralized,
It was possible to bring the negative flat band voltage closer to the 0 V side.

That is, in the present invention, the positive charge resulting from defects and impurities in the gate insulating film is neutralized, and the negative flat band voltage is brought closer to 0 V to depletion type in the n-channel MIS transistor. To the enhancement type by avoiding the transition to p-channel M
In the IS transistor, the threshold voltage V _th is prevented from increasing and a reliable operation can be performed. For example, low voltage driving in a driving circuit of a liquid crystal display is enabled. Further, by simultaneously improving the characteristics of both conductivity type channels, the circuit integration can be facilitated, for example, formation of complementary MIS transistors, that is, CMIS, by MIS transistors of both conductivity type channels.

[Brief description of drawings]

FIG. 1 Remote plasma CVD implementing the method of the invention.
It is a schematic block diagram of an example of an apparatus.

FIG. 2 is a cross-sectional view of a step in an example manufacturing method in which the method of the present invention is applied to the manufacture of a TFT.

FIG. 3 is a sectional view of a step of an example manufacturing method in which the method of the present invention is applied to the manufacture of a TFT.

FIG. 4 is a sectional view of a step of an example manufacturing method in which the method of the present invention is applied to the manufacture of a TFT.

FIG. 5 is a sectional view of a step of an example manufacturing method in which the method of the present invention is applied to the manufacture of a TFT.

FIG. 6 is a cross-sectional view of an example in which the method of the present invention is applied to manufacture of TFT.

FIG. 7 is a graph showing a T having a gate insulating film formed by the method of the present invention.
FT of the drain current I _D - a gate voltage V _G characteristic diagram.

FIG. 8 is a graph showing a T having a gate insulating film formed by the method of the present invention.
It is a measurement curve figure which shows the film-forming substrate temperature dependence of the gate insulating film of the flat band voltage of FT.

FIG. 9 is a drain current _ID -gate voltage V _G characteristic diagram of a TFT of a comparative example used for explaining the present invention.

FIG. 10 is a diagram showing the substrate temperature dependency of the flat band voltage of the MOS diode used for explaining the present invention during the formation of the SiO ₂ film.

FIG. 11 is a diagram showing an annealing temperature dependency of OH + H ₂ O concentration.

FIG. 12 is a diagram showing the dependence of the oxide film charge density on the film formation substrate temperature of the gate insulating film.

FIG. 13 is a diagram showing the temperature dependence of the SiO ₂ / Si interface state density D _it of the gate insulating film on the deposition substrate temperature.

[Explanation of symbols]

 1 Chamber 2 Semiconductor Substrate 3 Substrate Arrangement Section 4 Plasma Generation Section 21 Substrate 22 First Semiconductor Layer 23 Second Semiconductor Layer 24S Source Region 24D Drain Region 25 Channel Forming Region 26 Gate Insulating Film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Samejima 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (5)

[Claims] 1. A method for forming a gate insulating film, comprising forming a gate insulating film on a semiconductor substrate in a temperature range of more than 100 ° C. and less than 250 ° C. by a plasma process. 2. The method for forming a gate insulating film according to claim 1, wherein the plasma process for forming the gate insulating film is a film forming method using a remote plasma method. 3. A method for forming a gate insulating film, which comprises performing heat treatment at 200 ° C. or higher and 400 ° C. or lower after forming the gate insulating film. 4. The method of forming a gate insulating film according to claim 1, wherein the semiconductor is a polycrystalline semiconductor. 5. The method of forming a gate insulating film according to claim 1, wherein the semiconductor is an amorphous semiconductor.