CN111052397B - Thin film transistor and method of manufacturing the same - Google Patents

Thin film transistor and method of manufacturing the same Download PDF

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Publication number
CN111052397B
CN111052397B CN201880058156.1A CN201880058156A CN111052397B CN 111052397 B CN111052397 B CN 111052397B CN 201880058156 A CN201880058156 A CN 201880058156A CN 111052397 B CN111052397 B CN 111052397B
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metal oxide
oxide layer
layer
thin film
film transistor
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CN111052397A (en
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菊池亨
大园修司
太田淳
座间秀昭
浅利伸
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Ulvac Inc
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Ulvac Inc
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    • H01L29/772—Field effect transistors
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Abstract

A method for manufacturing a thin film transistor according to an embodiment of the present invention includes forming an active layer over a substrate. The source region and the drain region are formed so as to be electrically connectable to the active layer. A first metal oxide layer made of silicon oxide is formed on the surface of the active layer by plasma CVD. A second metal oxide layer made of aluminum oxide is formed on the surface of the first metal oxide layer by ALD. And forming a gate electrode on the surface of the second metal oxide layer.

Description

Thin film transistor and method of manufacturing the same
Technical Field
The present invention relates to a thin film transistor having a gate insulating film with a multilayer structure and a method of manufacturing the same.
Background
The LTPS thin film transistor (Low Temperature Poly Silicon TFT, low temperature polysilicon thin film transistor) has high mobility and is used for organic EL display devices and liquid crystal display devices. For example, patent document 1 discloses a thin film transistor using LTPS as an active layer.
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2010-98149.
Disclosure of Invention
Problems to be solved by the invention
In general, a thin film transistor using polysilicon (polysilicon) sequentially forms a gate insulating film and a gate electrode on polysilicon. However, when the coverage of the gate insulating film is poor, the gate insulating film cannot be uniformly formed on the polysilicon having the irregularities. Accordingly, leakage current flows between the gate electrode and the polysilicon, and a problem arises in that an image appears on a display device such as mottle.
In view of the above, an object of the present invention is to provide a thin film transistor having high coverage and excellent transistor characteristics, and a method for manufacturing the same.
Solution for solving the problem
In order to achieve the above object, a method for manufacturing a thin film transistor according to an embodiment of the present invention includes forming an active layer over a substrate.
The source region and the drain region are formed so as to be electrically connectable to the active layer.
A first metal oxide layer made of silicon oxide is formed on the surface of the active layer by plasma CVD.
A second metal oxide layer made of aluminum oxide is formed on the surface of the first metal oxide layer by ALD.
And forming a gate electrode on the surface of the second metal oxide layer.
In the above manufacturing method, the first metal oxide layer and the second metal oxide layer are sequentially formed as the gate insulating film. Since the second metal oxide layer is constituted of an aluminum oxide film formed by ALD, a high coverage can be obtained as compared with a gate insulating film using a silicon oxide single film formed by plasma CVD. Thus, leakage current between the gate electrode and the active layer can be effectively prevented, and a thin film transistor with excellent threshold voltage control can be manufactured.
Further, by forming the gate insulating film in a plurality of layers in this manner, the apparent dielectric constant becomes higher than that of a gate insulating film using a silicon oxide single film. Thereby, the electron mobility of the active layer is improved.
May further include: forming a hydrogen-rich intermediate layer between the first metal oxide layer and the second metal oxide layer; and annealing the intermediate layer.
According to this manufacturing method, a large number of hydrogen atoms contained in the hydrogen-rich intermediate layer move to the interface of the active layer and the first metal oxide layer due to annealing. A large number of hydrogen atoms terminate dangling bonds (dangling bonds) existing at the interface, so that the interface state density is lowered. Thus, leakage current between the gate electrode and the active layer can be prevented, and a thin film transistor having excellent switching characteristics can be manufactured.
In addition, according to this manufacturing method, the second metal oxide layer functions as a barrier layer, and hydrogen atoms contained in the first metal oxide layer and the intermediate layer easily move to the interface between the active layer and the first metal oxide layer due to annealing. This can improve the defect repair effect of the interface.
The intermediate layer may be formed by subjecting the first metal oxide layer to hydrogen plasma treatment.
The intermediate layer may be formed by forming a layer of silicon nitride or silicon oxynitride between the first metal oxide layer and the second metal oxide layer.
The step of forming the first metal oxide layer and the step of forming the silicon nitride or silicon oxynitride layer may be performed in the same chamber. In this way, by performing the substrate processing in the same chamber, contamination of the substrate surface accompanied by replacement of the substrate can be prevented. In addition, the time for replacing the substrate and the cost of the machine can be reduced.
The step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere.
By keeping the substrate processing in vacuum all the time in this way, contamination of the substrate surface by gas or air can be prevented.
A thin film transistor according to an embodiment of the present invention includes a gate electrode, an active layer, source and drain regions, and a gate insulating film.
The active layer is made of polysilicon.
The source region and the drain region are electrically connected to the active layer.
The gate insulating film includes a first metal oxide layer and a second metal oxide layer.
The first metal oxide layer is made of silicon oxide and is disposed between the gate electrode and the active layer.
The second metal oxide layer is made of aluminum oxide and is disposed between the first metal oxide layer and the gate electrode.
The gate insulating film may include an intermediate layer between the first metal oxide layer and the second metal oxide layer, and the intermediate layer may include silicon nitride.
The gate insulating film may include an intermediate layer between the first metal oxide layer and the second metal oxide layer, and the intermediate layer may include silicon oxynitride.
The thickness of the intermediate layer may be 3nm to 10 nm.
The intermediate layer functions only as a supply source of hydrogen atoms, and therefore can supply a sufficient amount of hydrogen to the interface at a thickness of 3nm to 10 nm.
Effects of the invention
As described above, according to the present invention, a thin film transistor having high coverage and excellent transistor characteristics and a method for manufacturing the same can be provided.
Drawings
Fig. 1 is a schematic cross-sectional view showing a structure of a thin film transistor according to an embodiment of the present invention.
Fig. 2 is a process cross-sectional view illustrating the method for manufacturing the thin film transistor.
Fig. 3 is a process cross-sectional view illustrating the method for manufacturing a thin film transistor.
Fig. 4 is a schematic view of a plasma CVD apparatus used for manufacturing a thin film transistor according to an embodiment of the present invention.
Fig. 5 is a schematic view of an ALD apparatus used for manufacturing a thin film transistor according to an embodiment of the present invention.
Fig. 6 is a process cross-sectional view illustrating the method for manufacturing a thin film transistor.
Fig. 7 is a process cross-sectional view illustrating the method for manufacturing a thin film transistor.
Fig. 8 is a process cross-sectional view illustrating the method for manufacturing a thin film transistor.
Fig. 9 is a graph showing the results of an experiment for flat band voltages of respective metal oxide thin films.
FIG. 10 shows Al 2 O 3 One experimental result of the CV curve of the film.
FIG. 11 is a diagram showing TEOS-SiO x And Al 2 O 3 An experimental result of the CV curve of the film of the two-layer structure.
Fig. 12 is a graph showing a relationship between the film thickness of the first metal oxide layer of the thin film transistor and the flatband voltage.
Fig. 13 is a graph showing a relationship between a film thickness of the first metal oxide layer of the thin film transistor and hysteresis characteristics.
Fig. 14 is a graph showing a relationship between the film thickness of the first metal oxide layer of the thin film transistor and the interface state density.
Fig. 15 is a schematic cross-sectional view showing a structure of a thin film transistor according to a second embodiment of the present invention.
Fig. 16 is a graph showing a relationship between the film thickness of the intermediate layer of the thin film transistor and the interface state density.
Fig. 17 is a schematic cross-sectional view showing a structure of a thin film transistor according to a third embodiment of the present invention.
Detailed Description
[ outline of LTPS-TFT ]
In the gate insulating film for LTPS, TEOS-SiO is generally used x . And from SiH 4 The use of TEOS-SiO compared to a gate insulating film made of SiO x The gate insulating film of (2) has excellent thin film transistor characteristics. Specifically, TEOS-SiO x The thin film transistor has the characteristics of close to ideal flat band voltage, easier threshold voltage control of the thin film transistor, excellent long-term stability of the thin film transistor characteristics, small defect state density of an interface and the like.
However, TEOS-SiO x The film has a problem that good coverage of the device pattern is not easily obtained. A gate insulating film and a gate electrode are sequentially formed on polysilicon as an active layer in a film structure of a top gate LTPS-TFT. If the coverage of the gate insulating film formed on the polysilicon having irregularities is poor, the gate insulating film cannot be uniformly formed, and a leakage current flows between the gate electrode and the polysilicon, which causes a problem in a display device such as image generation mottle.
In order to increase the aperture ratio of the pixel portion of the display device and to reduce power consumption of peripheral circuits other than the pixels, it is necessary to reduce the operating voltage. In order to cope with these, it is necessary to increase mobility of the thin film transistor, and thus it is necessary to thin the gate insulating film. However, there is a limit in thinning the gate insulating film because thinning the gate insulating film causes an increase in leakage current.
In recent years, therefore, a gate insulating film having excellent transistor characteristics and excellent coverage of irregularities has been attracting attention as a technique required for improving characteristics of a display device.
As an insulating film forming technique excellent in coverage of irregularities, an Atomic Layer Deposition (ALD) method is known. In this method, two or more kinds of source gases are sequentially supplied to the surface of a substrate to form a thin film controlled by a source layer. ALD is a method of forming an insulating film as follows: when the raw material is supplied to the substrate surface, the function of automatically stopping the adsorption reaction in the monolayer is used, and thus the uniform adhesion of the substrate to the irregularities is extremely excellent, and the coverage is almost 100%.
However, when Al is formed by ALD 2 O 3 When the film is evaluated for CV (capacitance-voltage) characteristics, the flatband voltage tends to be greatly shifted to the positive side as will be described later. If hysteresis occurs such that the flat band voltage differs between the positive and negative start voltages in the CV curve measurement, the threshold voltage of the transistor characteristics becomes unstable, and thus cannot be used as a gate insulating film.
In order to solve the above problems, in the present embodiment, the structure and the manufacturing method of the gate insulating film are studied to improve the coverage of polysilicon while suppressing the hysteresis characteristic of the CV curve so as to obtain good transistor characteristics.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
< first embodiment >, first embodiment
Fig. 1 is a schematic cross-sectional view of a thin film transistor 1 according to an embodiment of the present invention.
[ Structure of thin film transistor ]
The thin film transistor 1 according to the present embodiment includes an active layer 11, a source region 14S, a drain region 14D, a gate insulating film 12, and a gate electrode 13.
The thin film transistor 1 is constituted by a top gate thin film transistor in which a gate insulating film 12 is formed so as to cover an active layer 11, a source region 14S, and a drain region 14D formed on a substrate 10, and a gate electrode 13 is formed on the gate insulating film 12.
The structure of each portion of the thin film transistor 1 will be described below.
(active layer)
The active layer 11 is made of polysilicon formed by an insulating film (for example, a silicon oxide film) 10a on the substrate 10, and functions as a channel layer of the thin film transistor 1. Typically, the substrate 10 is a transparent glass substrate, and may be a semiconductor substrate such as a silicon substrate or a resin substrate such as a plastic film. As will be described later, the active layer 11 is formed by crystallizing amorphous silicon formed on the substrate 10 by an annealing treatment. The thickness of the active layer 11 is not particularly limited, and is, for example, 40nm to 50nm.
(Source and drain regions)
The source region 14S and the drain region 14D are formed separately from each other so as to sandwich the active layer 11. As will be described later, the source region 14S and the drain region 14D are formed by implanting impurity ions into, for example, a polysilicon film constituting the active layer 11.
(Gate insulating film)
The gate insulating film 12 is disposed between the active layer 11 and the gate electrode 13, electrically insulates them, and has a function of forming a layer (inversion layer) whose charge is inverted in the active layer 11 by a voltage applied to the gate electrode 13. The gate insulating film 12 has a first metal oxide layer 12A and a second metal oxide layer 12B.
The first metal oxide layer 12A is formed on the substrate 10 in such a manner as to cover the active layer 11, the source region 14S, and the drain region 14D.
The first metal oxide layer 12A is made of silicon oxide (SiO x ) In the present embodiment, the composition is composed of silane (SiH 4 ) TEOS is formed as a film forming material. Thus, the thin film transistor 1 can obtain excellent characteristics such as easier control of threshold voltage, excellent long-term stability of transistor characteristics, and small interface state density. The thickness of the first metal oxide layer 12A can be, for example, 10nm to 120nm.
As a method for forming the first metal oxide layer 12A, plasma CVD (Plasma-enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) described later can be used. As a source gas for plasma CVD, for example, silane (SiH 4 ) Silicon compounds such as Tetraethoxysilane (TEOS). In this embodiment, as a source gas for plasma CVD, TEOS and oxygen (O 2 )。
The second metal oxide layer 12B is formed on the first metal oxide layer 12A. The second metal oxide layer 12B is made of aluminum oxide (Al 2 O 3 ) The composition is formed. As a method of forming the second metal oxide layer 12B, ALD (Atomic Layer Deposition ) may be used. As a raw material gas for ALDVarious aluminum compounds can be used, and in this embodiment, trimethylaluminum (TMA) can be used. In addition, as the reaction gas for ALD, oxygen or ozone (O 3 ) In the present embodiment, the oxidizing gas may be water vapor (H 2 O). The purge gas for ALD is not particularly limited, and in the present embodiment, nitrogen (N 2 )。
ALD is excellent in step coverage and film thickness controllability, and Al produced by ALD 2 O 3 The layer has excellent coverage, and can effectively prevent leakage current. On the opposite side, from Al 2 O 3 When a single layer of the thin film constitutes the gate insulating film, the flatband voltage tends to shift in the positive direction, and thus hysteresis characteristics occur, and there is a possibility that the threshold voltage of the thin film transistor becomes unstable depending on the magnitude of the hysteresis characteristics.
In the present embodiment, the gate insulating film 12 is formed of TEOS-SiO x A first metal oxide layer 12A composed of Al 2 O 3 The second metal oxide layer 12B is a two-layer structure in which two layers are stacked in this order. With this structure, the formation of Al 2 O 3 Hysteresis characteristics caused by the layer and excellent coverage are obtained. Thus, the thin film transistor 1 can prevent leakage current and can control a threshold voltage well.
The thickness of the second metal oxide layer 12B can be, for example, 10nm to 120nm. This can provide excellent coverage while suppressing hysteresis characteristics.
By setting the thickness of the gate insulating film 12 (the sum of the thickness of the first metal oxide layer 12A and the thickness of the second metal oxide layer 12B) to 130nm or less in total, the above-described various effects can be obtained while the thin film transistor 1 is reduced in size.
(Gate electrode)
The gate electrode 13 is constituted by a conductive film formed over the gate insulating film 12. Typically, the gate electrode 13 is formed of a metal single-layer film or a metal multi-layer film such as Al, mo, cu, ti, and is formed by, for example, sputtering. The thickness of the gate electrode 13 is not particularly limited, and is, for example, 200nm to 300nm.
(others)
An interlayer insulating film 15 is formed over the gate insulating film 12 and the gate electrode 13. The interlayer insulating film 15 is a film for maintaining insulation between the electrodes. The interlayer insulating film 15 is made of an electrically insulating material, typically, silicon oxide, silicon nitride, or the like. The thickness of the interlayer insulating film 15 is not particularly limited, and is, for example, 200nm to 500nm.
The thin film transistor 1 also has a source electrode 16S and a drain electrode 16D. The source electrode 16S and the drain electrode 16D penetrate the interlayer insulating film 15 and the gate insulating film 12 and are electrically connected to the source region 14S and the drain region 14D, respectively. The source electrode 16S and the drain electrode 16D are extraction electrodes for connecting the source region 14S and the drain region 14D to a peripheral circuit, not shown.
[ method of manufacturing thin film transistor ]
Next, a method for manufacturing the thin film transistor 1 according to the present embodiment configured as described above will be described. Fig. 2 to 8 are cross-sectional views illustrating respective steps of a method for manufacturing the thin film transistor 1 and schematic cross-sectional views of a film forming apparatus.
(formation of gate electrode)
First, as shown in fig. 2, an insulating film 10a and an amorphous silicon film a are formed on a substrate 10. Typically, the insulating film 10a is made of a silicon oxide film, but may be made of other materials, and may be omitted as needed. The raw material of the amorphous silicon film a is not particularly limited, and if it is formed by, for example, plasma CVD, silane (SiH 4 ) Disilane (Si) 2 H 6 ) And an iso-silicon compound as a raw material gas.
(formation of Gate insulating film)
Next, a heat treatment is performed for crystallizing the amorphous silicon film a formed on the substrate 10. Thereafter, the active layer 11 made of polysilicon is formed into a predetermined shape by patterning.
Next, as shown in fig. 3, a gate insulating film 12 is formed on the substrate 10 so as to cover the surface of the active layer 11. The gate insulating film 12 is formed by a process including a step of forming a first metal oxide layer 12A and a step of forming a second metal oxide layer 12B.
[ first Metal oxide layer Forming Process ]
The first metal oxide layer 12A is formed on the substrate 10 so as to cover the surface of the active layer 11. The first metal oxide layer 12A is formed by plasma CVD. The plasma CVD apparatus is not particularly limited, and in the present embodiment, the plasma CVD apparatus 100 schematically shown in fig. 4 can be used.
The plasma CVD apparatus 100 includes a vacuum chamber 110 and a substrate support table 111 provided inside the vacuum chamber 110. The table 111 has a heater 112 inside. A high-frequency electrode 113 is disposed in the vacuum chamber 110 at a position facing the heater stage 111. The high-frequency electrode 113 has a shower head 114, and a gas diffusion plate 115 for uniformly diffusing the gas introduced from the gas introduction system and a plurality of discharge holes 116 for discharging the gas are provided in the shower head 114. The vacuum chamber 110 is connected to a vacuum exhaust system 120, a power supply system 130 having a high-frequency power supply, a controller 140, and a gas introduction system not shown. The controller 140 controls the heater 112, the power supply system 130, the vacuum exhaust system 120, and the gas introduction system, respectively.
In the present embodiment, as a source gas (CVD gas) for plasma CVD, TEOS and O can be used 2 . TEOS and O 2 The flow ratio of (2) is not particularly limited, and may be, for example, O 2 /TEOS＝50。
The film formation conditions are not particularly limited, and are, for example, the following conditions when the glass substrate size is 730mm×920 mm.
TEOS flow: 360[ sccm ]
O 2 Flow rate: 16000[ sccm ]]
Process pressure: 175 Pa
RF frequency: 27.12[ MHz ]
RF power: 4000[ W ]
Heater temperature: 350 DEG C
[ formation of second Metal oxide layer ]
The second metal oxide layer 12B is formed so as to cover the first metal oxide layer 12A. The second metal oxide layer 12B is formed by ALD. The ALD apparatus is not particularly limited, and in the present embodiment, the ALD apparatus 200 schematically shown in fig. 5 may be used.
The ALD apparatus 200 includes a vacuum chamber 210 and a substrate support table 211 provided inside the vacuum chamber 210. The table 211 has a heater 212 inside. A controller 220 and a gas introduction system and a vacuum exhaust system, not shown, are disposed in the vacuum chamber 210. The controller 220 controls the heater 212, the gas introduction system, and the vacuum exhaust system, respectively.
The gas introduction system is configured to be capable of introducing the raw material gas, the reaction gas, and the purge gas into the vacuum chamber 210 independently or in a mixed manner. In the present embodiment, TMA gas, water vapor, and N as a raw material gas, a reaction gas, and a purge gas can be used 2 And (3) gas.
In forming the second metal oxide layer 12B, TMA gas is introduced as a source gas from a gas introduction system into the vacuum chamber 210 as a first step. Molecules of TMA gas introduced into the vacuum chamber 210 are adsorbed (chemisorbed) on the surface of the substrate 10. After molecules of TMA gas are adsorbed on the surface of the substrate 10, the introduction of TMA gas from the gas introduction system is stopped.
For example, when the glass substrate has dimensions 730mm×920mm, the cover conditions may be such that the temperature of the substrate 10 is 250 ℃, the pressure in the vacuum chamber 210 is 100Pa, and the amount of TMA gas introduced is 3cc/cycle. In the subsequent processing, the temperature of the substrate 10 was also set to 250 ℃.
Next, N is set as a second step 2 The gas is introduced as a purge gas from the gas introduction system. As the pressure in the purge gas vacuum chamber 210 increases, the raw material gas is extruded. The raw material gas diffused in the vacuum chamber 210 is vacuum-exhausted by an exhaust pump.
The purification conditions are such that N 2 The gas introduction time was 1 second, and the pressure in the vacuum chamber 210 was 100Pa and N 2 The flow rate of the gas was 1000sccm.
Next, as a third step, water vapor is used as a counterThe gas should be introduced from the gas introduction system. The water vapor introduced into the vacuum chamber 210 reacts with molecules of TMA gas adhering to the surface of the substrate 10 to oxidize TMA, thereby forming alumina (Al) on the surface of the substrate 10 2 O 3 ) Is a film of (a). After the reaction, the introduction of the reaction gas from the gas introduction system was stopped.
The oxidation conditions were such that the pressure in the vacuum chamber 210 was 100Pa and the amount of water vapor introduced was 3cc/cycle.
Next, as a fourth step, N is set to 2 The gas is introduced as a purge gas from the gas introduction system. As the pressure within the purge gas vacuum chamber 210 increases, water vapor is forced out. The vapor diffused in the vacuum chamber 210 is vacuum-exhausted by an exhaust pump.
The purification conditions are such that N 2 The gas introduction time was 1 second, and the pressure in the vacuum chamber 210 was 100Pa and N 2 The flow rate of the gas was 1000sccm.
By sequentially repeating the first to fourth steps for a plurality of cycles until the thin film becomes a desired thickness, a film composed of Al is formed 2 O 3 A second metal oxide layer 12B formed of a thin film.
(step of Forming Gate electrode)
Next, as shown in fig. 6, a gate electrode 13 is formed over the second metal oxide layer 12B.
Typically, the gate electrode 13 is formed of a metal single-layer film or a metal multi-layer film of aluminum, molybdenum, copper, titanium, or the like, and is formed by, for example, a sputtering method. The gate electrode 13 is formed by patterning the metal film into a predetermined shape.
(step of Forming Source region and Drain region)
Next, as shown in fig. 7, a source region 14S and a drain region 14D are formed, respectively.
The method for forming the source region 14S and the drain region 14D is not particularly limited, and in the present embodiment, the source region 14S and the drain region 14D are formed in predetermined regions of the polysilicon film constituting the active layer 11 by an ion implantation technique using the gate electrode 13 as a mask. The impurity ions (dopants) to be implanted are appropriately selected according to the conductivity type (N type, P type) of the active layer 11, and typically boron (B), phosphorus (P) can be used.
(step of Forming interlayer insulating film and Source/drain electrode)
Next, as shown in fig. 8, an interlayer insulating film 15 is formed so as to cover the gate electrode 13 and the second metal oxide layer 12B.
The interlayer insulating film 15 is made of an electrically insulating material. Typically, the semiconductor device is composed of an oxide film such as a silicon oxide film or a silicon nitride film, a laminated film of these films, or the like. The interlayer insulating film 15 is formed by, for example, CVD or sputtering.
Next, openings D1 and D2 reaching the source region 14S and the drain region 14D are formed so as to penetrate the interlayer insulating film 15 and the gate insulating film 12. The method for forming the openings D1 and D2 is not particularly limited, and for example, a laser processing technique, an etching method, or the like can be used.
Thereafter, a metal film filling the openings D1 and D2 is formed on the interlayer insulating film 15, and the source electrode 16S and the drain electrode 16D are formed by patterning the metal film into a predetermined shape. The thin film transistor 1 shown in fig. 1 was manufactured as described above.
[ action of the present embodiment ]
In the present embodiment, the gate insulating film 12 is formed of a laminated film of the first metal oxide layer 12A and the second metal oxide layer 12B. Since the second metal oxide layer 12B is constituted of an aluminum oxide layer formed by ALD, a high coverage with respect to the active layer 11 can be obtained as compared with a gate insulating film using a silicon oxide single film formed by plasma CVD.
Here, as described above, al is used as 2 O 3 When a single layer of the thin film constitutes the gate insulating film, the flatband voltage tends to shift in the positive direction. In addition, hysteresis characteristics are liable to occur. When a gate insulating film having hysteresis characteristics is applied to a thin film transistor, the threshold voltage of the thin film transistor may become unstable.
The inventors produced a plurality of samples having different structures of gate insulating films on a silicon wafer, and evaluated the flatband voltage and hysteresis characteristics of the samples.
First, sample 1 and sample 2 were produced, the sample 1 having Al film formed by ALD 2 O 3 A gate insulating film composed of a single layer of a thin film, sample 2 having TEOS-SiO film formed by plasma CVD x A gate insulating film formed of a single layer of a thin film. In this experimental example, the plasma CVD apparatus 100 and the ALD apparatus 200 shown in fig. 4 and 5, respectively, were used as the film forming apparatus.
Fig. 9 and table 1 show measurement results showing the relationship between the film thickness of the gate insulating film and the flatband voltage (Vfb) in samples 1 and 2. In FIG. 9, open diamond symbols represent Al 2 O 3 Thin film, black squares represent TEOS-SiO x A film.
TABLE 1
Figure BDA0002402781210000121
From FIG. 9 and Table 1, it was confirmed that the gate insulating film was composed of TEOS-SiO x In sample 2 composed of a thin film, the gate insulating film was made of Al 2 O 3 The flat band voltage of sample 1 formed of the film was greatly shifted by +3v or more in the positive direction.
Next, sample 3 was prepared, the sample 3 having a thickness of 50nm of TEOS-SiO x Film and Al with thickness of 50nm 2 O 3 A gate insulating film (corresponding to the structure of the gate insulating film 12 of the present embodiment) composed of a laminate of thin films, in which the teos—sio x Film formation by plasma CVD of the film, the Al 2 O 3 The thin film is formed by ALD. Fig. 10 and 11 show CV curve measurement results of samples 1 and 3.
According to FIG. 10, the gate insulating film is made of Al 2 O 3 In sample 1 formed of the film, the flat voltage was positively biased as described above. It was confirmed that the initial voltage at the time of CV curve measurement was positive and the flat band voltage was different from each other, and hysteresis characteristics were generated. The hysteresis characteristic generation in the CV curve means that the threshold voltage of the transistor characteristic is unstable, and therefore, the transistor characteristic is regarded asThe gate insulating film is not preferable.
On the other hand, it was confirmed from FIG. 11 that the gate insulating film was formed on TEOS-SiO x Al is formed on the film 2 O 3 In the film sample, like the above-mentioned Al alone 2 O 3 Hysteresis characteristics such as those of the film samples were not produced. It was confirmed that TEOS-SiO was formed sequentially on the silicon substrate in this way x Film and Al 2 O 3 In the film of the two-layer structure of the film, hysteresis characteristics of the CV curve hardly occur.
As a result of the above experiments, in the thin film transistor 1 of the present embodiment, the gate insulating film 12 is formed of teos—sio in this order on the active layer 11 x A first metal oxide layer 12A composed of Al 2 O 3 The second metal oxide layer 12B is structured so as to suppress occurrence of hysteresis characteristics. Thereby, good threshold voltage control of the thin film transistor 1 becomes possible.
Next, in the thin film transistor 1 according to the present embodiment, the film thickness of the second metal oxide layer 12B is fixed to 50nm, and the flatband voltage Vfb (V), the hysteresis (V), and the interface state density Dit (eV) are set to 0nm to 80nm for the film thickness of the first metal oxide layer 12A -1 ·cm -2 ) The measurement was performed. The above measurements were carried out immediately after film formation and after annealing treatment (500 ℃ C.).
Fig. 12 to 14 and table 2 show the flat band voltage, hysteresis, and interface state density obtained by the above-described respective measurements.
TABLE 2
Figure BDA0002402781210000131
As is confirmed from fig. 12, in the first metal oxide layer 12A (teos—sio x ) When the film thickness is 20nm to 80nm, the absolute value of the flatband voltage is lower than that of sample 2, and the flatband voltage approaches 0 as the film thickness increases.
Further, as is confirmed from fig. 13, in the first metal oxide layer 12A (teos—sio x ) The film thickness is 20nm to 80nmIn this case, hysteresis characteristics hardly occur after annealing.
It was also confirmed that hysteresis characteristics were generated when the first metal oxide layer 12A was 0 nm. This corresponds essentially to sample 1 described above.
Further, as is confirmed from fig. 14, in the first metal oxide layer 12A (teos—sio x ) When the film thickness is 20nm to 80nm, the interface state density after annealing is significantly reduced. For this result, it can be considered as follows. The first metal oxide layer 12A is formed by plasma CVD, and therefore hydrogen atoms are contained in the first metal oxide layer 12A. It is considered that the hydrogen atoms move to the interface between the active layer 11 and the first metal oxide layer 12A due to the annealing treatment, and dangling bonds existing at the interface are terminated, thereby lowering the interface state density.
As described above, in the thin film transistor 1 of the present embodiment, the gate insulating film 12 is formed of teos—sio x A first metal oxide layer 12A formed of a thin film and Al 2 O 3 The laminated structure of the second metal oxide layer 12B formed of thin films, therefore, does not make Al 2 O 3 The hysteresis characteristics of (2) are generated, and excellent threshold voltage control is ensured. Further, since the gate insulating film 12 can be formed with a very high coverage with respect to the active layer 11, leakage current between the gate electrode 13 and the active layer 11 can be prevented, and good switching characteristics can be obtained.
Further, according to the present embodiment, since a good coverage of the gate insulating film 12 with respect to the active layer 11 can be obtained, thinning of the gate insulating film is possible. Accordingly, the thin film transistor can be reduced in size and thickness, and thus the aperture ratio of the pixel portion of the display device can be increased. In addition, since the operating voltage of the thin film transistor can be reduced, power consumption of the display device can be reduced.
< second embodiment >
Fig. 15 is a schematic cross-sectional view of a thin film transistor 2 according to a second embodiment of the present invention. Hereinafter, a structure different from the first embodiment will be mainly described, and the same reference numerals as those used in the above embodiment will be given to the same structures, and the description thereof will be omitted or simplified.
The structure of the gate insulating film 22 of the thin film transistor 2 of the present embodiment is different from that of the first embodiment. Specifically, the gate insulating film 22 further has an intermediate layer 12C disposed between the first metal oxide layer 12A and the second metal oxide layer 12B.
The intermediate layer 12C is a hydrogen-rich layer containing a large number of hydrogen atoms, and is made of, for example, silicon nitride (SiN) formed by a plasma CVD method x ) Or silicon oxynitride (SiO) x N y ) The composition is formed.
The intermediate layer 12C moves to the interface between the active layer 11 and the first metal oxide layer 12A due to a large number of hydrogen atoms contained in the intermediate layer 12C by annealing treatment described later. The dangling bonds existing at the interface are terminated by a large number of hydrogen atoms, and the effect of lowering the interface state density can be obtained.
The thickness of the intermediate layer 12C is not particularly limited as long as it has a function of supplying hydrogen atoms to dangling bonds as described above, and is, for example, 3nm to 30 nm.
Next, a method of forming the intermediate layer 12C will be described. In this embodiment, the gate insulating film forming step includes an intermediate layer forming step after the first metal oxide layer forming step. The active layer forming step, the source region and the drain region forming step, the gate electrode forming step, the interlayer insulating film forming step, and the source and drain electrode forming step are the same as those of the first embodiment, and therefore, the description thereof is omitted here.
An intermediate layer 12C is formed over the first metal oxide layer 12A. The method for forming the intermediate layer 12C is not particularly limited as long as the intermediate layer 12C contains a hydrogen atom, and for example, plasma CVD can be used. In the present embodiment, siH may be used as a source gas for plasma CVD 4 、NH 3 N 2 Formed of SiN x An intermediate layer 12C is formed. The intermediate layer 12C is annealed at a predetermined temperature (e.g., 500 ℃) after film formation. The annealing treatment may be performed before or after the formation of the second metal oxide layer 12B. However, in order to be contained in the intermediate layer 12CThe hydrogen atoms are effectively supplied to the interface between the active layer 11 and the first metal oxide layer 12A, and annealing treatment is preferably performed after the film formation of the second metal oxide layer 12B.
The plasma CVD apparatus for forming the intermediate layer 12C is not particularly limited, and for example, the plasma CVD apparatus 100 described with reference to fig. 4 can be used.
The conditions for forming the intermediate layer 12C are not particularly limited, and are, for example, the following conditions when the glass substrate size is 730mm×920 mm.
SiH 4 Flow rate: 500[ sccm ]]
NH 3 Flow rate: 5000[ sccm ]]
N 2 Flow rate: 7000[ sccm ]]
Process pressure: 200 Pa
RF frequency: 27.12[ MHz ]
RF power: 4000[ W ]
Heater temperature: 350 DEG C
According to the present embodiment, the same operational effects as those of the first embodiment can be obtained. In this embodiment, a large number of hydrogen atoms included in the hydrogen-rich intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A due to the annealing treatment. A large number of hydrogen atoms terminate dangling bonds existing at the interface, so that the interface state density is reduced. This can prevent leakage current between the gate electrode 13 and the active layer 11, and can obtain good switching characteristics.
Further, according to the present embodiment, the second metal oxide layer 12B functions as a hydrogen barrier layer, and hydrogen atoms included in the intermediate layer 12C are easily moved to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing treatment. This can improve the defect repair effect of the interface.
In the present embodiment, the step of forming the first metal oxide layer 12A and the step of forming the intermediate layer 12C may be performed in the same chamber. This can prevent contamination of the surface of the first metal oxide layer 12A associated with replacement of the substrate to be processed. In addition, the time for replacing the substrate and the cost of the machine can be reduced.
In order to evaluate the characteristics of the thin film transistor 2 according to the present embodiment, the structure of the gate insulating film was changed as follows, and the interface state density Dit (eV -1 ·cm -2 ) The measurement was performed.
The gate insulating film of each thin film transistor used in the experiment had a structure of only the first metal oxide layer 12A (film thickness 80 nm), a structure of only the second metal oxide layer 12B (film thickness 80 nm), a two-layer structure of the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm), and a three-layer structure in which the intermediate layer 12C (film thickness 3 nm) was disposed between the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm). The interface state density was measured immediately after film formation and after annealing treatment (500 ℃ C.).
Table 3 shows the interface state densities obtained by the above measurement.
TABLE 3
Figure BDA0002402781210000171
From table 3, it was confirmed that the interface state density after the annealing treatment was lower in the two-layer structure and the three-layer structure than in the case where the gate insulating film was a single film, and the characteristics of the thin film transistor were preferable. It was confirmed that the interface state density in the case of the three-layer structure was lower than that in the case of the two-layer structure, and this was a more preferable value. This is considered to be because a large number of hydrogen atoms contained in the intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A due to the annealing treatment, and dangling bonds are terminated, thereby further lowering the interface state density. Thus, the thin film transistor 2 can obtain more excellent switching characteristics.
In addition, as for the result, it is also considered that the second metal oxide layer 12B participates as a hydrogen barrier layer. Specifically, the second metal oxide layer 12B functions as a hydrogen barrier layer, and hydrogen atoms included in the intermediate layer 12C easily migrate to the interface between the active layer 11 and the first metal oxide layer 12A due to the annealing treatment. This can improve the defect repair effect of the interface.
Next, the film thickness of the intermediate layer 12C was examined. In the thin film transistor 2 according to the present embodiment, the film thickness of the first metal oxide layer 12A and the film thickness of the second metal oxide layer 12B are fixed to 50nm, and when the film thickness of the intermediate layer 12C is set to 0nm to 30nm, the interface state density Dit (eV -1 ·cm -2 ) The measurement was performed.
Fig. 16 and table 4 show the interface state densities obtained by the above measurement.
TABLE 4
Figure BDA0002402781210000172
From fig. 16, it was confirmed that even if the intermediate layer 12C was 3nm, the interface state density was reduced. It was confirmed that as the film thickness of the intermediate layer 12C became thicker, the interface state density was further reduced, and the interface state density became the lowest at 10nm of the film thickness. On the other hand, it was confirmed that the interface state density was not lowered any more when the film thickness of the intermediate layer 12C exceeded 10 nm. Therefore, it is found that the intermediate layer 12C has a function of sufficiently supplying hydrogen atoms at an extremely thin film thickness of 3nm to 10 nm.
Next, in a thin film transistor in which the structure of the gate insulating film is changed in the following manner, measurement of a value of a thin film transistor characteristic (TFT characteristic) is performed. The gate insulating film of each thin film transistor has a structure of only the first metal oxide layer 12A (film thickness 100 nm), a two-layer structure of the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm) (thin film transistor 1), and a three-layer structure (thin film transistor 2) in which an intermediate layer 12C (film thickness 10 nm) is disposed between the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm).
As a TFT characteristic value, a specific mobility (cm 2 The value of the amplitude (S value) (V/dec) of the sub-threshold value and/Vs are measured. The TFT characteristics were measured after the annealing treatment (500 ℃) of each thin film transistor.
Table 5 shows the mobility and S values obtained by the above measurement.
TABLE 5
Figure BDA0002402781210000181
From table 5, it was confirmed that the mobility of the two-layer structure or the three-layer structure was improved and the S value was decreased as compared with the case where the gate insulating film had a single-layer structure.
The reason for the improvement in mobility is considered to be that Al is formed by ALD 2 O 3 Dielectric constant (about 7.5) to TEOS-SiO X Is high in dielectric constant (about 4.5) and thus is compatible with TEOS-SiO X The oxide film equivalent film thickness is thinner than that of the single film, and more carriers can be generated at the same voltage. It is considered that the reason is that the deposition of Al by ALD 2 O 3 Hydrogen in the film terminates not only defects in the interface but also defects in the film, thereby TEOS-SiO X Unwanted charges in the film disappear, and more carriers are generated at the same voltage as well.
Next, the reason why the S value is improved is that the second metal oxide layer 12B functions as a hydrogen barrier layer as described above, and the hydrogen atoms in the first metal oxide layer 12A effectively repair defects at the active layer-gate insulating film interface, thereby lowering the interface state density.
In particular, when the gate insulating film has a three-layer structure, since the intermediate layer 12C is provided, the interface state density is further reduced due to a large number of hydrogen atoms in the intermediate layer 12C, and the S value becomes a particularly preferable value.
As described above, according to the present embodiment, good coverage and uniformity of the gate insulating film can be obtained, and thus a thin film transistor excellent in TFT characteristics can be obtained.
< third embodiment >
Fig. 17 is a schematic cross-sectional view of a thin film transistor 3 according to a third embodiment of the present invention. Hereinafter, a structure different from that of the first embodiment will be mainly described, and the same reference numerals are given to the same structure as those of the first embodiment, and the description thereof will be omitted or simplified.
In the thin film transistor 3 of the present embodiment, the gate insulating film 32 further has an intermediate layer 12D disposed between the first metal oxide layer 12A and the second metal oxide layer 12B, which is different from the first embodiment in this respect.
The intermediate layer 12D is a hydrogen-rich layer containing a large number of hydrogen atoms, and is formed by subjecting the first metal oxide layer 12A to hydrogen plasma treatment. The intermediate layer 12D has the same effect as the intermediate layer 12C of the second embodiment. The thickness of the intermediate layer 12D is not particularly limited, and is, for example, 3nm to 10 nm.
Next, a method of forming the intermediate layer 12D will be described. In this embodiment, the gate insulating film forming step includes an intermediate layer forming step after the first metal oxide layer forming step. The active layer forming step, the source region and the drain region forming step, the gate electrode forming step, the interlayer insulating film forming step, and the source and drain electrode forming step are the same as those of the first embodiment, and therefore, the description thereof will be omitted here.
The intermediate layer 12D is formed by subjecting the surface of the first metal oxide layer 12A to hydrogen plasma treatment. The intermediate layer 12D is annealed at a predetermined temperature (e.g., 500 ℃) after being formed. The annealing treatment may be performed before or after the formation of the second metal oxide layer 12B. However, in order to effectively supply the hydrogen atoms contained in the intermediate layer 12D to the interface between the active layer 11 and the first metal oxide layer 12A, it is preferable to perform annealing treatment after the film formation of the second metal oxide layer 12B. The intermediate layer 12D may be diffused into the first metal oxide layer 12A after the annealing treatment, or the like, to disappear.
The apparatus for performing the hydrogen plasma treatment is not particularly limited as long as it is a plasma apparatus capable of performing the hydrogen plasma treatment on the surface of the first metal oxide layer 12A. The plasma apparatus may be configured to apply a bias potential to the electrode on the substrate side to be processed during the hydrogen plasma processing.
The film formation conditions are not particularly limited, and are, for example, the following conditions when the glass substrate size is 730mm×920 mm.
H 2 Flow rate: 1000[ sccm ]]
Process pressure: 200 Pa
RF frequency: 27.12[ MHz ]
RF power: 500[ W ]
Heater temperature: 350 DEG C
In the present embodiment, the same operational effects as those of the first embodiment and the second embodiment can be obtained.
The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments, and various modifications are naturally possible.
For example, the plasma CVD apparatus and the ALD apparatus used in the above embodiments are not limited to the above-described apparatuses, and other apparatuses may be used.
In the above embodiments, the first metal oxide layer forming step and the second metal oxide layer forming step may be performed by a vane-type multi-chamber system or a continuous system.
In the case of performing the above steps in the blade-type multi-chamber system, after the first metal oxide layer is formed in the first chamber (the plasma CVD chamber for forming the first metal oxide layer), the substrate to be processed is taken out from the plasma CVD chamber and transferred to the subsequent second chamber (the ALD chamber for forming the second metal oxide layer), and then the substrate processing is performed on a piece-by-piece basis.
Alternatively, in the case where the above-described steps are performed by a continuous system, the substrate to be processed is transported by a transport unit such as a walking beam or various conveyor belts, and then the substrate is processed in a first processing chamber (having a plasma CVD apparatus for forming a first metal oxide layer) and a subsequent second processing chamber (having an ALD apparatus for forming a second metal oxide layer) which are divided in the transport direction.
In the vane-type multi-chamber system or the continuous system, the first metal oxide layer forming step and the second metal oxide layer forming step may be performed continuously in a vacuum atmosphere. By keeping the substrate processing step always in vacuum in this manner, contamination of the substrate surface by gas or air can be prevented.
In the above embodiments, the present invention has been described by taking a thin film transistor having a top gate type (staggered type) structure as an example, but the present invention can be applied to a thin film transistor having a bottom gate type (inverted staggered type) structure in which a gate electrode is disposed on a substrate and an active layer is disposed on the gate electrode with a gate insulating film interposed therebetween.
The thin film transistor described above can be used as a TFT for an active matrix display panel such as a liquid crystal display and an organic EL display. In addition, the above transistor can be used as a transistor element of various semiconductor devices or electronic apparatuses.
Description of the reference numerals
1. 2, 3: thin film transistor
10: substrate and method for manufacturing the same
11: active layer
12. 22, 32: gate insulating film
12A: first metal oxide layer
12B: second metal oxide layer
12C, 12D: intermediate layer
13: gate electrode
14S: source region
14D: drain region

Claims (9)

1. A method for manufacturing a Thin Film Transistor (TFT),
an active layer is formed on a substrate and,
source and drain regions are formed in such a manner as to be electrically connectable to the active layer,
a first metal oxide layer composed of silicon oxide is formed on the surface of the active layer by plasma CVD,
forming a second metal oxide layer composed of aluminum oxide on the surface of the first metal oxide layer by ALD,
forming a gate electrode on the surface of the second metal oxide layer,
a hydrogen-rich intermediate layer is formed between the first metal oxide layer and the second metal oxide layer,
and annealing the intermediate layer.
2. The method for manufacturing a thin film transistor according to claim 1, wherein,
the intermediate layer is formed by subjecting the first metal oxide layer to hydrogen plasma treatment.
3. The method for manufacturing a thin film transistor according to claim 1, wherein,
The intermediate layer is formed by forming a layer of silicon nitride or silicon oxynitride between the first metal oxide layer and the second metal oxide layer.
4. The method for manufacturing a thin film transistor according to claim 3, wherein,
the step of forming the first metal oxide layer and the step of forming the layer of silicon nitride or silicon oxynitride are performed in the same chamber.
5. The method for manufacturing a thin film transistor according to any one of claims 1 to 4, wherein,
the step of forming the first metal oxide layer and the step of forming the second metal oxide layer are continuously performed in a vacuum atmosphere.
6. A thin film transistor, comprising:
a gate electrode;
an active layer composed of polysilicon;
a source region and a drain region electrically connected to the active layer; and
a gate insulating film including a first metal oxide layer formed of silicon oxide and a second metal oxide layer formed of aluminum oxide, the first metal oxide layer being disposed between the gate electrode and the active layer, the second metal oxide layer being disposed between the first metal oxide layer and the gate electrode,
The gate insulating film further includes an intermediate layer between the first metal oxide layer and the second metal oxide layer,
the interface of the active layer and the first metal oxide layer is hydrogen-rich.
7. The thin film transistor according to claim 6, wherein,
the intermediate layer comprises silicon nitride.
8. The thin film transistor according to claim 6, wherein,
the intermediate layer comprises silicon oxynitride.
9. The thin film transistor according to claim 7 or 8, wherein,
the thickness of the intermediate layer is 3nm to 10 nm.
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