WO2019087784A1 - Thin film transistor and method for producing same - Google Patents

Thin film transistor and method for producing same Download PDF

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Publication number
WO2019087784A1
WO2019087784A1 PCT/JP2018/038616 JP2018038616W WO2019087784A1 WO 2019087784 A1 WO2019087784 A1 WO 2019087784A1 JP 2018038616 W JP2018038616 W JP 2018038616W WO 2019087784 A1 WO2019087784 A1 WO 2019087784A1
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metal oxide
oxide layer
layer
thin film
film transistor
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PCT/JP2018/038616
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French (fr)
Japanese (ja)
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亨 菊池
大園　修司
太田　淳
秀昭 座間
伸 浅利
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株式会社アルバック
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Priority to JP2019509580A priority Critical patent/JP6703186B2/en
Priority to CN201880058156.1A priority patent/CN111052397B/en
Priority to KR1020207009025A priority patent/KR102317441B1/en
Publication of WO2019087784A1 publication Critical patent/WO2019087784A1/en

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to a thin film transistor having a multi-layered gate insulating film and a method of manufacturing the same.
  • the LTPS thin film transistor (Low Temperature Poly Silicon TFT) has high mobility and is used for an organic EL display device or a liquid crystal display device.
  • Patent Document 1 discloses a thin film transistor using LTPS as an active layer.
  • a thin film transistor using polysilicon is formed on a polysilicon in the order of a gate insulating film and a gate electrode.
  • the gate insulating film is not uniformly deposited on the uneven polysilicon. Therefore, a leak current flows between the gate electrode and the polysilicon, which causes a problem on the display device such as unevenness in the image.
  • the manufacturing method of the thin film transistor concerning one form of the present invention is: Forming an active layer on the substrate. Source and drain regions are formed to be electrically connectable to the active layer. A first metal oxide layer composed of silicon oxide is formed on the surface of the active layer by plasma CVD. A second metal oxide layer composed of aluminum oxide is formed by ALD on the surface of the first metal oxide layer. A gate electrode is formed on the surface of the second metal oxide layer.
  • first and second metal oxide layers are sequentially formed as the gate insulating film. Since the second metal oxide layer is formed of an aluminum oxide film formed by ALD, a high coverage can be obtained as compared to a gate insulating film of a silicon oxide single film formed by plasma CVD. Thereby, it is possible to effectively prevent the leak current between the gate electrode and the active layer, and it is possible to manufacture a thin film transistor capable of excellent threshold voltage control.
  • the gate insulating film in multiple layers in this manner, the apparent dielectric constant is higher than that of the gate insulating film made of a silicon oxide single film. This improves the charge mobility of the active layer.
  • the method may further include the steps of forming a hydrogen-rich intermediate layer between the first metal oxide layer and the second metal oxide layer, and annealing the intermediate layer.
  • a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer are transferred to the interface between the active layer and the first metal oxide layer by annealing.
  • a large amount of hydrogen atoms terminate dangling bonds present at the interface to lower the interface state density. This makes it possible to prevent a leak current between the gate electrode and the active layer, and to manufacture a thin film transistor having good switching characteristics.
  • the second metal oxide layer functions as a barrier layer, and hydrogen atoms contained in the first metal oxide layer and the intermediate layer are annealed to form the active layer and the first metal oxide. It becomes easy to move to the interface with the object layer. This makes it possible to enhance the defect repair effect of the interface.
  • the intermediate layer may be formed by hydrogen plasma treatment of the first metal oxide layer.
  • the intermediate layer may be formed by forming a layer of silicon nitride or silicon oxynitride between the first and second metal oxide layers.
  • the step of forming the first metal oxide layer and the step of forming the layer of silicon nitride or silicon oxynitride may be performed in the same chamber.
  • the step of forming the first metal oxide layer and the step of forming the layer of silicon nitride or silicon oxynitride may be performed in the same chamber.
  • the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere. As described above, by making the substrate processing vacuum consistent, it is possible to prevent contamination of the substrate surface by gas or air.
  • a thin film transistor includes a gate electrode, an active layer, a source region and a drain region, and a gate insulating film.
  • the active layer is composed of polysilicon.
  • the source region and the drain region are electrically connected to the active layer.
  • the gate insulating film includes a first metal oxide layer and a second metal oxide layer.
  • the first metal oxide layer is made of silicon oxide and disposed between the gate electrode and the active layer.
  • the second metal oxide layer is made of aluminum oxide and is disposed between the first metal oxide layer and the gate electrode.
  • the gate insulating film may further include an intermediate layer containing silicon nitride between the first metal oxide layer and the second metal oxide layer.
  • the gate insulating film may further include an intermediate layer containing silicon oxynitride between the first metal oxide layer and the second metal oxide layer.
  • the thickness of the intermediate layer may be 3 nm or more and 10 nm or less. Since the intermediate layer functions only as a source of hydrogen atoms, it becomes possible to supply a sufficient amount of hydrogen to the interface with a thickness of 3 nm or more and 10 nm or less.
  • the present invention it is possible to provide a thin film transistor having a gate insulating film with high coverage and excellent transistor characteristics, and a method of manufacturing the same.
  • FIG. 1 is a schematic view of an ALD apparatus used for manufacturing a thin film transistor according to an aspect of the present invention. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor.
  • TEOS-SiO X is used for the gate insulating film used for LTPS.
  • the gate insulating film used for TEOS-SiO x is superior in thin film transistor characteristics to the gate insulating film made of SiH 4 -SiO.
  • the flat band voltage is close to the ideal value, the threshold voltage control of the thin film transistor is relatively easy, the long-term stability of the thin film transistor characteristics is excellent, the defect state density of the interface is small, etc. It is characterized by
  • the TEOS-SiO X film has a problem that it is difficult to obtain a good coverage for the device pattern.
  • a gate insulating film and a gate electrode are sequentially formed on polysilicon as an active layer. If the coverage of the gate insulating film formed on the uneven polysilicon is poor, the gate insulating film is not uniformly deposited, and a leak current flows between the gate electrode and the polysilicon, causing an image to appear on the image. It becomes a problem on the display device that unevenness occurs. In order to increase the aperture ratio of the pixel portion of the display device and to reduce the power consumption of peripheral circuits other than the pixel, it is necessary to lower the operating voltage.
  • Atomic layer deposition is known as an insulating film deposition technique excellent in coverage with respect to asperities. This is a method of forming a thin film of which atomic layer control is performed by sequentially supplying two or more kinds of source gases to the substrate surface.
  • ALD uses the function of self-terminating adsorption and reaction in a single molecular layer when the raw material is supplied to the surface of the substrate, which makes it extremely suitable for the unevenness of the substrate, and the coverage is approximately 100% It is a formation method of the insulating film which is.
  • the flat band voltage tends to be largely shifted to the positive side, as described later. If hysteresis occurs, which causes a difference in flat band voltage depending on whether the start voltage at the time of CV curve measurement is positive or negative, the threshold voltage of the transistor characteristics becomes unstable. It can not be used.
  • the coverage of polysilicon is increased while the hysteresis characteristics of the CV curve are suppressed, and good transistor characteristics are obtained. I am trying to get it.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor 1 according to an embodiment of the present invention.
  • the thin film transistor 1 includes an active layer 11, a source region 14S and a drain region 14D, a gate insulating film 12, and a gate electrode 13.
  • the gate insulating film 12 is formed to cover the active layer 11, the source region 14 S, and the drain region 14 D formed on the substrate 10, and the gate electrode 13 is formed on the gate insulating film 12. It is composed of a gated thin film transistor.
  • the active layer 11 is made of polysilicon formed on the insulating film (for example, silicon oxide film) 10 a on the substrate 10 and functions as a channel layer of the thin film transistor 1.
  • the substrate 10 is typically a transparent glass substrate, but may be a semiconductor substrate such as a silicon substrate or a resin substrate such as a plastic film.
  • the active layer 11 is formed by crystallizing amorphous silicon formed on the substrate 10 by annealing, as described later.
  • the thickness of the active layer 11 is not particularly limited, and is, for example, 40 nm to 50 nm.
  • the source region 14S and the drain region 14D are formed apart from each other so as to sandwich the active layer 11.
  • the source region 14S and the drain region 14D are formed, for example, by implanting impurity ions into a polysilicon film forming the active layer 11, as described later.
  • the gate insulating film 12 is disposed between the active layer 11 and the gate electrode 13 and electrically insulates between these, and the charge is inverted in the active layer 11 by the voltage applied to the gate electrode 12. It has a function of forming a layer (inversion layer).
  • the gate insulating film 12 has a first metal oxide layer 12A and a second metal oxide layer 12B.
  • the first metal oxide layer 12A is formed on the substrate 10 so as to cover the active layer 11, and the source region 14S and the drain region 14D.
  • the first metal oxide layer 12A is made of silicon oxide (SiO x ), and in this embodiment, is made of silicon oxide formed using silane (SiH 4 ) or TEOS as a film forming material. Accordingly, the thin film transistor 1 can relatively easily control the threshold voltage, and can obtain excellent characteristics such as excellent long-term stability of transistor characteristics and small interface state density.
  • the thickness of the first metal oxide layer 12A can be, for example, 10 nm to 120 nm.
  • plasma-enhanced chemical vapor deposition is used as described later.
  • silicon compounds such as silane (SiH 4 ) and tetraethoxysilane (TEOS) can be used as source gases for plasma CVD.
  • TEOS and oxygen (O 2 ) are used as source gases for plasma CVD.
  • the second metal oxide layer 12B is formed on the first metal oxide layer 12A.
  • the second metal oxide layer 12B is made of aluminum oxide (Al 2 O 3 ).
  • ALD Atomic Layer Deposition
  • various aluminum compounds can be used, and in the present embodiment, trimethylaluminum (TMA) is used.
  • TMA trimethylaluminum
  • an oxidizing gas such as oxygen or ozone (O 3 ) can be used, and in the present embodiment, water vapor (H 2 O) is used.
  • the purge gas for ALD is not particularly limited, and in the present embodiment, nitrogen (N 2 ) is used.
  • ALD is excellent in step coverage and film thickness controllability, and the Al 2 O 3 layer produced by ALD has excellent coverage and can effectively prevent leak current.
  • the gate insulating film is formed of a single layer of Al 2 O 3 thin film, the flat band voltage tends to shift in the positive direction, which causes hysteresis characteristics, and depending on the magnitude of the hysteresis characteristics, The threshold voltage of the thin film transistor may be unstable.
  • the gate insulating film 12 is formed by sequentially laminating a first metal oxide layer 12A composed of TEOS-SiO x and a second metal oxide layer 12B composed of Al 2 O 3 . It has a two-layer structure. This structure makes it possible to suppress the hysteresis characteristics attributed to the Al 2 O 3 layer and obtain an excellent coverage. Thereby, the thin film transistor 1 can perform good threshold voltage control while preventing a leak current.
  • the thickness of the second metal oxide layer 12B can be, for example, 10 nm to 120 nm. This makes it possible to obtain excellent coverage while suppressing hysteresis characteristics.
  • the thickness of the gate insulating film 12 (the sum of the thickness of the first metal oxide layer 12A and the thickness of the second metal oxide layer 12B) within 130 nm in total, the miniaturization of the thin film transistor 1 can be achieved. It is possible to obtain each of the above effects.
  • the gate electrode 13 is formed of a conductive film formed on the gate insulating film 12.
  • the gate electrode 13 is typically formed of a metal single layer film or a metal multilayer film of Al, Mo, Cu, Ti or the like, and is formed by, for example, a sputtering method.
  • the thickness of the gate electrode 13 is not particularly limited, and is, for example, 200 nm to 300 nm.
  • An interlayer insulating film 15 is formed on the gate insulating film 12 and the gate electrode 13.
  • the interlayer insulating film 15 is for maintaining the insulation between the electrodes.
  • the interlayer insulating film 15 is made of an electrically insulating material, and typically made of silicon oxide, silicon nitride or the like.
  • the thickness of the interlayer insulating film 15 is not particularly limited, and is, for example, 200 nm to 500 nm.
  • the thin film transistor 1 further includes a source electrode 16S and a drain electrode 16D.
  • the source electrode 16S and the drain electrode 16D penetrate the interlayer insulating film 15 and the gate insulating film 12, and are electrically connected to the source region 14S and the drain region 14D, respectively.
  • the source electrode 16S and the drain electrode 16D are configured as lead electrodes for connecting the source region 14S and the drain region 14D to peripheral circuits (not shown).
  • the insulating film 10 a and the amorphous silicon film A are formed on the substrate 10.
  • the insulating film 10a is typically formed of a silicon oxide film, but may of course be formed of another material and may be omitted if necessary.
  • the raw material of the amorphous silicon film A is not particularly limited. For example, if it is formed by plasma CVD, silicon compounds such as silane (SiH 4 ) and disilane (Si 2 H 6 ) can be used as a raw material gas.
  • a gate insulating film 12 is formed on the substrate 10 so as to cover the surface of the active layer 11.
  • the step of forming the gate insulating film 12 includes the steps of forming a first metal oxide layer 12A and forming a second metal oxide layer 12B.
  • the first metal oxide layer 12A is formed on the substrate 10 so as to cover the surface of the active layer 11.
  • the first metal oxide layer 12A is formed by plasma CVD.
  • the plasma CVD apparatus is not particularly limited, and in the present embodiment, a plasma CVD apparatus 100 schematically shown in FIG. 4 is used.
  • the plasma CVD apparatus 100 includes a vacuum chamber 110 and a stage 111 for supporting a substrate provided inside the vacuum chamber 110.
  • the stage 111 has a heater 112 inside.
  • a high frequency electrode 113 is disposed at a position facing the heater stage 111.
  • the high frequency electrode 113 has a shower head 114, and the shower head 114 is provided with a gas diffusion plate 115 for uniformly diffusing the gas introduced from the gas introduction system and a plurality of ejection holes 116 for ejecting the gas.
  • a vacuum evacuation system 120 Connected to the vacuum chamber 110 are a vacuum evacuation system 120, a power supply system 130 having a high frequency power source, a controller 140, and a gas introduction system (not shown).
  • the controller 140 controls the heater 112, the power supply system 130, the vacuum exhaust system 120, and the gas introduction system, respectively.
  • TEOS and O 2 are used as a source gas (CVD gas) for plasma CVD.
  • the film formation conditions are not particularly limited, and for example, when the glass substrate size is 730 mm ⁇ 920 mm, the following conditions are implemented.
  • TEOS flow rate 360 [sccm] O 2 flow rate: 16000 [sccm]
  • Process pressure 175 [Pa]
  • RF frequency 27.12 [MHz]
  • RF power 4000 [W]
  • Heater temperature 350 [° C]
  • the second metal oxide layer 12B is formed to cover the first metal oxide layer 12A.
  • the second metal oxide layer 12B is formed by ALD.
  • the ALD apparatus is not particularly limited, and in the present embodiment, the ALD apparatus 200 schematically shown in FIG. 5 is used.
  • the ALD apparatus 200 includes a vacuum chamber 210 and a stage 211 for supporting a substrate provided inside the vacuum chamber 210.
  • the stage 211 has a heater 212 inside.
  • a controller 220 controls the heater 212, the gas introduction system and the vacuum exhaust system, respectively.
  • the gas introduction system is configured to be capable of introducing the source gas, the reaction gas, and the purge gas independently or mixed into the vacuum chamber 210.
  • TMA gas is used as the source gas
  • water vapor is used as the reaction gas
  • N 2 gas is used as the purge gas.
  • a TMA gas is introduced into the vacuum chamber 210 as a source gas from the gas introduction system. Molecules of TMA gas introduced into the vacuum chamber 210 are adsorbed (chemisorbed) on the surface of the substrate 10. After the molecules of the TMA gas are adsorbed on the surface of the substrate 10, the introduction of the TMA gas from the gas introduction system is stopped.
  • the temperature of the substrate 10 can be 250 ° C.
  • the pressure in the vacuum chamber 210 can be 100 Pa
  • the amount of TMA gas introduced can be 3 cc / cycle.
  • the temperature of the substrate 10 is set to 250 ° C. also in the subsequent processing.
  • N 2 gas is introduced as a purge gas from the gas introduction system.
  • the pressure in the vacuum chamber 210 is increased by the purge gas, and the source gas is pushed out.
  • the source gas diffused in the vacuum chamber 210 is evacuated by the exhaust pump.
  • the purge conditions were such that the introduction time of the N 2 gas was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the flow rate of the N 2 gas was 1000 sccm.
  • water vapor is introduced as a reaction gas from the gas introduction system.
  • the water vapor introduced into the vacuum chamber 210 reacts with the molecules of the TMA gas adhering to the surface of the substrate 10 to oxidize the TMA, and a thin film of aluminum oxide (Al 2 O 3 ) is formed on the surface of the substrate 10 .
  • the introduction of the reaction gas from the gas introduction system is stopped.
  • the oxidation conditions were such that the pressure in the vacuum chamber 210 was 100 Pa, and the amount of water vapor introduced was 3 cc / cycle.
  • N 2 gas is introduced as a purge gas from the gas introduction system.
  • the pressure in the vacuum chamber 210 is increased by the purge gas and the water vapor is pushed out.
  • the water vapor diffused in the vacuum chamber 210 is evacuated by an exhaust pump.
  • the purge conditions were such that the introduction time of the N 2 gas was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the flow rate of the N 2 gas was 1000 sccm.
  • the first to fourth steps are sequentially repeated a plurality of cycles until the thin film has a desired thickness, whereby the second metal oxide layer 12B made of an Al 2 O 3 thin film is formed.
  • Step of forming gate electrode Next, as shown in FIG. 6, the gate electrode 13 is formed on the second metal oxide layer 12B.
  • the gate electrode 13 is typically formed of a metal single layer film or metal multilayer film of aluminum, molybdenum, copper, titanium or the like, and is formed by, for example, a sputtering method.
  • the gate electrode 13 is formed by patterning the metal film into a predetermined shape.
  • Step of forming source region and drain region Subsequently, as shown in FIG. 7, a source region 14S and a drain region 14D are respectively formed.
  • the method of forming the source region 14S and the drain region 14D is not particularly limited, and in this embodiment, the source region 14S and the source region 14S are formed in predetermined regions of the polysilicon film forming the active layer 11 by ion implantation technology using the gate electrode 13 as a mask. Drain regions 14D are respectively formed.
  • the impurity ions (dopant) to be implanted are appropriately selected according to the conductivity type (N type, P type) of the active layer 11, and typically, boron (B) or phosphorus (P) is used.
  • Step of forming interlayer insulating film and source / drain electrode Next, as shown in FIG. 8, an interlayer insulating film 15 is formed to cover the gate electrode 13 and the second metal oxide layer 12B.
  • the interlayer insulating film 15 is made of an electrically insulating material. Typically, it is composed of an oxide film or nitride film such as a silicon oxide film or a silicon nitride film, and a laminated film of these.
  • the interlayer insulating film 15 is formed by, for example, a CVD method or a sputtering method.
  • openings D1 and D2 reaching the source region 14S and the drain region 14D are formed to penetrate the interlayer insulating film 15 and the gate insulating film 12.
  • the method for forming the openings D1 and D2 is not particularly limited, and, for example, a laser processing technique, an etching method, or the like is used.
  • a metal film filling the openings D1 and D2 is formed on the interlayer insulating film 15, and the metal film is patterned into a predetermined shape to form the source electrode 16S and the drain electrode 16D. As described above, the thin film transistor 1 shown in FIG. 1 is manufactured.
  • the gate insulating film 12 is formed of a laminated film of a first metal oxide layer 12A and a second metal oxide layer 12B. Since the second metal oxide layer 12B is formed of an aluminum oxide layer formed by ALD, the coverage with respect to the active layer 11 is higher than that of a gate insulating film made of a silicon oxide single film formed by plasma CVD. Is obtained.
  • the gate insulating film when the gate insulating film is formed of a single layer of Al 2 O 3 thin film, the flat band voltage tends to shift in the positive direction. In addition, hysteresis characteristics are likely to occur. When a gate insulating film having hysteresis characteristics is applied to a thin film transistor, the threshold voltage of the thin film transistor may be unstable.
  • the inventors fabricated a plurality of samples having different gate insulating film configurations on a silicon wafer, and evaluated their flat band voltage and hysteresis characteristics.
  • Sample 1 having a gate insulating film consisting of a single layer of Al 2 O 3 thin film deposited by ALD, and Sample having a gate insulating film consisting of a single layer of TEOS-SiO x thin film deposited by plasma CVD 2 were produced.
  • the plasma CVD apparatus 100 and the ALD apparatus 200 shown in FIG. 4 and FIG. 5 were used as the film forming apparatus.
  • FIG. 9 and Table 1 show measurement results showing the relationship between the film thickness of the gate insulating film and the flat band voltage (Vfb) in Samples 1 and 2.
  • Vfb flat band voltage
  • FIG. 9 open diamonds indicate Al 2 O 3 thin films and black squares indicate TEOS-SiO x thin films.
  • sample 1 in which the gate insulating film is formed of an Al 2 O 3 thin film has a flat band voltage of +3 V or more And a large shift in the positive direction.
  • the flat band voltage is shifted to the positive as described above.
  • the flat band voltage is different between when the start voltage at the time of CV curve measurement is plus and minus when there is a hysteresis characteristic.
  • the generation of the hysteresis characteristic in the CV curve means that the threshold voltage of the transistor characteristic is unstable, which is not preferable as a gate insulating film.
  • the gate insulating film is an Al 2 O 3 thin film formed on the TEOS-SiO x thin film
  • the hysteresis characteristic like the above-mentioned sample of only Al 2 O 3 thin film is not generated. Is confirmed. As described above, it has been confirmed that the hysteresis characteristic of the CV curve hardly occurs in the thin film of the two-layer structure in which the TEOS-SiO x thin film and the Al 2 O 3 thin film are sequentially formed on the silicon substrate.
  • the gate insulating film 12 is formed of the first metal oxide layer 12A composed of TEOS-SiO x and Al 2 O 3 on the active layer 11. Since the structured second metal oxide layer 12B and the second metal oxide layer 12B are sequentially formed, the occurrence of hysteresis characteristics can be suppressed. Thereby, the thin film transistor 1 can perform good threshold voltage control.
  • the band voltage Vfb (V), the hysteresis (V), and the interface state density Dit (eV -1 ⁇ cm -2 ) were measured, respectively. The above measurements were performed immediately after film formation and after annealing (500 ° C.).
  • the interface state density after the annealing treatment is greatly reduced when the film thickness of the first metal oxide layer 12A (TEOS-SiO x ) is 20 nm or more and 80 nm or less. Ru.
  • the first metal oxide layer 12A is formed by plasma CVD, hydrogen atoms are contained in the first metal oxide layer 12A. The hydrogen atoms are transferred to the interface between the active layer 11 and the first metal oxide layer 12A by annealing, and the interface state density is lowered by terminating dangling bonds present at the interface. it is conceivable that.
  • the gate insulating film 12 includes the first metal oxide layer 12A formed of the TEOS-SiO x thin film and the second metal oxide layer 12B formed of the Al 2 O 3 thin film.
  • the above-described laminated structure ensures excellent threshold voltage control without generating hysteresis characteristics of Al 2 O 3 .
  • the gate insulating film 12 can be formed with a very high coverage to the active layer 11, leak current between the gate electrode 13 and the active layer 11 can be prevented, and good switching characteristics can be obtained. .
  • the thin film transistor can be miniaturized and thinned, and the aperture ratio of the pixel portion of the display device can be increased.
  • the operating voltage of the thin film transistor can be reduced, power consumption of the display device can be reduced.
  • FIG. 15 is a schematic cross-sectional view of a thin film transistor 2 according to a second embodiment of the present invention.
  • the configuration different from the first embodiment will be mainly described, and the same configuration as that of the above-described embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
  • the thin film transistor 2 of the present embodiment differs from that of the first embodiment in the configuration of the gate insulating film 22.
  • the gate insulating film 22 further includes an intermediate layer 12C disposed between the first metal oxide layer 12A and the second metal oxide layer 12B.
  • the intermediate layer 12C is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is made of, for example, silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) formed by plasma CVD.
  • the intermediate layer 12C a large amount of hydrogen atoms contained in the intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process described later. A large amount of hydrogen atoms terminate dangling bonds present at the interface and an effect of reducing interface state density is obtained.
  • the thickness of the intermediate layer 12C is not particularly limited as long as it has a function of supplying hydrogen atoms to dangling bonds as described above, and is, for example, 3 nm or more and 30 nm or less.
  • the step of forming an intermediate layer is included after the step of forming the first metal oxide layer.
  • the process of forming the active layer, the process of forming the source and drain regions, the process of forming the gate electrode, the process of forming the interlayer insulating film, and the process of forming the source and drain electrodes are the same as in the first embodiment. , I omit the explanation here.
  • the intermediate layer 12C is formed on the first metal oxide layer 12A.
  • the method for forming the intermediate layer 12C is not particularly limited as long as it is a method in which a hydrogen atom is contained in the intermediate layer 12C.
  • plasma CVD is used.
  • SiH 4 , NH 3 and N 2 are used as source gases for plasma CVD, and an intermediate layer 12 C composed of SiN x is formed.
  • the intermediate layer 12C is annealed at a predetermined temperature (for example, 500 ° C.). The annealing may be performed before or after the formation of the second metal oxide layer 12B.
  • annealing treatment is performed after the second metal oxide layer 12B is formed. It is desirable to
  • the plasma CVD apparatus for forming the intermediate layer 12C is not particularly limited.
  • the plasma CVD apparatus 100 described with reference to FIG. 4 can be employed.
  • the film forming conditions for the intermediate layer 12C are not particularly limited. For example, when the glass substrate size is 730 mm ⁇ 920 mm, the following conditions are implemented. SiH 4 flow rate: 500 [sccm] NH 3 flow rate: 5000 [sccm] N 2 flow rate: 7000 [sccm] Process pressure: 200 [Pa] RF frequency: 27.12 [MHz] RF power: 4000 [W] Heater temperature: 350 [° C]
  • the same operation and effect as those of the above-described first embodiment can be obtained.
  • a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by annealing.
  • a large amount of hydrogen atoms terminate dangling bonds present at the interface to lower the interface state density.
  • the second metal oxide layer 12B functions as a hydrogen barrier layer, and the hydrogen atoms contained in the intermediate layer 12C are annealed to form the active layer 11 and the first metal oxide layer 12A. It is easy to move to the interface with This makes it possible to enhance the defect repair effect of the interface.
  • the step of forming the first metal oxide layer 12A and the step of forming the intermediate layer 12C may be performed in the same chamber. This makes it possible to prevent the contamination of the surface of the first metal oxide layer 12A accompanying the replacement of the processing target substrate. Moreover, it becomes possible to reduce the effort of board
  • the interface state density Dit (eV ⁇ 1 ⁇ cm ⁇ 2 ) was measured by changing the structure of the gate insulating film as follows.
  • the structure of the gate insulating film of each thin film transistor used in the experiment is the structure of only the first metal oxide layer 12A (film thickness 80 nm), the structure of only the second metal oxide layer 12B (film thickness 80 nm), the first Layer structure of the metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm), and the first metal oxide layer 12A (film thickness 50 nm) and the second metal An intermediate layer 12C (film thickness 3 nm) is disposed between the oxide layer 12B (film thickness 50 nm) and the three-layer structure.
  • the interface state density was measured immediately after film formation and after annealing (500 ° C.).
  • Table 3 shows the interface state density obtained by the above measurement.
  • the interface state density after annealing is lower in the two-layer structure and the three-layer structure compared to when the gate insulating film is a single film, which is a preferable value for the thin film transistor characteristics. That is confirmed. It is confirmed that the interface state density when the gate insulating film has the above three-layer structure is lower than that of the above two-layer structure, which is a more preferable value. This is because the large amount of hydrogen atoms contained in the intermediate layer 12C is transferred to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process, and the dangling bond is terminated, so that the interface is further improved. It is considered that the rank density is lowered. Thereby, the thin film transistor 2 can obtain more excellent switching characteristics.
  • the second metal oxide layer 12B was involved as a hydrogen barrier layer in this result. Specifically, the second metal oxide layer 12B functions as a hydrogen barrier layer, and hydrogen atoms contained in the intermediate layer 12C are annealed at the interface between the active layer 11 and the first metal oxide layer 12A. It becomes easy to move. This makes it possible to enhance the defect repair effect of the interface.
  • the film thickness of the intermediate layer 12C will be considered.
  • the film thicknesses of the first metal oxide layer 12A and the second metal oxide layer 12B are fixed to 50 nm and the film thickness of the intermediate layer 12C is 0 nm to 30 nm.
  • the interface state density Dit (eV -1 ⁇ cm -2 ) was measured.
  • the interface state density decreases even if the intermediate layer 12C is 3 nm.
  • the interface state density is further decreased, and it is confirmed that the interface state density becomes the minimum value at the film thickness of 10 nm in Example 3-3.
  • the intermediate layer 12C exceeds 10 nm, the interface state density does not decrease. Therefore, it is understood that the intermediate layer 12C has a function of supplying hydrogen atoms sufficiently with an extremely thin film thickness of 3 nm to 10 nm.
  • the structure of the gate insulating film of each thin film transistor is the structure of only the first metal oxide layer 12A (film thickness 100 nm), the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness A two-layer structure (thin film transistor 1) having a film thickness of 50 nm, and an intermediate layer 12C (a film thickness of 50 nm) between the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm)
  • TFT characteristic value mobility (cm 2 / Vs) and subthreshold swing value (S value) (V / dec) were measured.
  • S value subthreshold swing value
  • Table 5 shows the mobility and the S value obtained by the above measurement.
  • the hydrogen in the film terminates defects not only at the interface but also in the film, eliminating unnecessary charges in the TEOS-SiO X film. It is also considered to generate more carriers at the same voltage as well.
  • the second metal oxide layer 12B functions as a hydrogen barrier layer, and the hydrogen atoms in the first metal oxide layer 12A become the active layer-gate. This is because the interface state density is lowered by effectively repairing the defect at the insulating film interface. In particular, when the gate insulating film has a three-layer structure, the interface state density is further reduced by the large amount of hydrogen atoms in the intermediate layer 12C because the intermediate layer 12C is provided, and the S value is particularly preferable There is.
  • FIG. 17 is a schematic cross-sectional view of a thin film transistor 3 according to a third embodiment of the present invention.
  • the configuration different from the first embodiment will be mainly described, and the same configuration as that of the above-described embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
  • the gate insulating film 32 further includes an intermediate layer 12D disposed between the first metal oxide layer 12A and the second metal oxide layer 12B. It differs from the embodiment.
  • the intermediate layer 12D is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is formed by hydrogen plasma treatment of the first metal oxide layer 12A.
  • the middle layer 12D has the same effect as the middle layer 12C of the second embodiment.
  • the thickness of the intermediate layer 12D is not particularly limited, and is, for example, 3 nm or more and 10 nm or less.
  • the step of forming an intermediate layer is included after the step of forming the first metal oxide layer.
  • the process of forming the active layer, the process of forming the source and drain regions, the process of forming the gate electrode, the process of forming the interlayer insulating film, and the process of forming the source and drain electrodes are the same as in the first embodiment. , I omit the explanation here.
  • the intermediate layer 12D is formed by hydrogen plasma treatment of the surface of the first metal oxide layer 12A. After the formation of the intermediate layer 12D, annealing is performed at a predetermined temperature (for example, 500 ° C.). The annealing may be performed before or after the formation of the second metal oxide layer 12B. However, in order to efficiently supply the hydrogen atoms contained in the intermediate layer 12D to the interface between the active layer 11 and the first metal oxide layer 12A, annealing treatment is performed after the second metal oxide layer 12B is formed. It is desirable to After the annealing process, the intermediate layer 12D may disappear by being diffused to the first metal oxide layer 12A.
  • a predetermined temperature for example, 500 ° C.
  • the apparatus for performing hydrogen plasma processing is not particularly limited as long as it is a plasma apparatus capable of performing hydrogen plasma processing on the surface of the first metal oxide layer 12A.
  • the plasma apparatus may be configured to be capable of applying a bias potential to the electrode on the side of the target substrate at the time of hydrogen plasma processing.
  • the film formation conditions are not particularly limited, and for example, when the glass substrate size is 730 mm ⁇ 920 mm, the following conditions are implemented.
  • H 2 flow rate 1000 [sccm]
  • Process pressure 200 [Pa]
  • RF frequency 27.12 [MHz]
  • RF power 500 [W]
  • Heater temperature 350 [° C]
  • the plasma CVD apparatus and the ALD apparatus used in the above embodiments are not limited to the above-described apparatuses, and other apparatuses may be used.
  • the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed by a single wafer type multi-chamber system or an in-line system.
  • a plasma CVD chamber is formed after the formation of the first metal oxide layer in the first chamber (plasma CVD chamber for forming the first metal oxide layer)
  • the substrate to be processed is taken out from the chamber and transferred to the next second chamber (ALD chamber for forming a second metal oxide layer) to perform substrate processing one by one.
  • the first processing chamber first metal partitioned in the transport direction while transporting the substrate to be processed by transport means such as a walking beam or various conveyors.
  • Substrate processing is performed in the following second processing chamber (having an ALD apparatus for forming a second metal oxide layer) and the next second processing chamber (having a plasma CVD apparatus for forming an oxide layer).
  • the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere.
  • the substrate processing process vacuum consistent, it is possible to prevent the contamination of the substrate surface by gas or air.
  • the present invention has been described by taking a thin film transistor of top gate type (stagger type) structure as an example, but the gate electrode is disposed on the substrate and activated with the gate insulating film interposed on the gate electrode.
  • the present invention is applicable even to a thin film transistor having a bottom gate (inverted staggered) structure in which layers are disposed.
  • the thin film transistor described above can be used as a TFT for an active matrix display panel such as a liquid crystal display or an organic EL display.
  • the transistor can be used as a transistor element of various semiconductor devices or electronic devices.

Abstract

A method for producing a thin film transistor according to one embodiment of the present invention comprises the formation of an active layer on a substrate. A source region and a drain region are formed such that the regions are able to be electrically connected with the active layer. A first metal oxide layer that is configured from silicon oxide is formed on the surface of the active layer by plasma CVD. A second metal oxide layer that is configured from aluminum oxide is formed on the surface of the first metal oxide layer by ALD. A gate electrode is formed on the surface of the second metal oxide layer.

Description

薄膜トランジスタ及びその製造方法Thin film transistor and method of manufacturing the same
　本発明は、多層構造のゲート絶縁膜を有する薄膜トランジスタ及びその製造方法に関する。 The present invention relates to a thin film transistor having a multi-layered gate insulating film and a method of manufacturing the same.
　ＬＴＰＳ薄膜トランジスタ（Low Temperature Poly Silicon TFT）は、移動度が高く、有機ＥＬ表示装置や液晶表示装置に用いられる。例えば特許文献１には、ＬＴＰＳを活性層に使用した薄膜トランジスタが開示されている。 The LTPS thin film transistor (Low Temperature Poly Silicon TFT) has high mobility and is used for an organic EL display device or a liquid crystal display device. For example, Patent Document 1 discloses a thin film transistor using LTPS as an active layer.
特開２０１０－９８１４９号公報JP, 2010-98149, A
　通常、ポリシリコンを使用した薄膜トランジスタは、ポリシリコン上にゲート絶縁膜、ゲート電極の順に作製する。しかしながら、ゲート絶縁膜の被覆率が悪いと、凹凸のあるポリシリコン上にゲート絶縁膜が均一に成膜されない。そのため、ゲート電極とポリシリコンとの間にリーク電流が流れてしまい、画像にムラが出る等の表示装置上の問題が発生する。 Usually, a thin film transistor using polysilicon is formed on a polysilicon in the order of a gate insulating film and a gate electrode. However, if the coverage of the gate insulating film is poor, the gate insulating film is not uniformly deposited on the uneven polysilicon. Therefore, a leak current flows between the gate electrode and the polysilicon, which causes a problem on the display device such as unevenness in the image.
　以上のような事情に鑑み、本発明の目的は、被覆率が高くトランジスタ特性に優れる薄膜トランジスタ及びその製造方法を提供することにある。 In view of the circumstances as described above, it is an object of the present invention to provide a thin film transistor having a high coverage and excellent transistor characteristics, and a method of manufacturing the same.
　上記目的を達成するため、本発明の一形態に係る薄膜トランジスタの製造方法は、
　基板上に活性層を形成することを含む。
　ソース領域及びドレイン領域が、上記活性層と電気的に接続可能に形成される。
　上記活性層の表面に、酸化ケイ素で構成される第１の金属酸化物層がプラズマＣＶＤで形成される。
　上記第１の金属酸化物層の表面に、酸化アルミニウムで構成される第２の金属酸化物層がＡＬＤで形成される。
　上記第２の金属酸化物層の表面に、ゲート電極が形成される。 In order to achieve the above-mentioned object, the manufacturing method of the thin film transistor concerning one form of the present invention is:
Forming an active layer on the substrate.
Source and drain regions are formed to be electrically connectable to the active layer.
A first metal oxide layer composed of silicon oxide is formed on the surface of the active layer by plasma CVD.
A second metal oxide layer composed of aluminum oxide is formed by ALD on the surface of the first metal oxide layer.
A gate electrode is formed on the surface of the second metal oxide layer.
　上記製造方法においては、ゲート絶縁膜として、第１及び第２の金属酸化物層が順に形成される。第２の金属酸化物層がＡＬＤで成膜された酸化アルミニウム膜で構成されるので、プラズマＣＶＤで成膜される酸化ケイ素単膜によるゲート絶縁膜と比べて高い被覆率が得られる。これにより、ゲート電極と活性層との間のリーク電流を効果的に防ぐことができ、良好な閾値電圧制御が可能な薄膜トランジスタを製造することが可能となる。 In the above manufacturing method, first and second metal oxide layers are sequentially formed as the gate insulating film. Since the second metal oxide layer is formed of an aluminum oxide film formed by ALD, a high coverage can be obtained as compared to a gate insulating film of a silicon oxide single film formed by plasma CVD. Thereby, it is possible to effectively prevent the leak current between the gate electrode and the active layer, and it is possible to manufacture a thin film transistor capable of excellent threshold voltage control.
　また、このようにゲート絶縁膜を多層に形成することで、酸化ケイ素単膜によるゲート絶縁膜と比べて見かけの誘電率が高くなる。これにより、活性層の電荷移動度が改善される。 In addition, by forming the gate insulating film in multiple layers in this manner, the apparent dielectric constant is higher than that of the gate insulating film made of a silicon oxide single film. This improves the charge mobility of the active layer.
　上記第１の金属酸化物層と上記第２の金属酸化物層との間に水素リッチな中間層を形成する工程と、上記中間層をアニール処理する工程とをさらに含んでいてもよい。 The method may further include the steps of forming a hydrogen-rich intermediate layer between the first metal oxide layer and the second metal oxide layer, and annealing the intermediate layer.
　この製造方法によれば、水素リッチな中間層に含まれる多量の水素原子が、アニールによって、活性層と第１の金属酸化物層との界面に移動する。多量の水素原子は、当該界面に存在するダングリングボンドを終端して、界面準位密度を低下させる。これにより、ゲート電極と活性層との間のリーク電流を防ぎ、良好なスイッチング特性を有する薄膜トランジスタを製造することが可能となる。 According to this manufacturing method, a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer are transferred to the interface between the active layer and the first metal oxide layer by annealing. A large amount of hydrogen atoms terminate dangling bonds present at the interface to lower the interface state density. This makes it possible to prevent a leak current between the gate electrode and the active layer, and to manufacture a thin film transistor having good switching characteristics.
　また、この製造方法によれば、第２の金属酸化物層がバリア層として働き、第１の金属酸化物層及び中間層に含まれる水素原子が、アニールによって、活性層と第１の金属酸化物層との界面に移動し易くなる。これにより、当該界面の欠陥修復効果を高めることが可能となる。 Further, according to this manufacturing method, the second metal oxide layer functions as a barrier layer, and hydrogen atoms contained in the first metal oxide layer and the intermediate layer are annealed to form the active layer and the first metal oxide. It becomes easy to move to the interface with the object layer. This makes it possible to enhance the defect repair effect of the interface.
　上記第１の金属酸化物層を水素プラズマ処理することによって、上記中間層を形成してもよい。 The intermediate layer may be formed by hydrogen plasma treatment of the first metal oxide layer.
　上記第１及び第２金属酸化物層の間に窒化ケイ素又は酸窒化ケイ素の層を形成することによって、上記中間層を形成してもよい。 The intermediate layer may be formed by forming a layer of silicon nitride or silicon oxynitride between the first and second metal oxide layers.
　上記第１の金属酸化物層を形成する工程と、上記窒化ケイ素又は酸窒化ケイ素の層を形成する工程とは、同チャンバ内で行われてもよい。このように、基板処理を同チャンバ内で行うことにより、基板の入れ替えに伴う基板表面の汚染を防ぐことが可能となる。また、基板入れ替えの手間や機器のコストを削減することが可能となる。 The step of forming the first metal oxide layer and the step of forming the layer of silicon nitride or silicon oxynitride may be performed in the same chamber. Thus, by performing the substrate processing in the same chamber, it is possible to prevent the contamination of the substrate surface accompanying the replacement of the substrate. Moreover, it becomes possible to reduce the effort of board | substrate replacement | exchange, and the cost of an apparatus.
　上記第１の金属酸化物層を形成する工程と、上記第２の金属酸化物層を形成する工程とは、真空雰囲気中で連続して行われてもよい。
　このように、基板処理を真空一貫とすることで、ガスや空気による基板表面の汚染を防ぐことが可能となる。 The step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere.
As described above, by making the substrate processing vacuum consistent, it is possible to prevent contamination of the substrate surface by gas or air.
　本発明の一形態に係る薄膜トランジスタは、ゲート電極と、活性層と、ソース領域及びドレイン領域と、ゲート絶縁膜とを具備する。
　上記活性層はポリシリコンで構成される。
　上記ソース領域及びドレイン領域は、上記活性層と電気的に接続される。
　上記ゲート絶縁膜は、第１の金属酸化物層と、第２の金属酸化物層とを含む。
　上記第１の金属酸化物層は、酸化ケイ素で構成され、上記ゲート電極と上記活性層との間に配置される。
　上記第２の金属酸化物層は、酸化アルミニウムで構成され、上記第１の金属酸化物層と上記ゲート電極との間に配置される。 A thin film transistor according to an embodiment of the present invention includes a gate electrode, an active layer, a source region and a drain region, and a gate insulating film.
The active layer is composed of polysilicon.
The source region and the drain region are electrically connected to the active layer.
The gate insulating film includes a first metal oxide layer and a second metal oxide layer.
The first metal oxide layer is made of silicon oxide and disposed between the gate electrode and the active layer.
The second metal oxide layer is made of aluminum oxide and is disposed between the first metal oxide layer and the gate electrode.
　上記ゲート絶縁膜は、上記第１の金属酸化物層と上記第２の金属酸化物層との間に、窒化ケイ素を含む中間層をさらに含んでいてもよい。 The gate insulating film may further include an intermediate layer containing silicon nitride between the first metal oxide layer and the second metal oxide layer.
　上記ゲート絶縁膜は、上記第１の金属酸化物層と上記第２の金属酸化物層との間に、酸窒化ケイ素を含む中間層をさらに含んでいてもよい。 The gate insulating film may further include an intermediate layer containing silicon oxynitride between the first metal oxide layer and the second metal oxide layer.
　上記中間層の厚みは、３ｎｍ以上１０ｎｍ以下であってもよい。
　中間層は水素原子の供給源としてのみ働くため、３ｎｍ以上１０ｎｍ以下の厚みで十分な量の水素を界面に供給することが可能となる。 The thickness of the intermediate layer may be 3 nm or more and 10 nm or less.
Since the intermediate layer functions only as a source of hydrogen atoms, it becomes possible to supply a sufficient amount of hydrogen to the interface with a thickness of 3 nm or more and 10 nm or less.
　以上述べたように、本発明によれば、被覆率が高くトランジスタ特性に優れるゲート絶縁膜を有する薄膜トランジスタ及びその製造方法を提供することができる。 As described above, according to the present invention, it is possible to provide a thin film transistor having a gate insulating film with high coverage and excellent transistor characteristics, and a method of manufacturing the same.
本発明の一実施形態に係る薄膜トランジスタの構成を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the thin-film transistor which concerns on one Embodiment of this invention. 上記薄膜トランジスタの製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. 上記薄膜トランジスタの製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. 本発明の一形態に係る薄膜トランジスタの製造に用いられるプラズマＣＶＤ装置の概略図である。It is the schematic of the plasma CVD apparatus used for manufacture of the thin-film transistor which concerns on one form of this invention. 本発明の一形態に係る薄膜トランジスタの製造に用いられるＡＬＤ装置の概略図である。FIG. 1 is a schematic view of an ALD apparatus used for manufacturing a thin film transistor according to an aspect of the present invention. 上記薄膜トランジスタの製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. 上記薄膜トランジスタの製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. 上記薄膜トランジスタの製造方法を説明する工程断面図である。It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. 各金属酸化物薄膜のフラットバンド電圧を示す一実験結果である。It is an experimental result which shows the flat band voltage of each metal oxide thin film. Ａｌ２Ｏ３薄膜のＣＶカーブを示す一実験結果である。It is an experimental result showing a CV curve of the al 2 O 3 thin film. ＴＥＯＳ－ＳｉＯｘとＡｌ２Ｏ３との二層構造の薄膜のＣＶカーブを示す一実験結果である。It is an experimental result which shows CV curve of the thin film of 2 layer structure of TEOS-SiO x and Al 2 O 3 . 上記薄膜トランジスタの第１の金属酸化物層の膜厚とフラットバンド電圧との関係を示す図である。It is a figure which shows the relationship between the film thickness of the 1st metal oxide layer of the said thin-film transistor, and flat band voltage. 上記薄膜トランジスタの第１の金属酸化物層の膜厚とヒステリシス特性との関係を示す図である。It is a figure which shows the relationship between the film thickness of the 1st metal oxide layer of the said thin-film transistor, and a hysteresis characteristic. 上記薄膜トランジスタの第１の金属酸化物層の膜厚と界面準位密度との関係を示す図である。It is a figure which shows the relationship between the film thickness of the 1st metal oxide layer of the said thin-film transistor, and interface state density. 本発明の第２の実施形態に係る薄膜トランジスタの構成を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the thin-film transistor which concerns on the 2nd Embodiment of this invention. 上記薄膜トランジスタの中間層の膜厚と界面準位密度との関係を示す図である。It is a figure which shows the relationship between the film thickness of the intermediate | middle layer of the said thin-film transistor, and interface state density. 本発明の第３の実施形態に係る薄膜トランジスタの構成を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the thin-film transistor which concerns on the 3rd Embodiment of this invention.
［ＬＴＰＳ－ＴＦＴの概要］
　ＬＴＰＳに用いられるゲート絶縁膜には、一般的に、ＴＥＯＳ－ＳｉＯＸが用いられている。ＴＥＯＳ－ＳｉＯＸに用いられるゲート絶縁膜は、ＳｉＨ４－ＳｉＯで作成されたゲート絶縁膜に比べ、薄膜トランジスタ特性が優れている。具体的には、ＴＥＯＳ－ＳｉＯＸではフラットバンド電圧が理想値に近く、薄膜トランジスタの閾値電圧制御が比較的容易である、薄膜トランジスタ特性の長期安定性に優れる、界面の欠陥準位密度が小さい、等という特長がある。 [Overview of LTPS-TFT]
Generally, TEOS-SiO X is used for the gate insulating film used for LTPS. The gate insulating film used for TEOS-SiO x is superior in thin film transistor characteristics to the gate insulating film made of SiH 4 -SiO. Specifically, in the case of TEOS-SiO X , the flat band voltage is close to the ideal value, the threshold voltage control of the thin film transistor is relatively easy, the long-term stability of the thin film transistor characteristics is excellent, the defect state density of the interface is small, etc. It is characterized by
　ところが、ＴＥＯＳ－ＳｉＯＸ膜は、デバイスパターンに対する良好な被覆率が得られにくいという問題がある。トップゲート型のＬＴＰＳ－ＴＦＴの膜構造は、活性層としてのポリシリコン上にゲート絶縁膜及びゲート電極が順に形成される。凹凸のあるポリシリコン上に形成されるゲート絶縁膜の被覆率が悪いと、ゲート絶縁膜が均一に成膜されずに、ゲート電極とポリシリコンとの間にリーク電流が流れてしまい、画像にムラが発生してしまう等の表示装置上の問題となってしまう。
　表示装置の画素部分の開口率を上げるため、また画素以外の周辺回路の消費電力を下げるためには、動作電圧を下げる必要がある。これらの対策を行うためには、薄膜トランジスタの移動度を大きくする必要があり、そのためにはゲート絶縁膜の薄膜化が必要である。しかし、ゲート絶縁膜の薄膜化はリーク電流の増加を招くことから、ゲート絶縁膜の薄膜化には限界がある。 However, the TEOS-SiO X film has a problem that it is difficult to obtain a good coverage for the device pattern. In the film structure of the top gate type LTPS-TFT, a gate insulating film and a gate electrode are sequentially formed on polysilicon as an active layer. If the coverage of the gate insulating film formed on the uneven polysilicon is poor, the gate insulating film is not uniformly deposited, and a leak current flows between the gate electrode and the polysilicon, causing an image to appear on the image. It becomes a problem on the display device that unevenness occurs.
In order to increase the aperture ratio of the pixel portion of the display device and to reduce the power consumption of peripheral circuits other than the pixel, it is necessary to lower the operating voltage. In order to take these measures, it is necessary to increase the mobility of the thin film transistor, which requires thinning of the gate insulating film. However, since thinning of the gate insulating film causes an increase in leakage current, there is a limit to thinning of the gate insulating film.
　そこで近年、トランジスタ特性に優れ、かつ、凹凸に対する被覆率に優れたゲート絶縁膜特性が、表示装置の特性改善に必要な技術として注目されている。
　凹凸に対する被覆率に優れた絶縁膜成膜技術として、原子層堆積法（ＡＬＤ）が知られている。これは、２種類以上の原料ガスを順番に基板表面に供給し、原子層制御された薄膜を形成する手法である。ＡＬＤは、原料を基板表面に供給した際に、一分子層で吸着・反応が自己停止する機能を用いており、これにより基板の凹凸に対する付き回りが非常に優れ、被覆率としてはほぼ１００％である絶縁膜の形成方法である。 Therefore, in recent years, a gate insulating film characteristic which is excellent in transistor characteristics and excellent in coverage with respect to asperities is attracting attention as a technique necessary for improving the characteristics of display devices.
Atomic layer deposition (ALD) is known as an insulating film deposition technique excellent in coverage with respect to asperities. This is a method of forming a thin film of which atomic layer control is performed by sequentially supplying two or more kinds of source gases to the substrate surface. ALD uses the function of self-terminating adsorption and reaction in a single molecular layer when the raw material is supplied to the surface of the substrate, which makes it extremely suitable for the unevenness of the substrate, and the coverage is approximately 100% It is a formation method of the insulating film which is.
　ところが、ＡＬＤ技術で成膜されたＡｌ２Ｏ３薄膜についてＣＶ（容量－電圧）特性を評価すると、後述するように、フラットバンド電圧がプラス側に大きくシフトする傾向がある。ＣＶカーブ測定時の開始電圧がプラスの時とマイナスの時とでフラットバンド電圧に違いが生じるような、ヒステリシスが発生すると、トランジスタ特性の閾値電圧が不安定になり、このままではゲート絶縁膜としては使用することができない。 However, when the CV (capacitance-voltage) characteristics of an Al 2 O 3 thin film formed by the ALD technique are evaluated, the flat band voltage tends to be largely shifted to the positive side, as described later. If hysteresis occurs, which causes a difference in flat band voltage depending on whether the start voltage at the time of CV curve measurement is positive or negative, the threshold voltage of the transistor characteristics becomes unstable. It can not be used.
　以上の問題を解決するため、本実施形態においては、ゲート絶縁膜の構造及び作製法を工夫することで、ＣＶカーブのヒステリシス特性を抑えつつ、ポリシリコンの被覆率を高め、良好なトランジスタ特性を得るようにしている。 In order to solve the above problems, in the present embodiment, by devising the structure and manufacturing method of the gate insulating film, the coverage of polysilicon is increased while the hysteresis characteristics of the CV curve are suppressed, and good transistor characteristics are obtained. I am trying to get it.
　以下、図面を参照しながら本発明の実施形態を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
＜第１の実施形態＞
　図１は、本発明の一実施形態に係る薄膜トランジスタ１の概略断面図である。 First Embodiment
FIG. 1 is a schematic cross-sectional view of a thin film transistor 1 according to an embodiment of the present invention.
［薄膜トランジスタの構成］
　本実施形態に係る薄膜トランジスタ１は、活性層１１と、ソース領域１４Ｓ及びドレイン領域１４Ｄと、ゲート絶縁膜１２と、ゲート電極１３とを有する。 [Configuration of thin film transistor]
The thin film transistor 1 according to the present embodiment includes an active layer 11, a source region 14S and a drain region 14D, a gate insulating film 12, and a gate electrode 13.
　薄膜トランジスタ１は、基板１０上に形成された活性層１１、ソース領域１４Ｓ及びドレイン領域１４Ｄを被覆するようにゲート絶縁膜１２が形成され、ゲート絶縁膜１２上にゲート電極１３が形成された、トップゲート型の薄膜トランジスタで構成される。 In the thin film transistor 1, the gate insulating film 12 is formed to cover the active layer 11, the source region 14 S, and the drain region 14 D formed on the substrate 10, and the gate electrode 13 is formed on the gate insulating film 12. It is composed of a gated thin film transistor.
　以下、薄膜トランジスタ１の各部の構成について説明する。 Hereinafter, the configuration of each part of the thin film transistor 1 will be described.
　（活性層）
　活性層１１は、基板１０上の絶縁膜（例えばシリコン酸化膜）１０ａに形成されたポリシリコンからなり、薄膜トランジスタ１のチャネル層として機能する。基板１０は、典型的には透明なガラス基板であるが、シリコン基板等の半導体基板やプラスチックフィルム等の樹脂基板でもよい。活性層１１は、後述するように、基板１０上に形成されたアモルファスシリコンをアニール処理によって結晶化させることで形成される。活性層１１の厚みは特に限定されず、例えば、４０ｎｍ～５０ｎｍである。 (Active layer)
The active layer 11 is made of polysilicon formed on the insulating film (for example, silicon oxide film) 10 a on the substrate 10 and functions as a channel layer of the thin film transistor 1. The substrate 10 is typically a transparent glass substrate, but may be a semiconductor substrate such as a silicon substrate or a resin substrate such as a plastic film. The active layer 11 is formed by crystallizing amorphous silicon formed on the substrate 10 by annealing, as described later. The thickness of the active layer 11 is not particularly limited, and is, for example, 40 nm to 50 nm.
　（ソース領域及びドレイン領域）
　ソース領域１４Ｓ及びドレイン領域１４Ｄは、活性層１１を挟むように相互に離間して形成される。ソース領域１４Ｓ及びドレイン領域１４Ｄは、後述するように、例えば、活性層１１を構成するポリシリコン膜に不純物イオンを注入することで形成される。 (Source region and drain region)
The source region 14S and the drain region 14D are formed apart from each other so as to sandwich the active layer 11. The source region 14S and the drain region 14D are formed, for example, by implanting impurity ions into a polysilicon film forming the active layer 11, as described later.
　（ゲート絶縁膜）
　ゲート絶縁膜１２は、活性層１１とゲート電極１３との間に配置され、これらの間を電気的に絶縁するとともに、ゲート電極１２に印加された電圧により、活性層１１内に電荷の反転した層（反転層）を形成する機能を有する。ゲート絶縁膜１２は、第１の金属酸化物層１２Ａと、第２の金属酸化物層１２Ｂとを有する。 (Gate insulating film)
The gate insulating film 12 is disposed between the active layer 11 and the gate electrode 13 and electrically insulates between these, and the charge is inverted in the active layer 11 by the voltage applied to the gate electrode 12. It has a function of forming a layer (inversion layer). The gate insulating film 12 has a first metal oxide layer 12A and a second metal oxide layer 12B.
　第１の金属酸化物層１２Ａは、活性層１１と、ソース領域１４Ｓ及びドレイン領域１４Ｄとを被覆するように、基板１０上に形成される。 The first metal oxide layer 12A is formed on the substrate 10 so as to cover the active layer 11, and the source region 14S and the drain region 14D.
　第１の金属酸化物層１２Ａは、酸化ケイ素（ＳｉＯｘ）で構成され、本実施形態では、シラン（ＳｉＨ４）やＴＥＯＳを成膜材料として形成された酸化ケイ素で構成される。これにより、薄膜トランジスタ１は、閾値電圧制御が比較的容易となり、トランジスタ特性の長期安定性に優れる、界面準位密度が小さい、等の優れた特性を得ることができる。第１の金属酸化物層１２Ａの厚みは、例えば、１０ｎｍ～１２０ｎｍとすることができる。 The first metal oxide layer 12A is made of silicon oxide (SiO x ), and in this embodiment, is made of silicon oxide formed using silane (SiH 4 ) or TEOS as a film forming material. Accordingly, the thin film transistor 1 can relatively easily control the threshold voltage, and can obtain excellent characteristics such as excellent long-term stability of transistor characteristics and small interface state density. The thickness of the first metal oxide layer 12A can be, for example, 10 nm to 120 nm.
　第１の金属酸化物層１２Ａの形成方法としては、後述するようにプラズマＣＶＤ（Plasma-enhanced Chemical Vapor Deposition）が用いられる。プラズマＣＶＤの原料ガスとしては、例えば、シラン（ＳｉＨ４）、テトラエトキシシラン（ＴＥＯＳ）等のケイ素化合物を用いることができる。本実施形態では、プラズマＣＶＤの原料ガスとして、ＴＥＯＳ及び酸素（Ｏ２）が用いられる。 As a method of forming the first metal oxide layer 12A, plasma-enhanced chemical vapor deposition (plasma CVD) is used as described later. For example, silicon compounds such as silane (SiH 4 ) and tetraethoxysilane (TEOS) can be used as source gases for plasma CVD. In this embodiment, TEOS and oxygen (O 2 ) are used as source gases for plasma CVD.
　第２の金属酸化物層１２Ｂは、第１の金属酸化物層１２Ａの上に形成される。第２の金属酸化物層１２Ｂは、酸化アルミニウム（Ａｌ２Ｏ３）で構成される。第２の金属酸化物層１２Ｂの形成方法としては、ＡＬＤ（Atomic Layer Deposition）が用いられる。ＡＬＤの原料ガスとしては、種々のアルミニウム化合物を用いることができ、本実施形態では、トリメチルアルミニウム（ＴＭＡ）が用いられる。また、ＡＬＤの反応ガスとしては、酸素、オゾン（Ｏ３）等の酸化ガスを用いることができ、本実施形態では、水蒸気（Ｈ２Ｏ）が用いられる。また、ＡＬＤのパージガスとしては、特に限定されず、本実施形態では、窒素（Ｎ２）が用いられる。 The second metal oxide layer 12B is formed on the first metal oxide layer 12A. The second metal oxide layer 12B is made of aluminum oxide (Al 2 O 3 ). ALD (Atomic Layer Deposition) is used as a method of forming the second metal oxide layer 12B. As a source gas for ALD, various aluminum compounds can be used, and in the present embodiment, trimethylaluminum (TMA) is used. Further, as a reactive gas for ALD, an oxidizing gas such as oxygen or ozone (O 3 ) can be used, and in the present embodiment, water vapor (H 2 O) is used. Also, the purge gas for ALD is not particularly limited, and in the present embodiment, nitrogen (N 2 ) is used.
　ＡＬＤは段差被覆性及び膜厚制御性に優れており、ＡＬＤによって作製されたＡｌ２Ｏ３層は、優れた被覆率を有し、リーク電流を効果的に防ぐことが可能となる。その反面、Ａｌ２Ｏ３薄膜の単一層でゲート絶縁膜を構成した場合、フラットバンド電圧が正方向にシフトする傾向があり、これによりヒステリシス特性が発生し、当該ヒステリシス特性の大きさによっては、薄膜トランジスタの閾値電圧が不安定になるおそれがある。 ALD is excellent in step coverage and film thickness controllability, and the Al 2 O 3 layer produced by ALD has excellent coverage and can effectively prevent leak current. On the other hand, when the gate insulating film is formed of a single layer of Al 2 O 3 thin film, the flat band voltage tends to shift in the positive direction, which causes hysteresis characteristics, and depending on the magnitude of the hysteresis characteristics, The threshold voltage of the thin film transistor may be unstable.
　本実施形態では、ゲート絶縁膜１２が、ＴＥＯＳ－ＳｉＯｘで構成される第１の金属酸化物層１２Ａと、Ａｌ２Ｏ３で構成される第２の金属酸化物層１２Ｂとが順に積層した二層構造となっている。この構造により、Ａｌ２Ｏ３層に起因するヒステリシス特性を抑え、かつ優れた被覆率を得ることが可能となる。これにより、薄膜トランジスタ１は、リーク電流を防ぎつつ良好な閾値電圧制御が可能となる。 In the present embodiment, the gate insulating film 12 is formed by sequentially laminating a first metal oxide layer 12A composed of TEOS-SiO x and a second metal oxide layer 12B composed of Al 2 O 3 . It has a two-layer structure. This structure makes it possible to suppress the hysteresis characteristics attributed to the Al 2 O 3 layer and obtain an excellent coverage. Thereby, the thin film transistor 1 can perform good threshold voltage control while preventing a leak current.
　第２の金属酸化物層１２Ｂの厚みは、例えば、１０ｎｍ～１２０ｎｍとすることができる。これにより、ヒステリシス特性を抑えつつ優れた被覆率を得ることが可能となる。 The thickness of the second metal oxide layer 12B can be, for example, 10 nm to 120 nm. This makes it possible to obtain excellent coverage while suppressing hysteresis characteristics.
　ゲート絶縁膜１２の厚み（第１の金属酸化物層１２Ａの厚みと第２の金属酸化物層１２Ｂの厚みの和）を、合計１３０ｎｍ以内とすることで、薄膜トランジスタ１の小型化を図りつつ、上記の各効果を得ることが可能となる。 By making the thickness of the gate insulating film 12 (the sum of the thickness of the first metal oxide layer 12A and the thickness of the second metal oxide layer 12B) within 130 nm in total, the miniaturization of the thin film transistor 1 can be achieved. It is possible to obtain each of the above effects.
　（ゲート電極）
　ゲート電極１３は、ゲート絶縁膜１２の上に形成された導電膜からなる。ゲート電極１３は、典型的には、Ａｌ，Ｍｏ，Ｃｕ，Ｔｉ等の金属単層膜あるいは金属多層膜で構成され、例えばスパッタリング法によって形成される。ゲート電極１３の厚みは特に限定されず、例えば、２００ｎｍ～３００ｎｍである。 (Gate electrode)
The gate electrode 13 is formed of a conductive film formed on the gate insulating film 12. The gate electrode 13 is typically formed of a metal single layer film or a metal multilayer film of Al, Mo, Cu, Ti or the like, and is formed by, for example, a sputtering method. The thickness of the gate electrode 13 is not particularly limited, and is, for example, 200 nm to 300 nm.
　（その他）
　ゲート絶縁膜１２及びゲート電極１３の上には、層間絶縁膜１５が形成されている。層間絶縁膜１５は、電極間の絶縁を保つためのものである。層間絶縁膜１５は、電気絶縁性材料で構成され、典型的には、酸化ケイ素、窒化珪素等で構成される。層間絶縁膜１５の厚みは特に限定されず、例えば、２００ｎｍ～５００ｎｍである。 (Others)
An interlayer insulating film 15 is formed on the gate insulating film 12 and the gate electrode 13. The interlayer insulating film 15 is for maintaining the insulation between the electrodes. The interlayer insulating film 15 is made of an electrically insulating material, and typically made of silicon oxide, silicon nitride or the like. The thickness of the interlayer insulating film 15 is not particularly limited, and is, for example, 200 nm to 500 nm.
　薄膜トランジスタ１は、ソース電極１６Ｓ及びドレイン電極１６Ｄをさらに有する。ソース電極１６Ｓ及びドレイン電極１６Ｄは、層間絶縁膜１５及びゲート絶縁膜１２を貫通し、ソース領域１４Ｓ及びドレイン領域１４Ｄにそれぞれ電気的に接続される。ソース電極１６Ｓ及びドレイン電極１６Ｄは、ソース領域１４Ｓ及びドレイン領域１４Ｄを、図示しない周辺回路へ接続するための引出し電極として構成される。 The thin film transistor 1 further includes a source electrode 16S and a drain electrode 16D. The source electrode 16S and the drain electrode 16D penetrate the interlayer insulating film 15 and the gate insulating film 12, and are electrically connected to the source region 14S and the drain region 14D, respectively. The source electrode 16S and the drain electrode 16D are configured as lead electrodes for connecting the source region 14S and the drain region 14D to peripheral circuits (not shown).
［薄膜トランジスタの製造方法］
　次に、以上のように構成される本実施形態の薄膜トランジスタ１の製造方法について説明する。図２～８は、薄膜トランジスタ１の製造方法を説明する各工程の断面図および成膜装置の概略断面図である。 [Method of manufacturing thin film transistor]
Next, a method of manufacturing the thin film transistor 1 of the present embodiment configured as described above will be described. 2 to 8 are a cross-sectional view of each step of the method for manufacturing the thin film transistor 1 and a schematic cross-sectional view of a film forming apparatus.
　（ゲート電極の形成）
　まず、図２に示すように、基板１０上に絶縁膜１０ａ及びアモルファスシリコン膜Ａを形成する。絶縁膜１０ａは、典型的にはシリコン酸化膜で構成されるが、勿論他の材料で構成されてもよく、また必要に応じて省略されてもよい。アモルファスシリコン膜Ａの原料は、特に限定されず、例えばプラズマＣＶＤによる形成であれば、原料ガスとしてシラン（ＳｉＨ４）やジシラン（Ｓｉ２Ｈ６）等のケイ素化合物を用いることができる。 (Formation of gate electrode)
First, as shown in FIG. 2, the insulating film 10 a and the amorphous silicon film A are formed on the substrate 10. The insulating film 10a is typically formed of a silicon oxide film, but may of course be formed of another material and may be omitted if necessary. The raw material of the amorphous silicon film A is not particularly limited. For example, if it is formed by plasma CVD, silicon compounds such as silane (SiH 4 ) and disilane (Si 2 H 6 ) can be used as a raw material gas.
　（ゲート絶縁膜の形成）
　次に、基板１０上に形成されたアモルファスシリコン膜Ａを結晶化するために熱処理が施される。その後、所定形状にパターニングされることにより、ポリシリコンからなる活性層１１が形成される。 (Formation of gate insulating film)
Next, heat treatment is performed to crystallize the amorphous silicon film A formed on the substrate 10. Thereafter, by patterning into a predetermined shape, an active layer 11 made of polysilicon is formed.
　続いて、図３に示すように、活性層１１の表面を被覆するように基板１０上にゲート絶縁膜１２が形成される。ゲート絶縁膜１２の形成工程は、第１の金属酸化物層１２Ａを形成するステップと、第２の金属酸化物層１２Ｂを形成するステップとを有する。 Subsequently, as shown in FIG. 3, a gate insulating film 12 is formed on the substrate 10 so as to cover the surface of the active layer 11. The step of forming the gate insulating film 12 includes the steps of forming a first metal oxide layer 12A and forming a second metal oxide layer 12B.
　〔第１の金属酸化物層の形成工程〕
　第１の金属酸化物層１２Ａは、活性層１１の表面を被覆するように基板１０上に形成される。第１の金属酸化物層１２Ａは、プラズマＣＶＤによって形成される。プラズマＣＶＤ装置は特に限定されず、本実施形態では図４に概略的に示すプラズマＣＶＤ装置１００が用いられる。 [Step of Forming First Metal Oxide Layer]
The first metal oxide layer 12A is formed on the substrate 10 so as to cover the surface of the active layer 11. The first metal oxide layer 12A is formed by plasma CVD. The plasma CVD apparatus is not particularly limited, and in the present embodiment, a plasma CVD apparatus 100 schematically shown in FIG. 4 is used.
　プラズマＣＶＤ装置１００は、真空チャンバ１１０と、真空チャンバ１１０内部に設置された基板支持用のステージ１１１とを備える。ステージ１１１は、内部にヒータ１１２を有する。真空チャンバ１１０の内部には、ヒータステージ１１１と対向する位置に高周波電極１１３が配置されている。高周波電極１１３は、シャワーヘッド１１４を有し、シャワーヘッド１１４にはガス導入系から導入されたガスを均一に拡散させるためのガス拡散板１１５及びガスを噴出する複数の噴出孔１１６が設けられている。真空チャンバ１１０には、真空排気系１２０、高周波電源を有する電力供給系１３０、コントローラ１４０及び図示しないガス導入系が接続されている。コントローラ１４０は、ヒータ１１２、電力供給系１３０、真空排気系１２０及びガス導入系をそれぞれ制御する。 The plasma CVD apparatus 100 includes a vacuum chamber 110 and a stage 111 for supporting a substrate provided inside the vacuum chamber 110. The stage 111 has a heater 112 inside. Inside the vacuum chamber 110, a high frequency electrode 113 is disposed at a position facing the heater stage 111. The high frequency electrode 113 has a shower head 114, and the shower head 114 is provided with a gas diffusion plate 115 for uniformly diffusing the gas introduced from the gas introduction system and a plurality of ejection holes 116 for ejecting the gas. There is. Connected to the vacuum chamber 110 are a vacuum evacuation system 120, a power supply system 130 having a high frequency power source, a controller 140, and a gas introduction system (not shown). The controller 140 controls the heater 112, the power supply system 130, the vacuum exhaust system 120, and the gas introduction system, respectively.
　本実施形態では、プラズマＣＶＤの原料ガス（ＣＶＤガス）として、ＴＥＯＳ及びＯ２が用いられる。ＴＥＯＳとＯ２との流量比は、特に限定されず、例えば、Ｏ２／ＴＥＯＳ＝５０とすることができる。 In the present embodiment, TEOS and O 2 are used as a source gas (CVD gas) for plasma CVD. The flow ratio of TEOS and O 2 is not particularly limited, and, for example, O 2 / TEOS = 50 can be set.
　成膜条件は特に限定されず、例えばガラス基板サイズ７３０ｍｍ×９２０ｍｍの時は、以下の条件で実施される。
　　ＴＥＯＳ流量：３６０［ｓｃｃｍ］
　　Ｏ２流量：１６０００［ｓｃｃｍ］
　　プロセス圧力：１７５［Ｐａ］
　　ＲＦ周波数：２７．１２［ＭＨｚ］
　　ＲＦ電力：４０００［Ｗ］
　　ヒータ温度：３５０［℃］ The film formation conditions are not particularly limited, and for example, when the glass substrate size is 730 mm × 920 mm, the following conditions are implemented.
TEOS flow rate: 360 [sccm]
O 2 flow rate: 16000 [sccm]
Process pressure: 175 [Pa]
RF frequency: 27.12 [MHz]
RF power: 4000 [W]
Heater temperature: 350 [° C]
　〔第２の金属酸化物層の形成〕
　第２の金属酸化物層１２Ｂは、第１の金属酸化物層１２Ａを被覆するように形成される。第２の金属酸化物層１２Ｂは、ＡＬＤによって形成される。ＡＬＤ装置は特に限定されず、本実施形態では図５に概略的に示すＡＬＤ装置２００が用いられる。 [Formation of Second Metal Oxide Layer]
The second metal oxide layer 12B is formed to cover the first metal oxide layer 12A. The second metal oxide layer 12B is formed by ALD. The ALD apparatus is not particularly limited, and in the present embodiment, the ALD apparatus 200 schematically shown in FIG. 5 is used.
　ＡＬＤ装置２００は、真空チャンバ２１０と、真空チャンバ２１０の内部に設置された基板支持用のステージ２１１とを備える。ステージ２１１は、内部にヒータ２１２を有する。真空チャンバ２１０には、コントローラ２２０と、図示しないガス導入系及び真空排気系が配置されている。コントローラ２２０は、ヒータ２１２、ガス導入系及び真空排気系をそれぞれ制御する。 The ALD apparatus 200 includes a vacuum chamber 210 and a stage 211 for supporting a substrate provided inside the vacuum chamber 210. The stage 211 has a heater 212 inside. In the vacuum chamber 210, a controller 220, and a gas introduction system and an evacuation system (not shown) are disposed. The controller 220 controls the heater 212, the gas introduction system and the vacuum exhaust system, respectively.
　ガス導入系は、原料ガス、反応ガス及びパージガスをそれぞれ独立して、あるいは混合して真空チャンバ２１０内部に導入することが可能に構成される。本実施形態では、原料ガスとしてＴＭＡガスが、反応ガスとして水蒸気が、パージガスとしてＮ２ガスがそれぞれ用いられる。 The gas introduction system is configured to be capable of introducing the source gas, the reaction gas, and the purge gas independently or mixed into the vacuum chamber 210. In the present embodiment, TMA gas is used as the source gas, water vapor is used as the reaction gas, and N 2 gas is used as the purge gas.
　第２の金属酸化物層１２Ｂの形成に際しては、第一の工程として、ガス導入系から原料ガスとしてＴＭＡガスを真空チャンバ２１０に導入する。真空チャンバ２１０内に導入されたＴＭＡガスの分子は、基板１０の表面に吸着（化学吸着）する。基板１０の表面にＴＭＡガスの分子を吸着させた後、ガス導入系からのＴＭＡガスの導入を停止する。 In the formation of the second metal oxide layer 12B, as a first step, a TMA gas is introduced into the vacuum chamber 210 as a source gas from the gas introduction system. Molecules of TMA gas introduced into the vacuum chamber 210 are adsorbed (chemisorbed) on the surface of the substrate 10. After the molecules of the TMA gas are adsorbed on the surface of the substrate 10, the introduction of the TMA gas from the gas introduction system is stopped.
　被覆条件は、例えばガラス基板サイズ７３０ｍｍ×９２０ｍｍの時は、基板１０の温度を２５０℃、真空チャンバ２１０内の圧力を１００Ｐａ、ＴＭＡガスの導入量を３ｃｃ／ｃｙｃｌｅとすることができる。尚、以降の処理においても、基板１０の温度は２５０℃に設定している。 For example, when the glass substrate size is 730 mm × 920 mm, the temperature of the substrate 10 can be 250 ° C., the pressure in the vacuum chamber 210 can be 100 Pa, and the amount of TMA gas introduced can be 3 cc / cycle. The temperature of the substrate 10 is set to 250 ° C. also in the subsequent processing.
　次に、第二の工程として、ガス導入系からパージガスとしてＮ２ガスを導入する。パージガスにより真空チャンバ２１０内の圧力が高まり、原料ガスが押し出される。真空チャンバ２１０内に拡散していた原料ガスは、排気ポンプにより真空排気される。 Next, as a second step, N 2 gas is introduced as a purge gas from the gas introduction system. The pressure in the vacuum chamber 210 is increased by the purge gas, and the source gas is pushed out. The source gas diffused in the vacuum chamber 210 is evacuated by the exhaust pump.
　パージ条件は、Ｎ２ガスの導入時間を１秒、真空チャンバ２１０内の圧力を１００Ｐａ、Ｎ２ガスの流量を１０００ｓｃｃｍとした。 The purge conditions were such that the introduction time of the N 2 gas was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the flow rate of the N 2 gas was 1000 sccm.
　次に、第三の工程として、ガス導入系から反応ガスとして水蒸気を導入する。真空チャンバ２１０に導入された水蒸気は、基板１０の表面に付着していたＴＭＡガスの分子と反応してＴＭＡを酸化し、基板１０表面に酸化アルミニウム（Ａｌ２Ｏ３）の薄膜が形成される。反応後、ガス導入系からの反応ガスの導入を停止する。 Next, as a third step, water vapor is introduced as a reaction gas from the gas introduction system. The water vapor introduced into the vacuum chamber 210 reacts with the molecules of the TMA gas adhering to the surface of the substrate 10 to oxidize the TMA, and a thin film of aluminum oxide (Al 2 O 3 ) is formed on the surface of the substrate 10 . After the reaction, the introduction of the reaction gas from the gas introduction system is stopped.
　酸化条件は、真空チャンバ２１０内の圧力を１００Ｐａ、水蒸気の導入量を３ｃｃ／ｃｙｃｌｅとした。 The oxidation conditions were such that the pressure in the vacuum chamber 210 was 100 Pa, and the amount of water vapor introduced was 3 cc / cycle.
　次に、第四の工程として、ガス導入系からパージガスとしてＮ２ガスを導入する。パージガスにより真空チャンバ２１０内の圧力が高まり、水蒸気が押し出される。真空チャンバ２１０内に拡散していた水蒸気は、排気ポンプにより真空排気される。 Next, as a fourth step, N 2 gas is introduced as a purge gas from the gas introduction system. The pressure in the vacuum chamber 210 is increased by the purge gas and the water vapor is pushed out. The water vapor diffused in the vacuum chamber 210 is evacuated by an exhaust pump.
　パージ条件は、Ｎ２ガスの導入時間を１秒、真空チャンバ２１０内の圧力を１００Ｐａ、Ｎ２ガスの流量を１０００ｓｃｃｍとした。 The purge conditions were such that the introduction time of the N 2 gas was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the flow rate of the N 2 gas was 1000 sccm.
　薄膜が所望の厚みとなるまで上記第一～第四の工程を順に複数サイクル繰り返すことで、Ａｌ２Ｏ３薄膜からなる第２の金属酸化物層１２Ｂが形成される。 The first to fourth steps are sequentially repeated a plurality of cycles until the thin film has a desired thickness, whereby the second metal oxide layer 12B made of an Al 2 O 3 thin film is formed.
　（ゲート電極の形成工程）
　次に、図６に示すように、第２の金属酸化物層１２Ｂの上にゲート電極１３を形成する。 (Step of forming gate electrode)
Next, as shown in FIG. 6, the gate electrode 13 is formed on the second metal oxide layer 12B.
　ゲート電極１３は、典型的には、アルミニウム、モリブデン、銅、チタン等の金属単層膜又は金属多層膜で構成され、例えば、スパッタリング法によって形成される。ゲート電極１３は、上記金属膜を所定形状にパターニングすることによって形成される。 The gate electrode 13 is typically formed of a metal single layer film or metal multilayer film of aluminum, molybdenum, copper, titanium or the like, and is formed by, for example, a sputtering method. The gate electrode 13 is formed by patterning the metal film into a predetermined shape.
　（ソース領域及びドレイン領域の形成工程）
　続いて、図７に示すように、ソース領域１４Ｓ及びドレイン領域１４Ｄがそれぞれ形成される。 (Step of forming source region and drain region)
Subsequently, as shown in FIG. 7, a source region 14S and a drain region 14D are respectively formed.
　ソース領域１４Ｓ及びドレイン領域１４Ｄの形成方法は特に限定されず、本実施形態では、ゲート電極１３をマスクとしたイオン注入技術によって、活性層１１を構成するポリシリコン膜の所定領域にソース領域１４Ｓ及びドレイン領域１４Ｄがそれぞれ形成される。注入される不純物イオン（ドーパント）は、活性層１１の導電タイプ（Ｎ型、Ｐ型）に応じて適宜選択され、典型的には、ボロン（Ｂ）やリン（Ｐ）が用いられる。 The method of forming the source region 14S and the drain region 14D is not particularly limited, and in this embodiment, the source region 14S and the source region 14S are formed in predetermined regions of the polysilicon film forming the active layer 11 by ion implantation technology using the gate electrode 13 as a mask. Drain regions 14D are respectively formed. The impurity ions (dopant) to be implanted are appropriately selected according to the conductivity type (N type, P type) of the active layer 11, and typically, boron (B) or phosphorus (P) is used.
　（層間絶縁膜及びソース／ドレイン電極の形成工程）
　次に、図８に示すように、ゲート電極１３及び第２の金属酸化物層１２Ｂを覆うように層間絶縁膜１５を形成する。 (Step of forming interlayer insulating film and source / drain electrode)
Next, as shown in FIG. 8, an interlayer insulating film 15 is formed to cover the gate electrode 13 and the second metal oxide layer 12B.
　層間絶縁膜１５は、電気絶縁性材料で構成される。典型的には、シリコン酸化膜、シリコン窒化膜等の酸化膜又は窒化膜、さらにこれらの積層膜等で構成される。層間絶縁膜１５は、例えば、ＣＶＤ法、スパッタリング法によって形成される。 The interlayer insulating film 15 is made of an electrically insulating material. Typically, it is composed of an oxide film or nitride film such as a silicon oxide film or a silicon nitride film, and a laminated film of these. The interlayer insulating film 15 is formed by, for example, a CVD method or a sputtering method.
　続いて、ソース領域１４Ｓ及びドレイン領域１４Ｄに到達する開口部Ｄ１及びＤ２が、層間絶縁膜１５及びゲート絶縁膜１２を貫通するように形成される。開口部Ｄ１及びＤ２の形成方法は、特に限定されず、例えばレーザ加工技術やエッチング法等が用いられる。 Subsequently, openings D1 and D2 reaching the source region 14S and the drain region 14D are formed to penetrate the interlayer insulating film 15 and the gate insulating film 12. The method for forming the openings D1 and D2 is not particularly limited, and, for example, a laser processing technique, an etching method, or the like is used.
　その後、開口部Ｄ１及びＤ２を充填する金属膜が層間絶縁膜１５の上に形成され、当該金属膜を所定形状にパターニングすることで、ソース電極１６Ｓ及びドレイン電極１６Ｄが形成される。以上のようにして、図１に示す薄膜トランジスタ１が製造される。 Thereafter, a metal film filling the openings D1 and D2 is formed on the interlayer insulating film 15, and the metal film is patterned into a predetermined shape to form the source electrode 16S and the drain electrode 16D. As described above, the thin film transistor 1 shown in FIG. 1 is manufactured.
［本実施形態の作用］
　本実施形態において、ゲート絶縁膜１２は、第１の金属酸化物層１２Ａと第２の金属酸化物層１２Ｂとの積層膜で構成される。第２の金属酸化物層１２ＢがＡＬＤで成膜された酸化アルミニウム層で構成されるので、プラズマＣＶＤで成膜される酸化ケイ素単膜によるゲート絶縁膜と比べて、活性層１１に対する高い被覆率が得られる。 [Operation of this embodiment]
In the present embodiment, the gate insulating film 12 is formed of a laminated film of a first metal oxide layer 12A and a second metal oxide layer 12B. Since the second metal oxide layer 12B is formed of an aluminum oxide layer formed by ALD, the coverage with respect to the active layer 11 is higher than that of a gate insulating film made of a silicon oxide single film formed by plasma CVD. Is obtained.
　ここで、上述のように、Ａｌ２Ｏ３薄膜の単一層でゲート絶縁膜が構成される場合、フラットバンド電圧が正方向にシフトする傾向がある。また、ヒステリシス特性が発生しやすい。ヒステリシス特性を有するゲート絶縁膜を薄膜トランジスタに適用すると、薄膜トランジスタの閾値電圧が不安定になるおそれがある。 Here, as described above, when the gate insulating film is formed of a single layer of Al 2 O 3 thin film, the flat band voltage tends to shift in the positive direction. In addition, hysteresis characteristics are likely to occur. When a gate insulating film having hysteresis characteristics is applied to a thin film transistor, the threshold voltage of the thin film transistor may be unstable.
　発明者らは、ゲート絶縁膜の構成が異なる複数のサンプルをシリコンウェハ上に作製し、これらのフラットバンド電圧及びヒステリシス特性を評価した。 The inventors fabricated a plurality of samples having different gate insulating film configurations on a silicon wafer, and evaluated their flat band voltage and hysteresis characteristics.
　まず、ＡＬＤによって成膜されたＡｌ２Ｏ３薄膜の単一層からなるゲート絶縁膜を有するサンプル１と、プラズマＣＶＤによって成膜されたＴＥＯＳ－ＳｉＯｘ薄膜の単一層からなるゲート絶縁膜を有するサンプル２とを作製した。本実験例では、成膜装置に図４及び図５にそれぞれ示したプラズマＣＶＤ装置１００及びＡＬＤ装置２００を用いた。 First, Sample 1 having a gate insulating film consisting of a single layer of Al 2 O 3 thin film deposited by ALD, and Sample having a gate insulating film consisting of a single layer of TEOS-SiO x thin film deposited by plasma CVD 2 were produced. In this experiment, the plasma CVD apparatus 100 and the ALD apparatus 200 shown in FIG. 4 and FIG. 5 were used as the film forming apparatus.
　図９及び表１に、サンプル１，２におけるゲート絶縁膜の膜厚とフラットバンド電圧（Ｖfb）との関係を示す測定結果を示す。図９中、白抜き菱形記号はＡｌ２Ｏ３薄膜を、黒四角はＴＥＯＳ－ＳｉＯｘ薄膜をそれぞれ示す。 9 and Table 1 show measurement results showing the relationship between the film thickness of the gate insulating film and the flat band voltage (Vfb) in Samples 1 and 2. FIG. In FIG. 9, open diamonds indicate Al 2 O 3 thin films and black squares indicate TEOS-SiO x thin films.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　図１１及び表１より、ゲート絶縁膜がＴＥＯＳ－ＳｉＯｘ薄膜で構成されたサンプル２と比較して、ゲート絶縁膜がＡｌ２Ｏ３薄膜で構成されたサンプル１は、フラットバンド電圧が＋３Ｖ以上と正方向に大きくシフトしていることが確認される。 From FIG. 11 and Table 1, in comparison with sample 2 in which the gate insulating film is formed of a TEOS-SiO x thin film, sample 1 in which the gate insulating film is formed of an Al 2 O 3 thin film has a flat band voltage of +3 V or more And a large shift in the positive direction.
　次に、プラズマＣＶＤによって成膜された厚み５０ｎｍのＴＥＯＳ－ＳｉＯｘ薄膜とＡＬＤによって成膜された厚み５０ｎｍのＡｌ２Ｏ３薄膜との積層膜からなるゲート絶縁膜（本実施形態のゲート絶縁膜１２の構成に相当）を有するサンプル３を作製し、サンプル１とサンプル３のＣＶカーブを比較した。図１０及び図１１に、サンプル１，３のＣＶカーブ測定結果を示す。 Next, a gate insulating film made of a laminated film of a 50 nm thick TEOS-SiO x thin film deposited by plasma CVD and a 50 nm thick Al 2 O 3 thin film deposited by ALD (gate insulating film of this embodiment) Sample 3 having 12 configurations was produced, and CV curves of Sample 1 and Sample 3 were compared. 10 and 11 show CV curve measurement results of Samples 1 and 3. FIG.
　図１０より、ゲート絶縁膜がＡｌ２Ｏ３薄膜で構成されたサンプル１では、上述のようにフラットバンド電圧がプラスにシフトしている。また、ＣＶカーブ測定時の開始電圧がプラスの時とマイナスの時とでフラットバンド電圧に違いが生じ、ヒステリシス特性が発生していることが確認される。ＣＶカーブにヒステリシス特性が発生するということは、トランジスタ特性の閾値電圧が不安定にあることを意味するため、ゲート絶縁膜としては好ましくない。 As shown in FIG. 10, in the sample 1 in which the gate insulating film is formed of an Al 2 O 3 thin film, the flat band voltage is shifted to the positive as described above. In addition, it is confirmed that the flat band voltage is different between when the start voltage at the time of CV curve measurement is plus and minus when there is a hysteresis characteristic. The generation of the hysteresis characteristic in the CV curve means that the threshold voltage of the transistor characteristic is unstable, which is not preferable as a gate insulating film.
　一方、図１１より、ゲート絶縁膜がＴＥＯＳ－ＳｉＯｘ薄膜の上にＡｌ２Ｏ３薄膜を形成したサンプルでは、上記のＡｌ２Ｏ３薄膜のみのサンプルのようなヒステリシス特性は発生していないことが確認される。このように、シリコン基板上にＴＥＯＳ－ＳｉＯｘ薄膜とＡｌ２Ｏ３薄膜とが順に形成された二層構造の薄膜においては、ＣＶカーブのヒステリシス特性がほとんど発生しなくなることが確認された。 On the other hand, as shown in FIG. 11, in the sample in which the gate insulating film is an Al 2 O 3 thin film formed on the TEOS-SiO x thin film, the hysteresis characteristic like the above-mentioned sample of only Al 2 O 3 thin film is not generated. Is confirmed. As described above, it has been confirmed that the hysteresis characteristic of the CV curve hardly occurs in the thin film of the two-layer structure in which the TEOS-SiO x thin film and the Al 2 O 3 thin film are sequentially formed on the silicon substrate.
　以上の実験結果により、本実施形態の薄膜トランジスタ１においても、ゲート絶縁膜１２が、活性層１１の上にＴＥＯＳ－ＳｉＯｘで構成される第１の金属酸化物層１２Ａと、Ａｌ２Ｏ３で構成される第２の金属酸化物層１２Ｂとが順に形成された構造となっているため、ヒステリシス特性の発生を抑えることができる。これにより、薄膜トランジスタ１は、良好な閾値電圧制御が可能となる。 According to the above experimental results, also in the thin film transistor 1 of the present embodiment, the gate insulating film 12 is formed of the first metal oxide layer 12A composed of TEOS-SiO x and Al 2 O 3 on the active layer 11. Since the structured second metal oxide layer 12B and the second metal oxide layer 12B are sequentially formed, the occurrence of hysteresis characteristics can be suppressed. Thereby, the thin film transistor 1 can perform good threshold voltage control.
　続いて、本実施形態に係る薄膜トランジスタ１において、第２の金属酸化物層１２Ｂの膜厚を５０ｎｍに固定して、第１の金属酸化物層１２Ａの膜厚を０ｎｍ～８０ｎｍとした時におけるフラットバンド電圧Ｖｆｂ（Ｖ）、ヒステリシス（Ｖ）及び界面準位密度Ｄｉｔ（ｅＶ－１・ｃｍ－２）をそれぞれ測定した。上記各測定は、成膜直後及びアニール処理（５００℃）後にそれぞれ行った。 Subsequently, in the thin film transistor 1 according to the present embodiment, the flat when the thickness of the second metal oxide layer 12B is fixed to 50 nm and the thickness of the first metal oxide layer 12A is 0 nm to 80 nm. The band voltage Vfb (V), the hysteresis (V), and the interface state density Dit (eV -1 · cm -2 ) were measured, respectively. The above measurements were performed immediately after film formation and after annealing (500 ° C.).
　図１２～１４及び表２に、上記各測定により得られたフラットバンド電圧、ヒステリシス及び界面準位密度をそれぞれ示す。 12 to 14 and Table 2 show the flat band voltage, the hysteresis, and the interface state density obtained by each of the above measurements.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　図１２より、第１の金属酸化物層１２Ａ（ＴＥＯＳ－ＳｉＯｘ）の膜厚が２０ｎｍ以上８０ｎｍ以下のとき、フラットバンド電圧の絶対値はサンプル２と比較して低く、膜厚が大きくなるに従い、フラットバンド電圧が０に近づくことが確認される。
　また、図１３より、第１の金属酸化物層１２Ａ（ＴＥＯＳ－ＳｉＯｘ）の膜厚が２０ｎｍ以上８０ｎｍ以下のとき、アニール後においてはヒステリシス特性がほとんど発生していないことが確認される。
　なお、第１の金属酸化物層１２Ａが０ｎｍの時、ヒステリシス特性が発生していることが確認される。これは、上述したサンプル１に実質的に相当するものである。 From FIG. 12, when the film thickness of the first metal oxide layer 12A (TEOS-SiO x ) is 20 nm or more and 80 nm or less, the absolute value of the flat band voltage is lower compared to sample 2 and increases as the film thickness increases. It is confirmed that the flat band voltage approaches 0.
Further, it is confirmed from FIG. 13 that when the film thickness of the first metal oxide layer 12A (TEOS-SiO x ) is 20 nm or more and 80 nm or less, almost no hysteresis characteristic is generated after annealing.
When the first metal oxide layer 12A is 0 nm, it is confirmed that the hysteresis characteristic is generated. This substantially corresponds to the sample 1 described above.
　さらに、図１４より、第１の金属酸化物層１２Ａ（ＴＥＯＳ－ＳｉＯｘ）の膜厚が２０ｎｍ以上８０ｎｍ以下の時について、アニール処理後における界面準位密度が大きく低下していることが確認される。この結果については、次のように考えられる。第１の金属酸化物層１２Ａは、プラズマＣＶＤにより形成されるため、第１の金属酸化物層１２Ａ中に水素原子が含有される。当該水素原子は、アニール処理によって活性層１１と第１の金属酸化物層１２Ａとの界面に移動し、当該界面に存在するダングリングボンドを終端することで、界面準位密度を低下させたものと考えられる。 Further, it is confirmed from FIG. 14 that the interface state density after the annealing treatment is greatly reduced when the film thickness of the first metal oxide layer 12A (TEOS-SiO x ) is 20 nm or more and 80 nm or less. Ru. About this result, it is thought as follows. Since the first metal oxide layer 12A is formed by plasma CVD, hydrogen atoms are contained in the first metal oxide layer 12A. The hydrogen atoms are transferred to the interface between the active layer 11 and the first metal oxide layer 12A by annealing, and the interface state density is lowered by terminating dangling bonds present at the interface. it is conceivable that.
　以上のように、本実施形態の薄膜トランジスタ１においては、ゲート絶縁膜１２がＴＥＯＳ－ＳｉＯｘ薄膜からなる第１の金属酸化物層１２ＡとＡｌ２Ｏ３薄膜からなる第２の金属酸化物層１２Ｂとの積層構造を有するため、Ａｌ２Ｏ３のヒステリシス特性を発生させることなく、優れた閾値電圧制御が確保される。また、活性層１１に対して非常に高い被覆率でゲート絶縁膜１２を形成することができるため、ゲート電極１３と活性層１１との間のリーク電流を防いで、良好なスイッチング特性が得られる。 As described above, in the thin film transistor 1 of the present embodiment, the gate insulating film 12 includes the first metal oxide layer 12A formed of the TEOS-SiO x thin film and the second metal oxide layer 12B formed of the Al 2 O 3 thin film. The above-described laminated structure ensures excellent threshold voltage control without generating hysteresis characteristics of Al 2 O 3 . Further, since the gate insulating film 12 can be formed with a very high coverage to the active layer 11, leak current between the gate electrode 13 and the active layer 11 can be prevented, and good switching characteristics can be obtained. .
　さらに本実施形態によれば、活性層１１に対するゲート絶縁膜１２の良好な被覆率が得られるため、ゲート絶縁膜の薄膜化が可能となる。これにより、薄膜トランジスタの小型化、薄型化を図れるようになるため、表示装置の画素部分の開口率を上昇させることができる。また、薄膜トランジスタの動作電圧を下げることができるため、表示装置の消費電力を低減させることが可能となる。 Furthermore, according to the present embodiment, since a good coverage of the gate insulating film 12 with respect to the active layer 11 can be obtained, it is possible to reduce the thickness of the gate insulating film. Thus, the thin film transistor can be miniaturized and thinned, and the aperture ratio of the pixel portion of the display device can be increased. In addition, since the operating voltage of the thin film transistor can be reduced, power consumption of the display device can be reduced.
＜第２の実施形態＞
　図１５は、本発明の第２の実施形態に係る薄膜トランジスタ２の概略断面図である。以下、第１の実施形態と異なる構成について主に説明し、上述の実施形態と同様の構成については同様の符号を付しその説明を省略又は簡略化する。 Second Embodiment
FIG. 15 is a schematic cross-sectional view of a thin film transistor 2 according to a second embodiment of the present invention. Hereinafter, the configuration different from the first embodiment will be mainly described, and the same configuration as that of the above-described embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
　本実施形態の薄膜トランジスタ２は、ゲート絶縁膜２２の構成が第１の実施形態と異なる。具体的には、ゲート絶縁膜２２は、第１の金属酸化物層１２Ａと第２の金属酸化物層１２Ｂとの間に配置された中間層１２Ｃをさらに有する。 The thin film transistor 2 of the present embodiment differs from that of the first embodiment in the configuration of the gate insulating film 22. Specifically, the gate insulating film 22 further includes an intermediate layer 12C disposed between the first metal oxide layer 12A and the second metal oxide layer 12B.
　中間層１２Ｃは、多量の水素原子を含んだ水素リッチな層であり、例えば、プラズマＣＶＤ法で形成された窒化ケイ素（ＳｉＮｘ）あるいは酸窒化ケイ素（ＳｉＯｘＮｙ）から構成される。 The intermediate layer 12C is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is made of, for example, silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) formed by plasma CVD.
　中間層１２Ｃは、後述するアニール処理により、中間層１２Ｃ中に含まれる多量の水素原子が活性層１１と第１の金属酸化物層１２Ａとの界面に移動する。多量の水素原子が、当該界面に存在するダングリングボンドを終端し、界面準位密度を低下させる効果が得られる。 In the intermediate layer 12C, a large amount of hydrogen atoms contained in the intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process described later. A large amount of hydrogen atoms terminate dangling bonds present at the interface and an effect of reducing interface state density is obtained.
　中間層１２Ｃは、上記のように水素原子をダングリングボンドに供給する機能を有していれば、膜厚は特に限定されず、例えば、３ｎｍ以上３０ｎｍ以下である。 The thickness of the intermediate layer 12C is not particularly limited as long as it has a function of supplying hydrogen atoms to dangling bonds as described above, and is, for example, 3 nm or more and 30 nm or less.
　次に、中間層１２Ｃの形成方法について説明する。本実施形態では、ゲート絶縁膜の形成工程において、第１の金属酸化物層の形成工程の後に、中間層の形成工程を有する。なお、活性層の形成工程、ソース領域及びドレイン領域の形成工程、ゲート電極の形成工程、層間絶縁膜の形成工程、ソース電極及びドレイン電極の形成工程については第１の実施形態と同様であるため、ここでは説明を省略する。 Next, a method of forming the intermediate layer 12C will be described. In this embodiment, in the step of forming the gate insulating film, the step of forming an intermediate layer is included after the step of forming the first metal oxide layer. The process of forming the active layer, the process of forming the source and drain regions, the process of forming the gate electrode, the process of forming the interlayer insulating film, and the process of forming the source and drain electrodes are the same as in the first embodiment. , I omit the explanation here.
　中間層１２Ｃは、第１の金属酸化物層１２Ａの上に形成される。中間層１２Ｃの形成方法としては、中間層１２Ｃ中に水素原子が含有される方法であれば特に限定されず、例えば、プラズマＣＶＤが用いられる。本実施形態では、プラズマＣＶＤの原料ガスとして、ＳｉＨ４、ＮＨ３及びＮ２が用いられ、ＳｉＮｘから構成される中間層１２Ｃが形成される。中間層１２Ｃは成膜後、所定温度（例えば５００℃）でアニール処理される。アニール処理は、第２の金属酸化物層１２Ｂの形成前であってもよいし、その形成後であってもよい。ただし、中間層１２Ｃ中に含まれる水素原子を効率よく活性層１１と第１の金属酸化物層１２Ａとの界面に供給するためには、第２の金属酸化物層１２Ｂの成膜後にアニール処理を実施するのが望ましい。 The intermediate layer 12C is formed on the first metal oxide layer 12A. The method for forming the intermediate layer 12C is not particularly limited as long as it is a method in which a hydrogen atom is contained in the intermediate layer 12C. For example, plasma CVD is used. In the present embodiment, SiH 4 , NH 3 and N 2 are used as source gases for plasma CVD, and an intermediate layer 12 C composed of SiN x is formed. After the film formation, the intermediate layer 12C is annealed at a predetermined temperature (for example, 500 ° C.). The annealing may be performed before or after the formation of the second metal oxide layer 12B. However, in order to efficiently supply the hydrogen atoms contained in the intermediate layer 12C to the interface between the active layer 11 and the first metal oxide layer 12A, annealing treatment is performed after the second metal oxide layer 12B is formed. It is desirable to
　中間層１２Ｃを形成するプラズマＣＶＤ装置としては、特に限定されず、例えば図４を参照して説明したプラズマＣＶＤ装置１００が採用可能である。 The plasma CVD apparatus for forming the intermediate layer 12C is not particularly limited. For example, the plasma CVD apparatus 100 described with reference to FIG. 4 can be employed.
　中間層１２Ｃの成膜条件は特に限定されず、例えばガラス基板サイズ７３０ｍｍ×９２０ｍｍの時は、以下の条件で実施される。
　　ＳｉＨ４流量：５００［ｓｃｃｍ］
　　ＮＨ３流量：５０００［ｓｃｃｍ］
　　Ｎ２流量：７０００［ｓｃｃｍ］
　　プロセス圧力：２００［Ｐａ］
　　ＲＦ周波数：２７．１２［ＭＨｚ］
　　ＲＦ電力：４０００［Ｗ］
　　ヒータ温度：３５０［℃］ The film forming conditions for the intermediate layer 12C are not particularly limited. For example, when the glass substrate size is 730 mm × 920 mm, the following conditions are implemented.
SiH 4 flow rate: 500 [sccm]
NH 3 flow rate: 5000 [sccm]
N 2 flow rate: 7000 [sccm]
Process pressure: 200 [Pa]
RF frequency: 27.12 [MHz]
RF power: 4000 [W]
Heater temperature: 350 [° C]
　本実施形態によれば、上述の第１の実施形態と同様の作用効果を得ることができる。本実施形態においては、水素リッチな中間層１２Ｃに含まれる多量の水素原子が、アニール処理によって、活性層１１と第１の金属酸化物層１２Ａとの界面に移動する。多量の水素原子は、当該界面に存在するダングリングボンドを終端して、界面準位密度を低下させる。これにより、ゲート電極１３と活性層１１との間のリーク電流を防ぎ、良好なスイッチング特性を得ることが可能となる。 According to this embodiment, the same operation and effect as those of the above-described first embodiment can be obtained. In the present embodiment, a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by annealing. A large amount of hydrogen atoms terminate dangling bonds present at the interface to lower the interface state density. As a result, it is possible to prevent a leak current between the gate electrode 13 and the active layer 11, and to obtain good switching characteristics.
　また、本実施形態によれば、第２の金属酸化物層１２Ｂが水素バリア層として働き、中間層１２Ｃに含まれる水素原子が、アニール処理によって、活性層１１と第１の金属酸化物層１２Ａとの界面に移動し易くなる。これにより、当該界面の欠陥修復効果を高めることが可能となる。 Further, according to the present embodiment, the second metal oxide layer 12B functions as a hydrogen barrier layer, and the hydrogen atoms contained in the intermediate layer 12C are annealed to form the active layer 11 and the first metal oxide layer 12A. It is easy to move to the interface with This makes it possible to enhance the defect repair effect of the interface.
　本実施形態では、第１の金属酸化物層１２Ａの形成工程と、中間層１２Ｃの形成工程とは、同一チャンバ内で行われてもよい。これにより、被処理基板の入れ替えに伴う第１の金属酸化物層１２Ａ表面の汚染を防ぐことが可能となる。また、基板入れ替えの手間や機器のコストを削減することが可能となる。 In the present embodiment, the step of forming the first metal oxide layer 12A and the step of forming the intermediate layer 12C may be performed in the same chamber. This makes it possible to prevent the contamination of the surface of the first metal oxide layer 12A accompanying the replacement of the processing target substrate. Moreover, it becomes possible to reduce the effort of board | substrate replacement | exchange, and the cost of an apparatus.
　本実施形態に係る薄膜トランジスタ２の特性を評価するため、ゲート絶縁膜の構造を次のように変えて、界面準位密度Ｄｉｔ（ｅＶ－１・ｃｍ－２）を測定した。
　実験に用いた各薄膜トランジスタのゲート絶縁膜の構造は、第１の金属酸化物層１２Ａ（膜厚８０ｎｍ）のみの構造、第２の金属酸化物層１２Ｂ（膜厚８０ｎｍ）のみの構造、第１の金属酸化物層１２Ａ（膜厚５０ｎｍ）と第２の金属酸化物層１２Ｂ（膜厚５０ｎｍ）との二層構造、及び第１の金属酸化物層１２Ａ（膜厚５０ｎｍ）と第２の金属酸化物層１２Ｂ（膜厚５０ｎｍ）との間に中間層１２Ｃ（膜厚３ｎｍ）が配置された三層構造とした。界面準位密度の測定は、成膜直後及びアニール処理（５００℃）後にそれぞれ行った。 In order to evaluate the characteristics of the thin film transistor 2 according to this embodiment, the interface state density Dit (eV −1 · cm −2 ) was measured by changing the structure of the gate insulating film as follows.
The structure of the gate insulating film of each thin film transistor used in the experiment is the structure of only the first metal oxide layer 12A (film thickness 80 nm), the structure of only the second metal oxide layer 12B (film thickness 80 nm), the first Layer structure of the metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm), and the first metal oxide layer 12A (film thickness 50 nm) and the second metal An intermediate layer 12C (film thickness 3 nm) is disposed between the oxide layer 12B (film thickness 50 nm) and the three-layer structure. The interface state density was measured immediately after film formation and after annealing (500 ° C.).
　表３に、上記測定により得られた界面準位密度を示す。 Table 3 shows the interface state density obtained by the above measurement.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　表３より、ゲート絶縁膜が単膜である時と比べて、上記二層構造、及び上記三層構造では、アニール処理後の界面準位密度が低く、薄膜トランジスタ特性としては好ましい値となっていることが確認される。ゲート絶縁膜が上記三層構造の時の界面準位密度は、上記二層構造の時よりも低く、より好ましい値となっていることが確認される。これは、中間層１２Ｃに含まれる多量の水素原子が、アニール処理によって活性層１１と第１の金属酸化物層１２Ａとの界面に移動し、ダングリングボンドを終端することで、より一層界面準位密度を低下させたものと考えられる。これにより、薄膜トランジスタ２は、より優れたスイッチング特性を得ることができる。 According to Table 3, the interface state density after annealing is lower in the two-layer structure and the three-layer structure compared to when the gate insulating film is a single film, which is a preferable value for the thin film transistor characteristics. That is confirmed. It is confirmed that the interface state density when the gate insulating film has the above three-layer structure is lower than that of the above two-layer structure, which is a more preferable value. This is because the large amount of hydrogen atoms contained in the intermediate layer 12C is transferred to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process, and the dangling bond is terminated, so that the interface is further improved. It is considered that the rank density is lowered. Thereby, the thin film transistor 2 can obtain more excellent switching characteristics.
　また、この結果には、第２の金属酸化物層１２Ｂが水素バリア層として関与したことも考えられる。具体的には、第２の金属酸化物層１２Ｂが水素バリア層として働き、中間層１２Ｃに含まれる水素原子が、アニール処理によって、活性層１１と第１の金属酸化物層１２Ａとの界面に移動し易くなる。これにより、当該界面の欠陥修復効果を高めることが可能となる。 Moreover, it is also considered that the second metal oxide layer 12B was involved as a hydrogen barrier layer in this result. Specifically, the second metal oxide layer 12B functions as a hydrogen barrier layer, and hydrogen atoms contained in the intermediate layer 12C are annealed at the interface between the active layer 11 and the first metal oxide layer 12A. It becomes easy to move. This makes it possible to enhance the defect repair effect of the interface.
　次に、中間層１２Ｃの膜厚について考察する。本実施形態に係る薄膜トランジスタ２において、第１の金属酸化物層１２Ａ及び第２の金属酸化物層１２Ｂの膜厚をそれぞれ５０ｎｍに固定し、中間層１２Ｃの膜厚を０ｎｍ～３０ｎｍとした時について、界面準位密度Ｄｉｔ（ｅＶ－１・ｃｍ－２）を測定した。 Next, the film thickness of the intermediate layer 12C will be considered. In the thin film transistor 2 according to this embodiment, when the film thicknesses of the first metal oxide layer 12A and the second metal oxide layer 12B are fixed to 50 nm and the film thickness of the intermediate layer 12C is 0 nm to 30 nm. The interface state density Dit (eV -1 · cm -2 ) was measured.
　図１６及び表４に、上記測定により得られた界面準位密度を示す。 The interface state density obtained by the above measurement is shown in FIG. 16 and Table 4.
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
　図１６より、中間層１２Ｃは、３ｎｍであっても界面準位密度が低下することが確認される。中間層１２Ｃの膜厚が厚くなると共に、界面準位密度はさらに低下していき、実施例３－３の膜厚１０ｎｍで界面準位密度が最低値となることが確認される。一方、中間層１２Ｃの膜厚が１０ｎｍを超えてしまうと、界面準位密度は低下しなくなることが確認される。よって、中間層１２Ｃは、３ｎｍ以上１０ｎｍ以下の極薄い膜厚で十分に水素原子を供給する機能を有することが分かる。 From FIG. 16, it is confirmed that the interface state density decreases even if the intermediate layer 12C is 3 nm. As the film thickness of the intermediate layer 12C is increased, the interface state density is further decreased, and it is confirmed that the interface state density becomes the minimum value at the film thickness of 10 nm in Example 3-3. On the other hand, it is confirmed that when the film thickness of the intermediate layer 12C exceeds 10 nm, the interface state density does not decrease. Therefore, it is understood that the intermediate layer 12C has a function of supplying hydrogen atoms sufficiently with an extremely thin film thickness of 3 nm to 10 nm.
　続いて、ゲート絶縁膜の構造を次のように変えた薄膜トランジスタにおいて、薄膜トランジスタ特性（ＴＦＴ特性）値の測定を行った。各薄膜トランジスタのゲート絶縁膜の構造は、第１の金属酸化物層１２Ａ（膜厚１００ｎｍ）のみの構造、第１の金属酸化物層１２Ａ（膜厚５０ｎｍ）と第２の金属酸化物層１２Ｂ（膜厚５０ｎｍ）との二層構造（薄膜トランジスタ１）、及び第１の金属酸化物層１２Ａ（膜厚５０ｎｍ）と第２の金属酸化物層１２Ｂ（膜厚５０ｎｍ）との間に中間層１２Ｃ（膜厚１０ｎｍ）が配置された三層構造（薄膜トランジスタ２）とした。 Subsequently, in the thin film transistor in which the structure of the gate insulating film was changed as follows, the thin film transistor characteristic (TFT characteristic) value was measured. The structure of the gate insulating film of each thin film transistor is the structure of only the first metal oxide layer 12A (film thickness 100 nm), the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness A two-layer structure (thin film transistor 1) having a film thickness of 50 nm, and an intermediate layer 12C (a film thickness of 50 nm) between the first metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm) The three-layer structure (thin film transistor 2) in which the film thickness is 10 nm is disposed.
　ＴＦＴ特性値としては、移動度（ｃｍ２／Ｖｓ）及びサブスレッショルドスイング値（Ｓ値）（Ｖ／ｄｅｃ）を測定した。ＴＦＴ特性の測定は、上記各薄膜トランジスタのアニール処理（５００℃）後に行った。 As the TFT characteristic value, mobility (cm 2 / Vs) and subthreshold swing value (S value) (V / dec) were measured. The measurement of the TFT characteristics was performed after the annealing process (500 ° C.) of each thin film transistor.
　表５に、上記測定により得られた移動度及びＳ値を示す。 Table 5 shows the mobility and the S value obtained by the above measurement.
Figure JPOXMLDOC01-appb-T000005
Figure JPOXMLDOC01-appb-T000005
　表５より、ゲート絶縁膜が単層構造である時に比べて、二層構造あるいは三層構造では移動度が向上し、かつＳ値が小さくなることが確認される。
　移動度が向上した理由は、ＡＬＤで成膜されたＡｌ２Ｏ３の誘電率（約７．５）がＴＥＯＳ－ＳｉＯＸの誘電率（約４．５）よりも高いため、ＴＥＯＳ－ＳｉＯＸ単膜と比較して、酸化膜換算膜厚が薄くなり、同一電圧においてより多くのキャリアを生成することができるためと考えられる。また、ＡＬＤで成膜されたＡｌ２Ｏ３の水素バリア効果により、膜中の水素が界面のみならず膜中の欠陥を終端することで、ＴＥＯＳ－ＳｉＯＸ膜中の不要な電荷が無くなり、同様に同一電圧においてより多くのキャリアを生成するためと考えられる。 From Table 5, it is confirmed that the mobility is improved and the S value is decreased in the two-layer structure or the three-layer structure as compared with the case where the gate insulating film has a single-layer structure.
Why the mobility is improved is higher than the dielectric constant of Al 2 O 3 deposited by ALD (about 7.5) is the dielectric constant of the TEOS-SiO X (approximately 4.5), TEOS-SiO X This is considered to be because the equivalent oxide film thickness becomes thinner compared to a single film, and more carriers can be generated at the same voltage. Also, due to the hydrogen barrier effect of Al 2 O 3 deposited by ALD, the hydrogen in the film terminates defects not only at the interface but also in the film, eliminating unnecessary charges in the TEOS-SiO X film. It is also considered to generate more carriers at the same voltage as well.
　次に、Ｓ値が改善した理由については、上述のように第２の金属酸化物層１２Ｂが水素バリア層として機能し、第１の金属酸化物層１２Ａ中の水素原子が、活性層－ゲート絶縁膜界面の欠陥を効果的に修復することで界面準位密度が低下することに起因している。
　特に、ゲート絶縁膜が三層構造の時については、中間層１２Ｃを有することから、中間層１２Ｃ中の多量の水素原子により界面準位密度がさらに低下し、Ｓ値が特に好ましい値となっている。 Next, for the reason why the S value is improved, as described above, the second metal oxide layer 12B functions as a hydrogen barrier layer, and the hydrogen atoms in the first metal oxide layer 12A become the active layer-gate. This is because the interface state density is lowered by effectively repairing the defect at the insulating film interface.
In particular, when the gate insulating film has a three-layer structure, the interface state density is further reduced by the large amount of hydrogen atoms in the intermediate layer 12C because the intermediate layer 12C is provided, and the S value is particularly preferable There is.
　以上のように、本実施形態によれば、ゲート絶縁膜の良好な被覆率及び均一性が得られるため、ＴＦＴ特性に優れた薄膜トランジスタを得ることができる。 As described above, according to the present embodiment, since good coverage and uniformity of the gate insulating film can be obtained, a thin film transistor having excellent TFT characteristics can be obtained.
＜第３の実施形態＞
　図１７は、本発明の第３の実施形態に係る薄膜トランジスタ３の概略断面図である。以下、第１の実施形態と異なる構成について主に説明し、上述の実施形態と同様の構成については同様の符号を付しその説明を省略又は簡略化する。 Third Embodiment
FIG. 17 is a schematic cross-sectional view of a thin film transistor 3 according to a third embodiment of the present invention. Hereinafter, the configuration different from the first embodiment will be mainly described, and the same configuration as that of the above-described embodiment will be denoted by the same reference numeral, and the description thereof will be omitted or simplified.
　本実施形態の薄膜トランジスタ３において、ゲート絶縁膜３２は、第１の金属酸化物層１２Ａと第２の金属酸化物層１２Ｂとの間に配置された中間層１２Ｄをさらに有する点で、第１の実施形態と異なる。 In the thin film transistor 3 of the present embodiment, the gate insulating film 32 further includes an intermediate layer 12D disposed between the first metal oxide layer 12A and the second metal oxide layer 12B. It differs from the embodiment.
　中間層１２Ｄは、多量の水素原子を含んだ水素リッチな層であり、第１の金属酸化物層１２Ａを水素プラズマ処理することで形成される。中間層１２Ｄは、第２の実施形態の中間層１２Ｃと同様の効果を有する。中間層１２Ｄの厚みは特に限定されず、例えば、３ｎｍ以上１０ｎｍ以下である。 The intermediate layer 12D is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is formed by hydrogen plasma treatment of the first metal oxide layer 12A. The middle layer 12D has the same effect as the middle layer 12C of the second embodiment. The thickness of the intermediate layer 12D is not particularly limited, and is, for example, 3 nm or more and 10 nm or less.
　次に、中間層１２Ｄの形成方法について説明する。本実施形態では、ゲート絶縁膜の形成工程において、第１の金属酸化物層の形成工程の後に、中間層の形成工程を有する。なお、活性層の形成工程、ソース領域及びドレイン領域の形成工程、ゲート電極の形成工程、層間絶縁膜の形成工程、ソース電極及びドレイン電極の形成工程については第１の実施形態と同様であるため、ここでは説明を省略する。 Next, a method of forming the intermediate layer 12D will be described. In this embodiment, in the step of forming the gate insulating film, the step of forming an intermediate layer is included after the step of forming the first metal oxide layer. The process of forming the active layer, the process of forming the source and drain regions, the process of forming the gate electrode, the process of forming the interlayer insulating film, and the process of forming the source and drain electrodes are the same as in the first embodiment. , I omit the explanation here.
　中間層１２Ｄは、第１の金属酸化物層１２Ａの表面を水素プラズマ処理することで形成される。中間層１２Ｄの形成後、所定温度（例えば５００℃）でアニール処理される。アニール処理は、第２の金属酸化物層１２Ｂの形成前であってもよいし、その形成後であってもよい。ただし、中間層１２Ｄ中に含まれる水素原子を効率よく活性層１１と第１の金属酸化物層１２Ａとの界面に供給するためには、第２の金属酸化物層１２Ｂの成膜後にアニール処理を実施するのが望ましい。中間層１２Ｄは、アニール処理後、第１の金属酸化物層１２Ａに拡散する等して、消失してもよい。 The intermediate layer 12D is formed by hydrogen plasma treatment of the surface of the first metal oxide layer 12A. After the formation of the intermediate layer 12D, annealing is performed at a predetermined temperature (for example, 500 ° C.). The annealing may be performed before or after the formation of the second metal oxide layer 12B. However, in order to efficiently supply the hydrogen atoms contained in the intermediate layer 12D to the interface between the active layer 11 and the first metal oxide layer 12A, annealing treatment is performed after the second metal oxide layer 12B is formed. It is desirable to After the annealing process, the intermediate layer 12D may disappear by being diffused to the first metal oxide layer 12A.
　水素プラズマ処理するための装置としては、第１の金属酸化物層１２Ａの表面を水素プラズマ処理可能なプラズマ装置であれば特に限定されない。また、当該プラズマ装置は、水素プラズマ処理時に、被処理基板側の電極にバイアス電位を印加可能に構成されていてもよい。 The apparatus for performing hydrogen plasma processing is not particularly limited as long as it is a plasma apparatus capable of performing hydrogen plasma processing on the surface of the first metal oxide layer 12A. In addition, the plasma apparatus may be configured to be capable of applying a bias potential to the electrode on the side of the target substrate at the time of hydrogen plasma processing.
　成膜条件は特に限定されず、例えばガラス基板サイズ７３０ｍｍ×９２０ｍｍの時は、以下の条件で実施される。
　　Ｈ２流量：１０００［ｓｃｃｍ］
　　プロセス圧力：２００［Ｐａ］
　　ＲＦ周波数：２７．１２［ＭＨｚ］
　　ＲＦ電力：５００［Ｗ］
　　ヒータ温度：３５０［℃］ The film formation conditions are not particularly limited, and for example, when the glass substrate size is 730 mm × 920 mm, the following conditions are implemented.
H 2 flow rate: 1000 [sccm]
Process pressure: 200 [Pa]
RF frequency: 27.12 [MHz]
RF power: 500 [W]
Heater temperature: 350 [° C]
　本実施形態においても、上述の第１及び第２の実施形態と同様の作用効果を得ることができる。 Also in the present embodiment, the same function and effect as those of the above-described first and second embodiments can be obtained.
　以上、本発明の実施形態について説明したが、本発明は上述の実施形態にのみ限定されるものではなく種々変更を加え得ることは勿論である。 As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, of course, a various change can be added.
　例えば、以上の実施形態に用いられたプラズマＣＶＤ装置及びＡＬＤ装置は、上述の装置に限定されず、他の装置を用いてもよい。 For example, the plasma CVD apparatus and the ALD apparatus used in the above embodiments are not limited to the above-described apparatuses, and other apparatuses may be used.
　また、以上の実施形態において、第１の金属酸化物層の形成工程と、第２の金属酸化物層の形成工程とは、枚葉式マルチチャンバシステムあるいはインラインシステムにより行ってもよい。 In the above embodiment, the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed by a single wafer type multi-chamber system or an in-line system.
　上記各工程を枚葉式マルチチャンバシステムにより行う場合は、第１のチャンバ（第１の金属酸化物層形成のためのプラズマＣＶＤチャンバ）で第１の金属酸化物層の形成後、プラズマＣＶＤチャンバから被処理基板を取出し、次の第２のチャンバ（第２の金属酸化物層形成のためのＡＬＤチャンバ）に搬送して、基板処理を一枚ずつ行う。 When the above steps are performed by a single wafer type multi-chamber system, a plasma CVD chamber is formed after the formation of the first metal oxide layer in the first chamber (plasma CVD chamber for forming the first metal oxide layer) The substrate to be processed is taken out from the chamber and transferred to the next second chamber (ALD chamber for forming a second metal oxide layer) to perform substrate processing one by one.
　あるいは、上記各工程をインラインシステムにより行う場合は、例えば、ウォーキングビームや種々のコンベア等の搬送手段により被処理基板を搬送しながら、搬送方向に区画された第１の処理室（第１の金属酸化物層形成のためのプラズマＣＶＤ装置を有する）及び次の第２の処理室（第２の金属酸化物層形成のためのＡＬＤ装置を有する）でそれぞれ基板処理を行う。 Alternatively, in the case where the above steps are performed by an in-line system, for example, the first processing chamber (first metal) partitioned in the transport direction while transporting the substrate to be processed by transport means such as a walking beam or various conveyors. Substrate processing is performed in the following second processing chamber (having an ALD apparatus for forming a second metal oxide layer) and the next second processing chamber (having a plasma CVD apparatus for forming an oxide layer).
　上記の枚葉式マルチチャンバシステムあるいはインラインシステムにおいて、第１の金属酸化物層の形成工程と、第２の金属酸化物層の形成工程とは、真空雰囲気下で連続して行われてもよい。このように、基板処理工程を真空一貫とすることで、ガスや空気による基板表面の汚染を防ぐことが可能となる。 In the single wafer type multi-chamber system or the in-line system described above, the step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere. . As described above, by making the substrate processing process vacuum consistent, it is possible to prevent the contamination of the substrate surface by gas or air.
　また、以上の実施形態では、トップゲート型（スタガ型）構造の薄膜トランジスタを例として本発明を説明したが、ゲート電極が基板上に配置され、当該ゲート電極の上にゲート絶縁膜を挟んで活性層が配置された、ボトムゲート型（逆スタガ型）構造の薄膜トランジスタであっても本発明は適用可能である。 In the above embodiments, the present invention has been described by taking a thin film transistor of top gate type (stagger type) structure as an example, but the gate electrode is disposed on the substrate and activated with the gate insulating film interposed on the gate electrode. The present invention is applicable even to a thin film transistor having a bottom gate (inverted staggered) structure in which layers are disposed.
　また、上述した薄膜トランジスタは、液晶ディスプレイや有機ＥＬディスプレイ等のアクティブマトリクス型表示パネル用のＴＦＴとして用いることができる。これ以外に、上記トランジスタは、各種半導体装置あるいは電子機器のトランジスタ素子として用いることができる。 In addition, the thin film transistor described above can be used as a TFT for an active matrix display panel such as a liquid crystal display or an organic EL display. Besides the above, the transistor can be used as a transistor element of various semiconductor devices or electronic devices.
　１，２，３…薄膜トランジスタ
　１０…基板
　１１…活性層
　１２，２２，３２…ゲート絶縁膜
　１２Ａ…第１の金属酸化物層
　１２Ｂ…第２の金属酸化物層
　１２Ｃ，１２Ｄ…中間層
　１３…ゲート電極
　１４Ｓ…ソース領域
　１４Ｄ…ドレイン領域 1, 2, 3 Thin film transistor 10 Substrate 11 Active layer 12, 22 32 Gate insulating film 12A First metal oxide layer 12B Second metal oxide layer 12C, 12D Intermediate layer 13 Gate Electrode 14S: source region 14D: drain region

Claims (10)

  1. 　基板上に活性層を形成し、
    　ソース領域及びドレイン領域を、前記活性層と電気的に接続可能に形成し、
    　前記活性層の表面に、酸化ケイ素で構成される第１の金属酸化物層をプラズマＣＶＤで形成し、
    　前記第１の金属酸化物層の表面に、酸化アルミニウムで構成される第２の金属酸化物層をＡＬＤで形成し、
    　前記第２の金属酸化物層の表面に、ゲート電極を形成する
    　薄膜トランジスタの製造方法。     Form an active layer on the substrate,
    Forming a source region and a drain region so as to be electrically connectable to the active layer;
    A first metal oxide layer composed of silicon oxide is formed by plasma CVD on the surface of the active layer,
    The second metal oxide layer composed of aluminum oxide is formed by ALD on the surface of the first metal oxide layer,
    A gate electrode is formed on the surface of the second metal oxide layer.
  2. 　請求項１に記載の薄膜トランジスタの製造方法であって、
    　前記第１の金属酸化物層と前記第２の金属酸化物層との間に水素リッチな中間層を形成する工程と、
    　前記中間層をアニール処理する工程と、をさらに含む
    　薄膜トランジスタの製造方法。     A method of manufacturing a thin film transistor according to claim 1, wherein
    Forming a hydrogen-rich interlayer between the first metal oxide layer and the second metal oxide layer;
    Annealing the intermediate layer. A method of manufacturing a thin film transistor.
  3. 　請求項２に記載の薄膜トランジスタの製造方法であって、
    　前記第１の金属酸化物層を水素プラズマ処理することによって、前記中間層を形成する
    　薄膜トランジスタの製造方法。     A method of manufacturing a thin film transistor according to claim 2, wherein
    A method of manufacturing a thin film transistor, wherein the intermediate layer is formed by hydrogen plasma treatment of the first metal oxide layer.
  4. 　請求項２に記載の薄膜トランジスタの製造方法であって、
    　前記第１及び第２金属酸化物層の間に窒化ケイ素又は酸窒化ケイ素の層を形成することによって、前記中間層を形成する
    　薄膜トランジスタの製造方法。     A method of manufacturing a thin film transistor according to claim 2, wherein
    A method of manufacturing a thin film transistor, wherein the intermediate layer is formed by forming a layer of silicon nitride or silicon oxynitride between the first and second metal oxide layers.
  5. 　請求項４に記載の薄膜トランジスタの製造方法であって、
    　前記第１の金属酸化物層を形成する工程と、前記窒化ケイ素又は酸窒化ケイ素の層を形成する工程とは、同チャンバ内で行われる
    　薄膜トランジスタの製造方法。     5. The method of manufacturing a thin film transistor according to claim 4, wherein
    A method of manufacturing a thin film transistor, wherein the step of forming the first metal oxide layer and the step of forming the layer of silicon nitride or silicon oxynitride are performed in the same chamber.
  6. 　請求項１～５のいずれか１つに記載の薄膜トランジスタの製造方法であって、
    　前記第１の金属酸化物層を形成する工程と、前記第２の金属酸化物層を形成する工程とは、真空雰囲気中で連続して行われる
    　薄膜トランジスタの製造方法。     A method of manufacturing a thin film transistor according to any one of claims 1 to 5, wherein
    The step of forming the first metal oxide layer and the step of forming the second metal oxide layer are continuously performed in a vacuum atmosphere.
  7. 　ゲート電極と、
    　ポリシリコンで構成された活性層と、
    　前記活性層と電気的に接続されるソース領域及びドレイン領域と、
    　前記ゲート電極と前記活性層との間に配置され、酸化ケイ素で構成された第１の金属酸化物層と、前記第１の金属酸化物層と前記ゲート電極との間に配置され、酸化アルミニウムで構成された第２の金属酸化物層と、を含むゲート絶縁膜と
    　を具備する薄膜トランジスタ。     A gate electrode,
    An active layer composed of polysilicon,
    A source region and a drain region electrically connected to the active layer;
    A first metal oxide layer arranged between the gate electrode and the active layer and made of silicon oxide, and between the first metal oxide layer and the gate electrode, aluminum oxide And a gate insulating film including the second metal oxide layer constituted by the above.
  8. 　請求項７に記載の薄膜トランジスタであって、
    　前記ゲート絶縁膜は、前記第１の金属酸化物層と前記第２の金属酸化物層との間に、窒化ケイ素を含む中間層をさらに含む
    　薄膜トランジスタ。     8. The thin film transistor according to claim 7, wherein
    The gate insulating film further includes an intermediate layer containing silicon nitride between the first metal oxide layer and the second metal oxide layer.
  9. 　請求項７に記載の薄膜トランジスタであって、
    　前記ゲート絶縁膜は、前記第１の金属酸化物層と前記第２の金属酸化物層との間に、酸窒化ケイ素を含む中間層をさらに含む
    　薄膜トランジスタ。     8. The thin film transistor according to claim 7, wherein
    The gate insulating film further includes an intermediate layer containing silicon oxynitride between the first metal oxide layer and the second metal oxide layer.
  10. 　請求項８又は９に記載の薄膜トランジスタであって、
    　前記中間層の厚みは、３ｎｍ以上１０ｎｍ以下である
    　薄膜トランジスタ。     The thin film transistor according to claim 8 or 9,
    The thickness of the intermediate layer is 3 nm or more and 10 nm or less.
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