TW201528524A - Thin film transistor, method of manufacturing thereof, and application thereof - Google Patents

Abstract

The present invention relates to a thin film transistor. The thin film transistor comprises a substrate and a buffer layer is disposed on the substrate. The buffer layer comprises a n-layered silicon nitride layer; and a first silicon oxide layer is disposed over the n-layered silicon nitride layer, wherein the adjacent layers of the n-layered silicon nitride layer have different density and n is greater than or equal to 3. The thin film transistor of the present invention formed the n-layered silicon nitride layer and the buffer layer of the first silicon oxide layer by changing the film structure and film quality, which can enhance the barrier function of the buffer layer, effectively blocks metal ions of glass substrate upward diffusion, reduces defect centers of polysilicon layer and leakage current, improves quality of polysilicon back interface, prevents forming leakage pathways in polysilicon back interface, improves the stability of the polysilicon layer, thus improves film the reliability of the thin film transistors to enhance the yield and quality of the display device.

Description

Thin film transistor and manufacturing method and application thereof

The present invention relates to the field of semiconductors, and in particular to a thin film transistor and a method and application thereof.

Organic light-emitting displays (OLEDs) are considered to be the next-generation flat panel display technology due to their many advantages such as autonomous illumination, fast response, thinness, low power consumption, and flexible display. At present, OLED technology has been gradually applied to various electronic products, among which active matrix organic light-emitting display (AMOLED) has become superior in high image quality, short moving image response time, low power consumption, wide viewing angle and ultra-light and ultra-thin. The main trend in the development of OLEDs.

At present, polycrystalline germanium thin film transistors are often used in AMOLED backplane technology, and polycrystalline germanium thin film transistors have the advantages of low power consumption and large electron mobility. The process temperature of early polycrystalline germanium thin film transistors is as high as 1000 °C, so the choice of substrate material is greatly limited. Recently, due to the development of laser, the process temperature can be reduced to below 600 °C, and the substrate can use glass substrate. The polycrystalline germanium thin film transistor obtained by the process is also referred to as a low temperature polycrystalline germanium thin film transistor (LTPS TFT).

The aluminum, barium and sodium in the traditional bismuth glass have a high content of metals, which is easily diffused by the process heat cycle. In addition to the use of flawless glass, in the manufacturing process of the existing low-temperature polysilicon thin film transistor, one of the steps is to form a buffer layer on the substrate, and the buffer layer is formed to prevent metal ions in the substrate from diffusing to the LTPS active region to generate defect centers and thereby increase Leakage current, a suitable thickness of the buffer layer can also improve the quality of the back surface of the polysilicon, and reduce heat transfer, slow down the cooling rate of the laser heated by the laser, and help to form larger polycrystalline grains.

CN1012651311A discloses a method for preparing a low temperature polycrystalline germanium film, wherein the buffer layer is a two-layer structure SiN _x /SiO ₂ film or a single layer structure SiN _x or SiO ₂ film, and the double layer structure SiN _x /SiO ₂ film buffer layer The upper layer of the buffer layer is SiO ₂ and the lower layer is SiN _x on the substrate.

In the manufacture of polycrystalline germanium thin film transistors, there is a strict requirement for the content of impurities. The buffer layer of the prior art is less likely to completely block the diffusion of metal ions in the glass substrate. To solve this problem, the thickness of the buffer layer is generally increased to enhance the blocking. Capability, but an excessively thick buffer layer is prone to excessive residual stress and affects crystallization characteristics.

Therefore, there is a need for a reliable method for effectively improving the barrier layer blocking ability, manufacturing a buffer layer having a strong barrier ability, improving the stability of the polysilicon layer and improving the quality of the polysilicon back surface interface, thereby obtaining a thin film transistor with improved reliability, thereby obtaining A display device with improved yield and quality.

In view of the above problems, the inventors have long-term in-depth research, by changing the film-forming structure and film-forming film, forming a buffer layer having a multilayer structure of tantalum nitride and yttria, increasing a plurality of grain boundaries, and blocking metal ions from diffusing upward. This improves the reliability of the thin film transistor including the buffer layer of the multilayer laminated structure.

In one aspect, the present invention provides a thin film transistor comprising a substrate and a buffer layer disposed on the substrate, wherein the buffer layer comprises: n layers of tantalum nitride; and a first layer of tantalum oxide, The first ruthenium oxide layer is disposed on the n-layer tantalum nitride layer, wherein a density of two adjacent tantalum nitride layers in the n-layer tantalum nitride layer is different, and n is greater than or equal to 3, And n is a natural number.

In one embodiment of the invention, n is a natural number from 5 to 10.

In another embodiment of the present invention, each of the n-type tantalum nitride layers has a thickness of 50 to 100 Å.

In another embodiment of the invention, the first ruthenium oxide layer has a thickness of about 1500 Å.

In another embodiment of the present invention, the adjacent two layers of tantalum nitride layers further include an interface oxide layer.

In another embodiment of the invention, the interface oxide layer is a ruthenium oxide layer.

In another embodiment of the present invention, the buffer layer further includes a second ruthenium oxide layer disposed on the first ruthenium oxide layer, the second ruthenium oxide layer having a lower density than the first oxidized layer The density of the enamel layer.

In another embodiment of the invention, the second ruthenium oxide layer has a thickness of 500 to 1000 Å.

In another embodiment of the invention, the thin film transistor further includes a polysilicon layer disposed over the buffer layer.

In another aspect, the present invention provides a method of fabricating a thin film transistor, the method comprising:

Depositing n layers of tantalum nitride layer over the substrate, n is greater than or equal to 3, and n is a natural number, and deposition power of adjacent two layers of tantalum nitride layers in the n-layer tantalum nitride layer is different, so that the phase The density of the adjacent two layers of tantalum nitride is different;

Depositing a first hafnium oxide layer over the n-layer tantalum nitride layer to form a buffer layer in which the n-layer tantalum nitride layer and the first hafnium oxide layer are stacked;

An active layer is formed over the buffer layer.

In one embodiment of the method of the invention, n is a natural number from 5 to 10.

In another embodiment of the method of the present invention, the tantalum nitride layer has a thickness of 50 to 100 Å.

In another embodiment of the method of the present invention, the tantalum nitride layer has a deposition power of 500 to 1500 W.

In another embodiment of the method of the present invention, the deposition power of the adjacent two layers of tantalum nitride layers differs by 100 W.

In another embodiment of the method of the present invention, the first ruthenium oxide layer has a thickness of about 1500 Å.

In another embodiment of the method of the present invention, the deposition power of the first ruthenium oxide layer is not higher than 500 W.

In another embodiment of the method of the present invention, the depositing of the adjacent tantalum nitride layer further includes introducing an oxidizing gas to form an interface oxide layer.

In another embodiment of the method of the invention, the oxidizing gas is N ₂ O.

In another embodiment of the method of the present invention, the method further includes forming a second ruthenium oxide layer on the first ruthenium oxide layer, the second ruthenium oxide layer having a lower density than the first ruthenium oxide layer Density.

In another embodiment of the invention, the second ruthenium oxide layer has a thickness of 500 to 1000 Å.

In another embodiment of the method of the present invention, the second cerium oxide layer has a deposition power of not less than 1000 W.

In another embodiment of the method of the invention, the active layer is a polycrystalline germanium layer.

In still another aspect, the present invention provides the use of the above-described thin film transistor in an OLED.

The thin film transistor with the improved buffer layer of the present invention can form a buffer layer having a n-layer tantalum nitride layer and a layer of tantalum oxide layer by changing the film formation structure and the film formation film, thereby enhancing the barrier property of the buffer layer. Effectively blocking the metal ions in the glass substrate to diffuse upward, reducing the defect center of the polysilicon layer and reducing the leakage current, improving the quality of the polysilicon back surface interface, preventing the formation of leakage on the back surface of the polysilicon, improving the stability of the polysilicon layer, and further improving the film. The reliability of the transistor improves the yield and quality of the display device.

1‧‧‧Substrate
2‧‧‧buffer layer
21n‧‧‧ layer of tantalum nitride layer
22‧‧‧First ruthenium oxide layer
23‧‧‧Second ruthenium oxide layer
3‧‧‧Polysilicon layer
4‧‧‧ gate insulation
5‧‧‧ gate
6‧‧‧Interlayer dielectric layer
7‧‧‧Source/Drain

1 is a schematic structural view of a thin film transistor according to an embodiment of the present invention; FIG. 2 is a schematic structural view of a buffer layer according to an embodiment of the present invention; and FIG. 3 is a view showing a method of manufacturing a thin film transistor according to Embodiment 1 of the present invention. Flow chart.

The technical solution of the present invention will be further described below according to specific embodiments. The scope of the present invention is not limited to the following embodiments, and the examples are given for illustrative purposes only and are not intended to limit the invention in any way.

The present invention provides a thin film transistor. In a preferred embodiment, as shown in FIG. 1 and FIG. 2, the thin film transistor includes a substrate 1, a buffer layer 2, a polysilicon layer 3, a gate insulating layer 4, and a gate 5. Interlayer dielectric layer 6 and source/drain 7, wherein buffer layer 2 includes n layers of tantalum nitride layer 21, first tantalum oxide layer 22 disposed over n-layer tantalum nitride layer 21, and a first tantalum oxide layer The second hafnium oxide layer 23 above 22, the density of adjacent two tantalum nitride layers in the n-layer tantalum nitride layer 21 is different and n is greater than or equal to 3, and n is a natural number.

The yttria/tantalum nitride double layer structure acts as a buffer layer to block the diffusion of impurities in the glass substrate mainly by utilizing the barrier action of tantalum nitride itself and the grain boundary between tantalum nitride and tantalum oxide. According to the present invention, the n-layer tantalum nitride layer and the first tantalum oxide layer having different densities of two adjacent tantalum nitride layers are used as buffer layers, and the tantalum nitride layers form grain boundaries with each other to increase the number of grain boundaries. , thereby enhancing the ability of the buffer layer to block the diffusion of metal ions.

Since ruthenium oxide is more likely to form a better polycrystalline germanium than the tantalum nitride, and tantalum nitride is more effective in blocking contaminants from the substrate, it is preferable that the upper layer of the buffer layer is a ruthenium oxide layer and the lower layer is a tantalum nitride layer.

The buffer layer should have an appropriate thickness. The excessively thin buffer layer is less able to block the diffusion of metal ions, while the excessively thick buffer layer is prone to excessive residual stress and affects the crystallization characteristics, and the total thickness should be maintained below 3000 Å. A suitable thickness of the buffer layer can also improve the quality of the polysilicon back interface and reduce heat transfer, slowing the cooling rate of the laser heated germanium, and helping to form larger polycrystalline grains.

In order to increase the number of grain boundaries, the number of different density tantalum nitride layers should theoretically be as large as possible, but considering the complexity of the process and the production cost, n is preferably a natural number of 5-10.

The thickness of each of the tantalum nitride layers in the n-layer tantalum nitride layer should be substantially uniform, preferably 50 to 100 Å, to ensure sufficient diffusion of metal ions.

A denser first ruthenium oxide layer is formed over the n-layer tantalum nitride layer to ensure that the tantalum nitride layer is closely connected to the ruthenium oxide layer and adheres well, and the thickness of the first ruthenium oxide layer is preferably about 1500 Å.

An interface oxide layer is also formed between the adjacent two layers of tantalum nitride, and the interface oxide layer is tantalum oxide. Since the grain boundary between tantalum nitride and tantalum oxide is superior to the grain boundary between the different densities of tantalum nitride for the metal ions from the glass substrate, the interface oxide layer can effectively enhance the buffer layer to the metal Ion blocking ability.

A looser second ruthenium oxide layer is also formed on the first ruthenium oxide layer, so that the amorphous ruthenium has sufficient space to rearrange into a polycrystalline ruthenium structure, and the thickness of the second ruthenium oxide layer is preferably 500 to 1000 Å.

The present invention also provides a method for fabricating the above thin film transistor, comprising: depositing n layers of tantalum nitride layer on a substrate, n is greater than or equal to 3, and n is a natural number, adjacent to the n-layer tantalum nitride layer The deposition power of the two layers of tantalum nitride layers is different, so that the density of the adjacent two layers of tantalum nitride layers is different; a first layer of tantalum oxide is deposited on the n layers of tantalum nitride layers to form the n layers a buffer layer in which the tantalum nitride layer and the first tantalum oxide layer are stacked; an active layer is formed on the buffer layer.

For the above active layer, a polycrystalline germanium layer is preferred.

According to the present invention, the n-layer tantalum nitride layer and the ruthenium oxide layer constituting the thin film transistor buffer layer are both formed by chemical vapor deposition (CVD), and low pressure chemical vapor deposition, thermal vapor deposition, catalytic chemistry can be employed. A vapor deposition method, a plasma enhanced chemical vapor deposition method, or the like, among which plasma enhanced chemical vapor deposition is preferred. Plasma Enhanced Chemical Vapor Deposition (PECVD) is a commonly used low temperature film preparation technique that combines glow discharge and chemical vapor deposition. The basic principle is to use a low temperature plasma as an energy source to place the substrate on the glow discharge cathode. The appropriate reaction material gas is introduced, and the gas forms a series of thin films on the surface of the substrate through a series of chemical reactions and plasma reactions. PECVD has the advantages of low basic temperature, fast deposition rate and good film formation quality, and is widely used in the field of low temperature polycrystalline germanium film manufacturing.

As the raw material gas for forming the tantalum nitride layer, as the nitrogen source gas, NH ₃ , NH ₂ H ₂ N, N ₂ or the like can be used, and NH ₃ and N _{2 are} preferable. As the germanium source gas, SiH ₄ or Si can be used. ₂ H ₆ , SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ , SiH ₃ Cl ₃ , SiF ₄ or the like, preferably SiH ₄ .

The raw material gas to form silicon oxide layer, examples of the oxygen source gas may be used _{O 2, O 3, N 2} O and the like, preferably N ₂ O, as the silicon source gas using _{SiH 4, Si 2 H 6,} SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ , SiH ₃ Cl ₃ , SiF ₄ or the like, preferably SiH ₄ .

In order to form a film layer having different densities, it can be realized by adjusting process parameters such as a material gas type, a material gas flow rate ratio, a deposition power, and a deposition temperature, for example, the same material gas type and flow rate ratio and deposition temperature can be adjusted by adjusting The deposition power is used to control the density; the same source gas type and deposition temperature and deposition power can be used to control the density by adjusting the ratio of the material gas flow rate; the same material gas type and flow ratio and deposition can be used. Power, the density is controlled by adjusting the deposition temperature; in addition, multiple parameters can be adjusted simultaneously to achieve a more optimized effect.

Considering the complexity of the process and the production cost, it is preferable to control the density by adjusting the deposition power. Generally, a higher deposition power will result in a looser film layer, and a lower deposition power will result in a lower deposition power. A denser film layer.

In one embodiment of the method of the present invention, the deposition power of the adjacent two layers is different when the n-layer tantalum nitride layer is deposited, thereby causing different densities of adjacent two layers in the n-layer tantalum nitride layer. The deposition power of the n-layer tantalum nitride layer is preferably 500-1500 W, and at the same time, the grain boundary between the adjacent two layers of tantalum nitride layer has a certain blocking effect, and the density of the adjacent two layers of tantalum nitride layer should have Certainly different, so the deposition power of the adjacent two layers of tantalum nitride layer should have a certain difference, preferably 100W.

In another embodiment of the method of the present invention, an oxidizing gas is introduced between the deposited tantalum nitride layers to form an interface oxide layer, and the oxidizing gas may be O ₂ , O ₃ , N ₂ O, etc., preferably N ₂ O, The power of the oxidizing gas is not higher than 500W.

In another embodiment of the method of the present invention, the first ruthenium oxide layer is deposited at a first power, and the second ruthenium oxide layer is deposited at a second power, the first power being less than the second power, thereby causing the first ruthenium oxide layer The density is higher than the density of the second ruthenium oxide layer. The first power is preferably not higher than 500 W, the formed first ruthenium oxide layer is denser, and is closely connected to the tantalum nitride layer and adheres well; the second power is preferably not less than 1000 W, and the second oxidation is formed. The tantalum layer is looser and has better adaptability, so that the amorphous germanium has enough space to rearrange into a polycrystalline germanium structure.

It should be noted that the substrate, the polysilicon layer, the gate insulating layer, the gate electrode, the interlayer dielectric layer, and the source/drain electrodes in the thin film transistor of the present invention are not particularly limited, and materials and structures conventional in the art may be employed. And formed using conventional techniques. For example, the substrate may be a glass substrate, and the polysilicon layer may be formed by a laser annealing treatment of the amorphous germanium layer, and the gate insulating layer may be a tantalum nitride/yttria double layer stacked structure, and the gate may be aluminum, molybdenum, chromium, tungsten. The germanium, titanium, etc., the interlayer dielectric layer may be a tantalum nitride/yttria double layer stacked structure, and the source/drain may be doped with a polycrystalline germanium layer.

Since the thin film transistor of the present invention employs a buffer layer having an n-layer tantalum nitride layer and a first tantalum oxide layer, the buffer layer has a good ability to block metal ions from diffusing upward in the glass substrate, thereby ensuring stability of the polysilicon layer. The thin film transistor of the present invention has correspondingly good reliability.

The invention also provides the use of the above thin film transistor in an OLED. According to the thin film transistor of the present invention, since it has excellent reliability, the driving circuit switching element of the display device can effectively reduce the defective rate of the display device and improve the display quality.

Unless otherwise defined, the terms used in the present invention are intended to be understood by those skilled in the art.

The invention will now be further described in detail by way of examples.

Example

Comparative example 1

In the vacuum chamber, a radio frequency source with a radio frequency of 13.56 MHz is used to generate a low-temperature plasma as a gas reaction energy source, and the reaction gases, methane, ammonia and nitrogen, are introduced through a multi-channel gas inlet device to form a decane with ammonia. The gas flow ratio is set to 1:1~3, the deposition temperature is set to 420~430°C, and a thickness of 1000Å is deposited on the glass substrate by a PECVD method at a power of 500W;

In the same chamber, a radio frequency source with a radio frequency of 13.56 MHz is used to generate a low-temperature plasma as a gas reaction energy source, and the reaction gases medioxane and nitrous oxide are introduced through a multi-channel gas access device to form a decane with one The flow ratio of nitrous oxide is set to 1:40-50, the deposition temperature is set to 420-430 ° C, and a ruthenium oxide layer having a thickness of about 1500 Å is deposited by PECVD on the above-mentioned tantalum nitride layer at a power of 1000 W, thereby Forming a buffer layer of a tantalum nitride/yttria double layer structure;

Forming an amorphous germanium layer on the buffer layer;

Performing a laser annealing treatment on the amorphous germanium layer to transform the amorphous germanium layer into a polycrystalline germanium layer;

A gate insulating layer, a gate, an interlayer dielectric layer, and a source/drain are sequentially formed over the polysilicon layer.

The thin film transistor of Comparative Example 1 was subjected to leakage current measurement, and the measurement result was 1E-11 to 1E-12A.

Example 1

3 is a process flow diagram of a method for manufacturing a thin film transistor according to Embodiment 1 of the present invention, and is specifically described as follows:

a) using a radio frequency source with a radio frequency of 13.56 MHz in a vacuum chamber to generate a low-temperature plasma as a gas reaction energy source, and introducing a reaction gas of methooxane, ammonia, and nitrogen through a multi-channel gas inlet device to form a methotane. The flow rate ratio with ammonia gas is set to 1:1~3, the deposition temperature is set to 420~430°C, and the first tantalum nitride layer with a thickness of 100Å is deposited by PECVD on the glass substrate at a power of 500W. The parameters are shown in Table 1;

Table 1: Deposition process parameters of the first tantalum nitride layer

[0074] b) maintaining the above process conditions in the same chamber, changing only the RF power, and continuously depositing a second nitridation having a thickness of 100 Å over the formed first tantalum nitride layer at a second power of 600 W Layer

c) repeating step b, each deposition of the tantalum nitride layer increases the deposition power by 100 W, and co-deposits 10 layers of tantalum nitride;

d) in the same chamber, using a radio frequency source with a radio frequency of 13.56 MHz, generating a low temperature plasma as a gas reaction energy source, and introducing a reaction gas of methooxane and nitrous oxide through a multi-channel gas inlet device to form a methotoxane The flow ratio to nitrous oxide is set to 1:40-50, the deposition temperature is set to 420-430 ° C, and the first power of 500 W is deposited on the above-mentioned tantalum nitride layer by PECVD method to a thickness of about 1500 Å. The ruthenium oxide layer, the deposition process parameters are shown in Table 2;

Table 2: Deposition process parameters of the first ruthenium oxide layer

[0078] e) in the same chamber, maintaining the above process conditions, only changing the RF power, using a second power of 1000 W on the first ruthenium oxide layer by PECVD method to deposit a thickness of 500 ~ 1000 Å of second yttrium oxide a layer to form a buffer layer of an n-layer tantalum nitride layer and a two-layer tantalum oxide layer stack structure;

f) A polysilicon layer, a gate insulating layer, a gate, an interlayer dielectric layer, and a source/drain were sequentially formed on the buffer layer in the same manner and in the same manner as in Comparative Example 1.

The thin film transistor of Example 1 was subjected to leakage current measurement, and the measurement result was 1E-12A.

Example 2

a) using a radio frequency source with a radio frequency of 13.56 MHz in a vacuum chamber to generate a low-temperature plasma as a gas reaction energy source, and introducing a reaction gas of methooxane, ammonia, and nitrogen through a multi-channel gas inlet device to form a methotane. The flow rate ratio with ammonia gas is set to 1:1~3, the deposition temperature is set to 420~430°C, and the first tantalum nitride layer with a thickness of 100Å is deposited by PECVD on the glass substrate at a power of 500W. The parameters are shown in Table 3;

Table 3: Deposition process parameters of the first tantalum nitride layer

[0084] b) at a temperature of 420 ~ 430 ° C, N ₂ O is introduced into the chamber to form an interface oxide layer;

c) maintaining the above process conditions in the same chamber, changing only the RF power, and continuously depositing a second tantalum nitride layer having a thickness of 100 Å on the formed first tantalum nitride layer at a second power of 600 W;

d) repeating steps b) and c), each time depositing a tantalum nitride layer, the deposition power is increased by 100 W, and 10 layers of tantalum nitride layer are co-deposited;

e) in the same chamber, using a radio frequency source with a radio frequency of 13.56 MHz, generating a low temperature plasma as a gas reaction energy source, and introducing a reaction gas of methooxane and nitrous oxide via a multi-channel gas inlet device to form a methotoxane The flow ratio to nitrous oxide is set to 1:40-50, the deposition temperature is set to 420-430 ° C, and the first power of 500 W is deposited on the above-mentioned tantalum nitride layer by PECVD method to a thickness of about 1500 Å. The ruthenium oxide layer, the deposition process parameters are shown in Table 4;

Table 4: Deposition process parameters of the first ruthenium oxide layer

[0089] f) in the same chamber, maintaining the above process conditions, only changing the RF power, depositing a second layer of ruthenium oxide having a thickness of 500 to 1000 Å on the glass substrate at a second power of 1000 W, thereby forming an n layer a buffer layer comprising a tantalum nitride layer of an interface oxide layer and a two-layer yttria layer stack structure;

g) A polysilicon layer, a gate insulating layer, a gate, an interlayer dielectric layer, and a source/drain are sequentially formed on the buffer layer in the same manner and in the same manner as in Comparative Example 1.

Leakage current measurement was performed on the thin film transistor of Example 2, and the measurement result was less than 1E-12A. The leakage currents of Comparative Example 1, Example 1 and Example 2 were compared. The results are as follows: Leakage current of Comparative Example 1 > Leakage current of Example 1 > Leakage current of Example 2.

It can be seen that the buffer layer using the n-layer tantalum nitride and the first tantalum oxide layer structure can effectively reduce the leakage current compared with the prior art, and the addition of the interface oxide layer between the tantalum nitride layers can further reduce the leakage current.

In summary, the thin film transistor of the present invention forms a buffer layer having a n-layer tantalum nitride layer and a layer of tantalum oxide layer by changing the film formation structure and the film formation film, thereby enhancing the barrier property of the buffer layer and effectively blocking The metal ions in the glass substrate diffuse upward, reduce the defect center of the polysilicon layer and reduce the leakage current, improve the quality of the polysilicon back surface interface, prevent the formation of leakage in the back surface of the polysilicon, improve the stability of the polysilicon layer, and further improve the thin film transistor. Reliability, improve the yield and quality of the display device.

It should be understood by those skilled in the art that the presently described embodiments are merely exemplary, and that various alternatives, modifications and improvements are possible within the scope of the invention. Therefore, the present invention is not limited to the above embodiments, but is limited only by the scope of the patent application.

21‧‧‧n layer of tantalum nitride layer

22‧‧‧First ruthenium oxide layer

23‧‧‧Second ruthenium oxide layer

Claims (23)

A thin film transistor comprising a substrate and a buffer layer disposed on the substrate, wherein the buffer layer comprises:
a n-layer tantalum nitride layer; and a first hafnium oxide layer, the first hafnium oxide layer being disposed on the n-layer tantalum nitride layer, wherein two adjacent layers of the n-layer tantalum nitride layer are nitrided The densities of the crucible layers are different, and n is greater than or equal to 3, and n is a natural number. A thin film transistor according to the first aspect of the patent application, wherein n is a natural number of 5 to 10. The thin film transistor according to claim 2, wherein each of the n-layer tantalum nitride layers has a thickness of 50 to 100 Å. The thin film transistor according to claim 1, wherein the first ruthenium oxide layer has a thickness of 1500 Å. A thin film transistor according to claim 1, wherein the adjacent two layers of tantalum nitride further comprise an interface oxide layer. A thin film transistor according to claim 5, wherein the interface oxide layer is a ruthenium oxide layer. The thin film transistor according to claim 1, wherein the buffer layer further comprises a second ruthenium oxide layer disposed on the first ruthenium oxide layer, the second ruthenium oxide layer having a lower density than the Density of the first ruthenium oxide layer. The thin film transistor according to claim 7, wherein the second ruthenium oxide layer has a thickness of 500 to 1000 Å. The thin film transistor according to any one of claims 1 to 7, wherein the thin film transistor further comprises a polysilicon layer disposed over the buffer layer. The use of a thin film transistor according to any one of claims 1 to 9 in an OLED. A method of manufacturing a thin film transistor, comprising:
Depositing n layers of tantalum nitride layer over the substrate, n is greater than or equal to 3, and n is a natural number, and deposition power of adjacent two layers of tantalum nitride layers in the n-layer tantalum nitride layer is different, so that the phase The density of the adjacent two layers of tantalum nitride is different;
Depositing a first hafnium oxide layer over the n-layer tantalum nitride layer to form a buffer layer of the n-layer tantalum nitride layer and the first tantalum oxide layer; and forming an active layer on the buffer layer Floor. According to the method of claim 11, wherein n is a natural number of 5 to 10. The method of claim 12, wherein the tantalum nitride layer has a thickness of 50 to 100 Å. The method of claim 13, wherein the tantalum nitride layer has a deposition power of 500 to 1500 W. The method of claim 14, wherein the deposition power of the adjacent two layers of tantalum nitride layers differs by 100 W. The method of claim 11, wherein the first ruthenium oxide layer has a thickness of 1500 Å. The method of claim 16, wherein the first cerium oxide layer has a deposition power of not more than 500 W. According to the method of claim 11, the depositing of the adjacent tantalum nitride layer further includes forming an interface oxide layer by introducing an oxidizing gas. The method of claim 18, wherein the oxidizing gas is N ₂ O. The method of claim 11, further comprising forming a second ruthenium oxide layer on the first ruthenium oxide layer, the second ruthenium oxide layer having a lower density than the first ruthenium oxide layer degree. The method of claim 20, wherein the second ruthenium oxide layer has a thickness of 500 to 1000 Å. The method of claim 20, wherein the second cerium oxide layer has a deposition power of not less than 1000 W. The method of any one of clauses 11 to 22, wherein the active layer is a polycrystalline germanium layer.