TWI643012B - An lpts transistor and its display device - Google Patents

Abstract

A low-temperature polycrystalline silicon transistor includes a buffer layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer. The buffer layer includes a first silicon nitride layer and an oxide. A silicon layer; an active layer is disposed on the buffer layer and includes a source region, a drain region, a channel region, and a lightly doped region; the active layer is located between the buffer layer and the first insulating layer; A metal layer is disposed on the first insulating layer, and the first metal layer and the channel region have overlapping areas in a vertical projection direction, and are located between the first insulating layer and the second insulating layer. The second metal layer is located between the second insulating layer and the third insulating layer; wherein the thickness of the first silicon nitride layer is 130 to 250 nm, and the thickness of the silicon oxide layer is 150 ~ 300nm.

Description

Low-temperature polycrystalline silicon electric crystal and display device thereof

The invention relates to the technical field of low-temperature polycrystalline silicon, in particular to a low-temperature polycrystalline silicon thin film transistor and a display device thereof.

Low Temperature Poly-Silicon (LTPS) is a branch of poly-silicon technology. For LCD displays, the use of low-temperature polycrystalline silicon materials has many advantages, such as thin film circuits that can be made thinner and smaller, lower power consumption, and so on.

The advantages of low temperature polycrystalline silicon technology are: The thin film transistor circuit has a smaller area, a high aperture ratio, a large light-transmissive area, and a brighter overall picture; a higher resolution, a thin film transistor circuit has a small size and a high aperture ratio, and the corresponding LCD panel is easier to achieve high Resolution, and can have a better display.

In view of this, how to increase the electron mobility in the existing low-temperature polycrystalline silicon transistor structure to improve the response speed of LCD and the specifications of the product is a subject being studied by the relevant technical personnel in the industry.

An embodiment of the present invention relates to a low-temperature polycrystalline silicon transistor including: a buffer layer including a first silicon nitride layer and a silicon oxide layer; an active layer disposed on the buffer layer, wherein the active layer includes A source region, a drain region, a channel region, and a lightly doped region, the source region and the drain region are respectively located on two sides of the channel region, and the lightly doped region is located between the channel region and the channel region; Between the source region and between the channel region and the drain region; a first insulating layer disposed on the buffer layer so that the active layer is located between the buffer layer and the first insulation Between layers; a first metal layer provided on the first insulating layer, and the first metal layer and the channel region having an overlapping area in a vertical projection direction; a second insulating layer provided on the first insulating layer On the first insulating layer such that the first metal layer is located between the first insulating layer and the second insulating layer; a second metal layer disposed on the second insulating layer; and a first Three insulating layers disposed on the second insulating layer so that the second metal layer Between the second insulating layer and the third insulating layer; wherein said first silicon nitride layer having a thickness of 130 ~ 250nm, and the silicon oxide layer having a thickness of 150 ~ 300nm.

In the low-temperature polycrystalline silicon transistor according to the embodiment of the present invention, the thickness of the first silicon nitride layer is greater than 150 nm, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is 0.78 to 1. between.

The low-temperature polycrystalline silicon transistor according to the embodiment of the present invention, wherein the second insulating layer includes a second silicon nitride layer, and a thickness ratio of the first silicon nitride layer to the second silicon nitride layer is 0.4 ~ 0.67.

The low-temperature polycrystalline silicon transistor according to the embodiment of the present invention, wherein the electron mobility of the low-temperature polycrystalline silicon transistor is greater than or equal to 90 cm2 / (vcs).

An embodiment of the present invention also relates to a low-temperature polycrystalline silicon transistor including: a buffer layer including a first silicon nitride layer and a silicon oxide layer; an active layer disposed on the buffer layer, wherein the active layer Including a source region, a drain region, a channel region, and a lightly doped region, the source region and the drain region are respectively located on two sides of the channel region, and the lightly doped region is located on the channel region and Between the source region and between the channel region and the drain region; a first insulating layer is disposed on the buffer layer so that the active layer is located between the buffer layer and the first layer Between the insulating layers; a first metal layer disposed on the first insulating layer, and the first metal layer and the channel region have overlapping areas in a vertical projection direction; a second insulating layer disposed on the On the first insulating layer, the first metal layer is located between the first insulating layer and the second insulating layer; the second insulating layer includes a second silicon nitride layer; a second metal Layer on the second insulating layer; and a third insulating layer on the second insulating layer On the second insulating layer, so that the second metal layer is located between the second insulating layer and the third insulating layer; wherein the electron mobility of the low-temperature polycrystalline silicon transistor is greater than or equal to 90 cm2 / (vcs), The thickness ratio of the first silicon nitride layer to the second silicon nitride layer is between 0.4 and 0.97.

In the low-temperature polycrystalline silicon transistor according to the embodiment of the present invention, the thickness of the first silicon nitride layer is 130 to 250 nm, and the thickness of the silicon oxide layer is 150 to 300 nm.

In the low-temperature polycrystalline silicon transistor according to the embodiment of the present invention, the thickness of the first silicon nitride layer is greater than 150 nm, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is 0.78 to 1. between.

An embodiment of the present invention also relates to a display device, including: A color filter substrate includes a plurality of color filter structures; a thin-film transistor array substrate includes a plurality of first low-temperature polycrystalline silicon transistors, and the first low-temperature polycrystalline silicon transistors are respectively disposed corresponding to the color filter structures, wherein The first low-temperature polycrystalline silicon transistor uses the above-mentioned low-temperature polycrystalline silicon transistor; and a display molecular layer is disposed between the color filter substrate and the thin-film transistor array substrate.

The display device according to the embodiment of the present invention, wherein the color filter substrate and the thin film transistor array substrate can jointly define an adjacent display area and a peripheral area, and the first low-temperature polycrystalline silicon transistor is disposed In the display area.

The display device according to the embodiment of the present invention further includes a gate driving circuit disposed in the peripheral region, and the first low-temperature polycrystalline silicon transistor is electrically connected to the gate driving circuit, respectively.

According to the display device of the embodiment of the present invention, the gate driving circuit includes a plurality of second low-temperature polycrystalline silicon transistors, and the second low-temperature polycrystalline silicon transistor uses the above-mentioned low-temperature polycrystalline silicon transistors.

100‧‧‧Low temperature polycrystalline silicon transistor

110‧‧‧ substrate

120‧‧‧ buffer layer

121‧‧‧The first silicon nitride layer

122‧‧‧Silicon oxide layer

130‧‧‧Active Level

131‧‧‧Source area

132‧‧‧Drain

133‧‧‧Channel area

134‧‧‧lightly doped region

140‧‧‧first insulating layer

150‧‧‧ first metal layer

160‧‧‧Second insulation layer

170‧‧‧Second metal layer

180‧‧‧third insulating layer

161‧‧‧Second silicon nitride layer

200‧‧‧ thin film transistor array substrate

210‧‧‧The first low temperature polycrystalline silicon transistor

220‧‧‧Second Low Temperature Polycrystalline Silicon Transistor

230‧‧‧ pixels

300‧‧‧color filter substrate

400‧‧‧ Display molecular layer

500‧‧‧Gate driving circuit

600‧‧‧ display device

A1‧‧‧display area

A2‧‧‧Peripheral area

G1 ~ GN‧‧‧Gate line

In order to make the above and other objects, features, points, and embodiments of the present invention more comprehensible, the description of the drawings is as follows: FIG. 1 is a partial cross-section of a low temperature polycrystalline silicon transistor according to an embodiment of the present invention Schematic.

FIG. 2A is a schematic diagram of the electron mobility of a low-temperature polycrystalline silicon transistor according to an embodiment of the present invention.

FIG. 2B shows the electrons of a low temperature polycrystalline silicon transistor according to the prior art. Mobility diagram.

3 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.

FIG. 4 is a schematic top view of a display device according to an embodiment of the present invention.

In order to make the foregoing objects, features, and advantages of the present invention more comprehensible, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Numerous specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the meaning of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

See Figure 1. FIG. 1 is a schematic partial cross-sectional structure diagram of a low-temperature polycrystalline silicon transistor according to an embodiment of the present invention. An embodiment of the present invention provides a low-temperature polycrystalline silicon transistor 100. As shown in FIG. 1, the low-temperature polycrystalline silicon transistor 100 includes a substrate 110, a buffer layer 120, an active layer 130, a first insulating layer 140, a first metal layer 150, and a second The insulating layer 160, the second metal layer 170, and the third insulating layer 180. The buffer layer 120 is disposed on the substrate 110 and includes a first silicon nitride layer 121 and a silicon oxide layer 122. The active layer 130 is disposed on the buffer layer 120, and the active layer 130 includes a source region 131, a drain region 132, a channel region 133, and a light doped region 134, where the source region 131 and the drain region 132 are located on both sides of the channel region 133, respectively, and the lightly doped region 134 is located between the channel region 133 and the source region 131 and between the channel region 133 and the drain region 132. In this embodiment, The source region 131 and the drain region 132 are respectively a doped region N +, and the lightly doped region 134 is a doped region N-. The first insulating layer 140 is disposed on the buffer layer 120 such that the active layer 130 is located between the buffer layer 120 and the first insulating layer 140. In addition, the first metal layer 150 is patterned on the first insulating layer 140, and the channel region 133 of the first metal layer 150 and the active layer 130 has an overlapping area in a vertical projection direction. The second insulating layer 160 is disposed on the first insulating layer 140 such that the first metal layer 150 is located between the first insulating layer 140 and the second insulating layer 160. In addition, the second metal layer 170 is patterned on the second insulating layer 160, and the third insulating layer 180 is disposed on the second insulating layer 160, so that the second metal layer 170 is located on the second insulating layer 160 and the third insulating layer 180. between.

In this embodiment, the thickness of the first silicon nitride layer 121 of the buffer layer 120 is greater than 130 nm, and the thickness of the silicon oxide layer 122 of the buffer layer 120 is greater than 150 nm. In addition, in consideration of process cost and capacity limitations, the thickness of the first silicon nitride layer 121 is less than 250 nm, and the thickness of the silicon oxide layer 122 is less than 300 nm. In this embodiment, when only the thickness of the first silicon nitride layer 121 is increased and the thickness of the silicon oxide layer 122 is maintained, for example, if the thickness of the first silicon nitride layer 121 is increased to 130 nm to 250 nm, the thickness of the silicon oxide layer 122 is maintained as 100nm ~ 149nm, the effect is to increase the electron mobility of the low-temperature polycrystalline silicon transistor 100; when the thickness of the first silicon nitride layer 121 is kept unchanged, only the thickness of the silicon oxide layer 122 is increased, such as maintaining the first silicon nitride layer The thickness of 121 is 50 nm to 129 nm. Increasing the thickness of the silicon oxide layer 122 to 150 nm to 300 nm cannot increase the electron mobility of the low-temperature polycrystalline silicon transistor 100 directly. When the thickness of the first silicon nitride layer 121 and the silicon oxide layer 122 are both When increasing, if the thickness of the first silicon nitride layer 121 is increased to 130 nm to 250 nm, and the thickness of the silicon oxide layer 122 is increased to 150 nm to 300 nm, the effect is that the first silicon nitride layer 121 can increase H + (holes). Quantity, As a result, the electron mobility of the low-temperature polycrystalline silicon transistor 100 is increased, and the silicon oxide layer 122 can provide a sufficient distance during the hydrogenation process, so that H + (holes) can stably fall within the active layer 130.

Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a schematic diagram of the electron mobility of a low-temperature polycrystalline silicon transistor according to an embodiment of the present invention. As shown in FIG. 2A, when the thickness of the first silicon nitride layer 121 is increased to 160 nm, and the thickness of the silicon oxide layer 122 is increased to 190 nm, when the thickness of the second insulating layer 160 is 170 nm, the maximum electron mobility is about 93 cm2. / (vcs); When the thickness TILD of the second insulating layer 160 is 320 nm, the electron mobility is about 108 cm2 / (vcs) at the highest. FIG. 2B is a schematic diagram of the electron mobility of a low temperature polycrystalline silicon transistor according to the prior art. As shown in FIG. 2B, the thickness of the first silicon nitride layer 121 is maintained at 130 nm, and the thickness of the silicon oxide layer 122 is maintained at 165 nm. When the thickness of the second insulating layer 160 is 170 nm, the maximum electron mobility is about 83 cm2 / (vcs); When the thickness TILD of the second insulating layer 160 is 320 nm, the electron mobility is about 97 cm2 / (vcs) at the highest. It can be seen from FIG. 2A and FIG. 2B that after the thickness of the first silicon nitride layer 121 and the silicon oxide layer 122 is adjusted, the electron mobility significantly increases. It can be known from the foregoing that, compared with the prior art, in the embodiment, the embodiment of the present invention adjusts the thickness of the buffer layer 120, especially after increasing the thickness of the first silicon nitride layer 121 and the thickness of the silicon oxide layer 122, Without affecting the original manufacturing process, the electron mobility of the low-temperature polycrystalline silicon transistor 100 is increased, and it is applied to a fast-response display device to improve the product specifications.

In another embodiment of the present invention, following the first embodiment, the thickness of the first silicon nitride layer 121 of the buffer layer 120 is greater than 150 nm. In the buffer layer 120, the first silicon nitride layer 121 and the silicon oxide layer 122 Thickness ratio between 0.78 ~ 1 At this time, the thickness of the first silicon nitride layer 121 is between 150 and 234 nm, and the thickness of the silicon oxide layer 122 is between 150 and 300 nm. In this embodiment, when only the thickness of the first silicon nitride layer 121 is increased and the thickness ratio of the first silicon nitride layer 121 to the silicon oxide layer 122 is kept less than 0.78, if the thickness of the first silicon nitride layer 121 is increased, If it is larger than 150 nm, the thickness of the first silicon nitride layer 121 increases, which increases the hydrogenation effect, which can increase the electron mobility of the low-temperature polycrystalline silicon transistor 100, but the thickness of the silicon oxide layer 122 is relatively reduced. Excimer laser annealing (Excimer- Laser Annealing (ELA) process has a smaller window window, which will cause the crystallinity of polycrystalline silicon to deteriorate, and the electron mobility of low-temperature polycrystalline silicon transistor 100 will also decrease. When the thickness of the first silicon nitride layer 121 is kept constant and the thickness ratio of the first silicon nitride layer 121 to the silicon oxide layer 122 is 0.78 ~ 1, if the thickness of the first silicon nitride layer 121 is kept at 150 nm, The thickness of the silicon oxide layer 122 is relatively increased to reduce the transmittance of the silicon oxide layer 122. When only the thickness of the first silicon nitride layer 121 is increased and the thickness ratio of the first silicon nitride layer 121 to the silicon oxide layer 122 is 0.78 to 1, the hydrogenation effect in the process is improved, and the low-temperature polycrystalline silicon transistor 100 is increased. Electron mobility.

In still another embodiment of the present invention, following the first embodiment, the second insulating layer 160 includes a second silicon nitride layer 161, and the thickness of the first silicon nitride layer 121 of the buffer layer 120 is between 130 and 250 nm. When the electron mobility of the low-temperature polycrystalline silicon transistor 100 is greater than or equal to 90 cm 2 / (vcs), the thickness ratio of the first silicon nitride layer 121 to the second silicon nitride layer 161 is between 0.4 and 0.67. In this embodiment, when the thickness ratio of the first silicon nitride layer 121 to the second silicon nitride layer 161 is less than 0.4, the hydrogenation effect of the second insulating layer 160 may be deteriorated. When the thickness ratio of the first silicon nitride layer 121 to the second silicon nitride layer 161 is greater than 0.67, the hydrogenation of the buffer layer 120 The effect will be worse. When the thickness ratio of the first silicon nitride layer 121 and the second silicon nitride layer 161 is between 0.4 and 0.67, the hydrogenation effect of the buffer layer 120 is better, and the thickness of the second insulating layer 160 is moderate, which maintains a good The transmission rate will not affect the subsequent processes of hydrogenation and etching.

Please refer to Figure 3 and Figure 4. FIG. 3 is a schematic cross-sectional view of a display device according to an embodiment of the present invention, and FIG. 4 is a schematic top view of the display device according to an embodiment of the present invention. Please refer to FIG. 3 and FIG. 4 at the same time. A display device 600 in this embodiment includes a thin film transistor array substrate 200, a color filter substrate substrate 300, a display molecular layer 400, and a gate driving circuit 500. The thin film transistor array substrate 200 includes a substrate 110, a buffer layer 120, an active layer 130, a first insulating layer 140, a first metal layer 150, a second insulating layer 160, a second metal layer 170, and a third insulating layer 180. The structure of the low-temperature polycrystalline silicon transistor 100 is formed from these film layer structures, and the structure relationship is the same as that of the foregoing embodiment, and details are not described herein. The thin film transistor array substrate 200 can be further divided into a display area A1 and a peripheral area A2. The color filter substrate substrate 300 includes a color filter structure (not shown) and a light-shielding structure (not shown), of which the thin film transistor array substrate 200 The display area A1 corresponds to the color filter structure of the color filter substrate 300, and the thin film transistor array substrate 200 and the color filter substrate 300 are assembled and bonded, and the display molecular layer 400 is disposed on the thin film transistor array substrate 200 and the color filter. Between the light substrates 300. For example, when the display device 600 is a color display device, each pixel 230 has at least three colors, that is, each pixel 230 corresponds to three first low-temperature polycrystalline silicon transistors 210. In this embodiment, the first low-temperature polycrystalline silicon transistor 210 corresponding to each pixel 230 can be formed by the structural features of the foregoing embodiment, such as in the buffer layer 120 of the first low-temperature polycrystalline silicon transistor 210. The thickness of the first silicon nitride layer is greater than 130 nm and the thickness of the silicon oxide layer is greater than 150 nm. Alternatively, the thickness ratio of the first silicon nitride layer to the silicon oxide layer is between 0.78 and 1. In this way, the electron mobility of the transistor 210 of the display device 600 can be improved, power saving can be further achieved, and product reliability can be increased.

In this embodiment, the gate driving circuit 500 of the display device 600 is disposed in the peripheral region A2 and is located at the first low-temperature polycrystalline silicon transistor 210 of the pixel 230 through the gate lines G1 to GN and the gate driving circuit, respectively. 500 is electrically connected, as shown in FIG. 4, so that the gate driving circuit 500 provides a driving signal to the first low-temperature polycrystalline silicon transistor 210 to perform a driving display function. The gate driving circuit 500 includes a plurality of second low-temperature polycrystalline silicon transistors 220. For example, the gate driving circuit 500 includes a plurality of shift register circuits (not shown), and the shift register circuits are connected to each other in series to form a multi-level circuit, thereby providing multi-level driving signals to The first low-temperature polycrystalline silicon transistor 210 of the pixel 230 is activated. Each shift register circuit further includes a plurality of second low-temperature polycrystalline silicon transistors 220, and the second low-temperature polycrystalline silicon transistor 220 adopts the structure of the low-temperature polycrystalline silicon transistor 100 of the above embodiment.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (12)

A low-temperature polycrystalline silicon transistor includes: a buffer layer including a first silicon nitride layer and a silicon oxide layer; an active layer disposed on the buffer layer, wherein the active layer includes a source region, a A drain region, a channel region, and a lightly doped region, the source region and the drain region are located on both sides of the channel region, and the lightly doped region is located on the channel region and the source Between the polar regions and between the channel region and the drain region; a first insulating layer is disposed on the buffer layer so that the active layer is located between the buffer layer and the first insulating layer A first metal layer disposed on the first insulating layer, and the first metal layer and the channel region having an overlapping area in a vertical projection direction; a second insulating layer disposed on the first insulating layer An insulating layer such that the first metal layer is located between the first insulating layer and the second insulating layer; a second metal layer disposed on the second insulating layer; and a third insulating layer Layer disposed on the second insulating layer such that the second metal layer is located on the first insulating layer Insulating layer and the third insulating layer; wherein said first silicon nitride layer having a thickness of 130 ~ 250nm, and the silicon oxide layer having a thickness of 150 ~ 300nm. The low-temperature polycrystalline silicon transistor according to item 1 of the patent application scope, wherein the thickness of the first silicon nitride layer is greater than 150 nm, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is 0.78 ~ Between 1. The low-temperature polycrystalline silicon transistor according to item 1 or item 2 of the patent application scope, wherein the second insulating layer includes a second silicon nitride layer, and the first silicon nitride layer and the second nitride are The thickness ratio of the silicon layer is 0.4 to 0.67. The low-temperature polycrystalline silicon transistor according to item 3 of the patent application scope, wherein the electron mobility of the low-temperature polycrystalline silicon transistor is greater than or equal to 90 cm2 / (vcs). A low-temperature polycrystalline silicon transistor includes: a buffer layer including a first silicon nitride layer and a silicon oxide layer; an active layer disposed on the buffer layer, wherein the active layer includes a source region, a A drain region, a channel region, and a lightly doped region, the source region and the drain region are located on both sides of the channel region, and the lightly doped region is located on the channel region and the source Between the polar regions and between the channel region and the drain region; a first insulating layer is disposed on the buffer layer so that the active layer is located between the buffer layer and the first insulating layer A first metal layer disposed on the first insulating layer, and the first metal layer and the channel region having an overlapping area in a vertical projection direction; a second insulating layer disposed on the first insulating layer An insulating layer such that the first metal layer is located between the first insulating layer and the second insulating layer, wherein the second insulating layer includes a second silicon nitride layer; a second metal layer, Disposed on the second insulating layer; and a third insulating layer disposed on the second insulating layer Layer, so that the second metal layer is located between the second insulating layer and the third insulating layer; wherein the electron mobility of the low-temperature polycrystalline silicon transistor is greater than or equal to 90 cm2 / (vcs), and the The thickness ratio of the first silicon nitride layer to the second silicon nitride layer is between 0.4 and 0.97. The low-temperature polycrystalline silicon transistor according to item 5 of the application, wherein the thickness of the first silicon nitride layer is 130 to 250 nm, and the thickness of the silicon oxide layer is 150 to 300 nm. The low-temperature polycrystalline silicon transistor according to item 5 of the scope of the patent application, wherein the thickness of the first silicon nitride layer is greater than 150 nm, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is 0.78 ~ Between 1. A display device includes: a color filter substrate including a plurality of color filter structures; a thin film transistor array substrate including a plurality of first low-temperature polycrystalline silicon transistors, and the first low-temperature polycrystalline silicon transistors correspond to the respective ones A color filter structure is provided, wherein the first low-temperature polycrystalline silicon transistor is the low-temperature polycrystalline silicon transistor described in any one of claims 1 to 7; and a display molecular layer is disposed on the color filter substrate and the color filter substrate. Thin film transistor array substrate. The display device according to item 8 of the scope of patent application, wherein the color filter substrate and the thin film transistor array substrate can jointly define an adjacent display area and a peripheral area, and the first low-temperature polycrystalline silicon transistor Set in the display area. The display device according to item 9 of the scope of patent application, further comprising a gate driving circuit disposed in the peripheral region, and the first low-temperature polycrystalline silicon transistor is electrically connected to the gate driving circuit, respectively. The display device according to item 10 of the scope of patent application, wherein the gate driving circuit includes a plurality of second low-temperature polycrystalline silicon transistors, and the second low-temperature polycrystalline silicon transistor is any one of claims 1 to 7 The low temperature polycrystalline silicon transistor described above. A display device includes: a color filter substrate including a plurality of color filter structures; a thin film transistor array substrate including a plurality of first low-temperature polycrystalline silicon transistors, and the first low-temperature polycrystalline silicon transistors correspond to the respective ones A color filter structure is provided; a display molecular layer is provided between the color filter substrate and the thin film transistor array substrate; and a driving circuit includes a plurality of second low-temperature polycrystalline silicon transistors, and the first The low-temperature polycrystalline silicon transistor is electrically connected to the driving circuit, respectively; wherein the first low-temperature polycrystalline silicon transistor or the second low-temperature polycrystalline silicon transistor is the low-temperature polycrystalline silicon transistor described in any one of claims 1 to 7 .