CN108198862B - Low-temperature polycrystalline silicon transistor and display device thereof - Google Patents
Low-temperature polycrystalline silicon transistor and display device thereof Download PDFInfo
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- CN108198862B CN108198862B CN201711464991.9A CN201711464991A CN108198862B CN 108198862 B CN108198862 B CN 108198862B CN 201711464991 A CN201711464991 A CN 201711464991A CN 108198862 B CN108198862 B CN 108198862B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 73
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 69
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 69
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 33
- 239000010409 thin film Substances 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 239000002052 molecular layer Substances 0.000 claims description 3
- 238000001914 filtration Methods 0.000 claims 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 abstract 2
- 238000005984 hydrogenation reaction Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- Crystallography & Structural Chemistry (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Liquid Crystal (AREA)
Abstract
The invention relates to a low-temperature polycrystalline silicon transistor, which comprises a buffer layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer and a third insulating layer, wherein the buffer layer comprises a first silicon nitride layer and a silicon monoxide layer; the active layer is arranged on the buffer layer and comprises a source electrode region, a drain electrode region, a channel region and a light doped region; the active layer is positioned between the buffer layer and the first insulating layer; the first metal layer is arranged on the first insulating layer, has an overlapping area with the channel area in the vertical projection direction and is positioned between the first insulating layer and the second insulating layer; the second metal layer is positioned between the second insulating layer and the third insulating layer; wherein the first silicon nitride layer has a thickness of 130-250 nm, and the silicon oxide layer has a thickness of 150-300 nm.
Description
Technical Field
The invention relates to the technical field of low-temperature polycrystalline silicon, in particular to a low-temperature polycrystalline silicon thin film transistor and a display device thereof.
Background
Low Temperature Polysilicon (LTPS), is a branch of polysilicon technology. For LCD displays, there are many advantages to using low temperature polysilicon materials, such as thin film circuitry that can be made thinner and smaller, lower power consumption, etc.
The advantages of the low-temperature polysilicon technology are represented as follows:
the thin film transistor circuit has smaller area, high aperture ratio and large light-permeable area, and the whole picture is brighter; the liquid crystal display panel has the advantages of higher resolution, small circuit size of the thin film transistor, high aperture ratio, easiness in achieving high resolution of the corresponding LCD panel and capability of having more excellent display effect.
In view of this, how to increase electron mobility in the existing low-temperature polysilicon transistor structure to increase the LCD reaction speed and improve the product specification is a subject of research by those skilled in the art.
Disclosure of Invention
In view of the above problems, embodiments of the present invention provide a low temperature polysilicon transistor capable of improving electron mobility.
Specifically, embodiments of the present invention relate to a low temperature polysilicon transistor, including:
a buffer layer including a first silicon nitride layer and a silicon oxide layer;
the active layer is arranged on the buffer layer and comprises a source region, a drain region, a channel region and a lightly doped region, wherein the source region and the drain region are respectively positioned at two sides of the channel region, and the lightly doped region is positioned between the channel region and the source region and between the channel region and the drain region;
a first insulating layer disposed on the buffer layer such that the active layer is located between the buffer layer and the first insulating layer;
the first metal layer is arranged on the first insulating layer, and the first metal layer and the channel region are provided with an overlapping region in the vertical projection direction;
a second insulating layer disposed on the first insulating layer such that the first metal layer is located between the first insulating layer and the second insulating layer;
a second metal layer disposed on the second insulating layer;
a third insulating layer disposed on the second insulating layer such that the second metal layer is located between the second insulating layer and the third insulating layer;
the first silicon nitride layer is 130-250 nm thick, and the silicon oxide layer is 150-300 nm thick.
In the low temperature polysilicon transistor according to an embodiment of the present invention, the thickness of the first silicon nitride layer is greater than 150nm, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is 0.78-1.
In the low temperature polysilicon transistor according to the embodiment of the invention, the second insulating layer includes a second silicon nitride layer, and a thickness ratio of the first silicon nitride layer to the second silicon nitride layer is 0.4 to 0.67.
The low-temperature polysilicon transistor of the embodiment of the invention has the electron mobility of more than or equal to 90cm2/(vcs)。
Embodiments of the present invention also relate to a low temperature polysilicon transistor, including:
a buffer layer including a first silicon nitride layer and a silicon oxide layer;
the active layer is arranged on the buffer layer and comprises a source region, a drain region, a channel region and a lightly doped region, wherein the source region and the drain region are respectively positioned at two sides of the channel region, and the lightly doped region is positioned between the channel region and the source region and between the channel region and the drain region;
a first insulating layer disposed on the buffer layer such that the active layer is located between the buffer layer and the first insulating layer;
the first metal layer is arranged on the first insulating layer, and the first metal layer and the channel region are provided with an overlapping region in the vertical projection direction;
a second insulating layer disposed on the first insulating layer such that the first metal layer is located between the first insulating layer and the second insulating layer; the second insulating layer includes a second silicon nitride layer;
a second metal layer disposed on the second insulating layer; and
a third insulating layer disposed on the second insulating layer such that the second metal layer is located between the second insulating layer and the third insulating layer;
wherein the electron mobility of the low-temperature polysilicon transistor is greater than or equal to 90cm2(vs) and the thickness ratio of the first silicon nitride layer to the second silicon nitride layer is 0.4-0.97.
In the low temperature polysilicon transistor according to the embodiment of the invention, the thickness of the first silicon nitride layer is 130 to 250nm, and the thickness of the silicon oxide layer is 150 to 300 nm.
In the low temperature polysilicon transistor according to an embodiment of the present invention, the thickness of the first silicon nitride layer is greater than 150nm, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is 0.78-1.
Embodiments of the present invention also relate to a display device, including:
the color filter substrate comprises a plurality of color filter structures;
the thin film transistor array substrate comprises a plurality of first low-temperature polysilicon transistors, wherein the first low-temperature polysilicon transistors are respectively arranged corresponding to the color filter structure, and the first low-temperature polysilicon transistors adopt the low-temperature polysilicon transistors;
and the display molecular layer is arranged between the color filter substrate and the thin film transistor array substrate.
In the display device according to the embodiment of the invention, the color filter substrate and the thin film transistor array substrate may define an adjacent display area and a peripheral area together, and the first ltps transistor is disposed in the display area.
The display device according to an embodiment of the invention further includes a gate driving circuit disposed in the peripheral region, and the first ltps transistors are electrically connected to the gate driving circuit, respectively.
In the display device according to the embodiment of the invention, the gate driving circuit includes a plurality of second low temperature polysilicon transistors, and the second low temperature polysilicon transistors are the low temperature polysilicon transistors.
Drawings
Fig. 1 is a schematic partial cross-sectional view of a low-temperature polysilicon transistor according to an embodiment of the invention.
Fig. 2A is a schematic diagram of the electron mobility of a low temperature polysilicon transistor according to an embodiment of the invention.
Fig. 2B is a schematic diagram of electron mobility of a prior art low temperature polysilicon transistor.
Fig. 3 is a schematic cross-sectional view of a display device according to an embodiment of the invention.
Fig. 4 is a schematic top view of a display device according to an embodiment of the invention.
Wherein, the reference numbers:
100: low temperature polysilicon transistor 110: substrate 120: buffer layer
121: first silicon nitride layer 122: silicon oxide layer 130: active layer
131: source region 132: drain region 133: channel region
134: lightly doped region 140: first insulating layer 150: a first metal layer
160: second insulating layer 170: second metal layer 180: a third insulating layer
161: second silicon nitride layer
200: thin film transistor array substrate 210: a first low temperature polysilicon transistor
220: second low-temperature polysilicon transistor 230: pixel
300: color filter substrate 400: display molecule layer
500: gate drive circuit 600: display device
A1: display area a 2: peripheral zone
G1-GN: gate line
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Fig. 1 is a schematic partial cross-sectional view of a low-temperature polysilicon transistor according to an embodiment of the invention. An embodiment of the present invention provides a low temperature polysilicon transistor 100, as shown in fig. 1, the low temperature polysilicon transistor 100 includes a substrate 110, a buffer layer 120, an active layer 130, a first insulating layer 140, a first metal layer 150, a second insulating layer 160, a second metal layer 170, and a third insulating layer 180. The buffer layer 120 is disposed on the substrate 110 and includes a first silicon nitride layer 121 and a silicon oxide layer 122; the active layer 130 is disposed on the buffer layer 120, the active layer 130 includes a source region 131, a drain region 132, a channel region 133 and a lightly doped region 134, the source region 131 and the drain region 132 are respectively disposed at two sides of the channel region 133, and the lightly doped region 134 is disposed between the channel region 133 and the source region 131 and between the channel region 133 and the drain region 132. In the present embodiment, the source region 131 and the drain region 132 are respectively a doped region N +, and the lightly doped region 134 is a doped region N-. The first insulating layer 140 is disposed on the buffer layer 120, such that the active layer 130 is located between the buffer layer 120 and the first insulating layer 140. In addition, the first metal layer 150 is disposed on the first insulating layer 140 in a patterned manner, and the first metal layer 150 and the channel region 133 of the active layer 130 have an overlapping region in a vertical projection direction. The second insulating layer 160 is disposed on the first insulating layer 140, such that the first metal layer 150 is located between the first insulating layer 140 and the second insulating layer 160. In addition, the second metal layer 170 is disposed on the second insulating layer 160 in a patterned manner, and the third insulating layer 180 is disposed on the second insulating layer 160 such that the second metal layer 170 is located between the second insulating layer 160 and the third insulating layer 180.
In the present embodiment, the thickness of the first silicon nitride layer 121 of the buffer layer 120 is greater than 130nm, and the thickness of the silicon oxide layer 122 of the buffer layer 120 is required to be greater than 150 nm. In addition, the thickness of the first silicon nitride layer 121 is less than 250nm and the thickness of the silicon oxide layer 122 is less than 300nm in consideration of the process cost and the production energy limit. In the present embodiment, when only the thickness of the first silicon nitride layer 121 is increased while the thickness of the silicon oxide layer 122 is kept unchanged, such as increasing the thickness of the first silicon nitride layer 121 to 130nm to 250nm and keeping the thickness of the silicon oxide layer 122 to 100nm to 149nm, the electron mobility of the ltps transistor 100 can be increased; when the thickness of the first silicon nitride layer 121 is kept unchanged and the thickness of the silicon oxide layer 122 is only increased, if the thickness of the first silicon nitride layer 121 is kept between 50nm and 129nm and the thickness of the silicon oxide layer 122 is increased to between 150nm and 300nm, the electron mobility of the low temperature polysilicon transistor 100 cannot be directly increased; when the thicknesses of the first silicon nitride layer 121 and the silicon oxide layer 122 are increased, for example, the thickness of the first silicon nitride layer 121 is increased to 130nm to 250nm, and the thickness of the silicon oxide layer 122 is increased to 150nm to 300nm, the first silicon nitride layer 121 may increase the number of H + (holes) to increase the electron mobility of the low temperature polysilicon transistor 100, and the silicon oxide layer 122 may provide a sufficient distance during the hydrogenation process so that H + (holes) may stably fall within the active layer 130.
Fig. 2A is a schematic diagram of the electron mobility of a low temperature polysilicon transistor according to an embodiment of the invention. As shown in FIG. 2A, the thickness of the first silicon nitride layer 121 is increased to 160nm, the thickness of the silicon oxide layer 122 is increased to 190nm, and when the thickness T of the second insulating layer 160 is increasedILDAt 170nm, the electron mobility is up to about 93cm2(vcs), when the thickness T of the second insulating layer 160 is smallILDAt 320nm, the electron mobility is up to about 108cm2/(vcs). Fig. 2B is a schematic diagram of electron mobility of a prior art low temperature polysilicon transistor. As shown in FIG. 2B, the thickness of the first silicon nitride layer 121 is maintained at 130nm, the thickness of the silicon oxide layer 122 is maintained at 165nm, and the thickness T of the second insulating layer 160 is maintainedILDAt 170nm, the electron mobility is up to about 83cm2(vcs), when the thickness T of the second insulating layer 160 is smallILDAt 320nm, the electron mobility is up to about 97cm2/(vcs). As can be seen from fig. 2A and 2B, the electron mobility is significantly increased after the thicknesses of the first silicon nitride layer 121 and the silicon oxide layer 122 are adjusted. As can be seen from the above, in the embodiment, compared to the prior art, the thickness of the buffer layer 120 is adjusted, and particularly, after the thickness of the first silicon nitride layer 121 and the thickness of the silicon oxide layer 122 are respectively increased, the electron mobility of the ltps transistor 100 is increased without affecting the original process, so that the ltps transistor is applied to a fast-response display device to improve the specification of the product.
In another embodiment of the present invention, continuing from the first embodiment, the thickness of the first silicon nitride layer 121 of the buffer layer 120 is greater than 150nm, and the thickness ratio of the first silicon nitride layer 121 to the silicon oxide layer 122 in the buffer layer 120 is between 0.78-1, at this time, the thickness of the first silicon nitride layer 121 is between 150-234 nm, and the thickness of the silicon oxide layer 122 is between 150-300 nm. In the embodiment, when the thickness of the first silicon nitride layer 121 is increased to be less than 0.78 while the thickness ratio of the first silicon nitride layer 121 to the silicon oxide layer 122 is maintained to be less than 0.78, if the thickness of the first silicon nitride layer 121 is increased to be greater than 150nm, the thickness of the first silicon nitride layer 121 is increased, the hydrogenation effect is increased, and the electron mobility of the low temperature polysilicon transistor 100 can be increased, but the thickness of the silicon oxide layer 122 is relatively decreased, the window (window) of the Excimer Laser Annealing (ELA) process is decreased, which may cause the crystallization of polysilicon to be deteriorated, and may also cause the electron mobility of the low temperature polysilicon transistor 100 to be decreased. When the thickness ratio of the first silicon nitride layer 121 to the silicon oxide layer 122 is kept to be 0.78-1 while keeping the thickness of the first silicon nitride layer 121 constant, if the thickness of the first silicon nitride layer 121 is kept to be 150nm, the transmittance of the silicon oxide layer 122 is reduced due to the relative increase of the thickness of the silicon oxide layer 122. When the thickness of the first silicon nitride layer 121 is increased and the thickness ratio of the first silicon nitride layer 121 to the silicon oxide layer 122 is 0.78-1, the hydrogenation effect in the manufacturing process is improved, and the electron mobility of the low-temperature polysilicon transistor 100 is increased.
In another embodiment of the present invention, continuing the first embodiment, the second insulating layer 160 includes a second silicon nitride layer 161, and the first silicon nitride layer 121 of the buffer layer 120 has a thickness of 130-250 nm. When the electron mobility of the low-temperature polysilicon transistor 100 is greater than or equal to 90cm2When v (cs), the thickness ratio of the first silicon nitride layer 121 to the second silicon nitride layer 161 is 0.4 to 0.67. In the present embodiment, when the thickness ratio of the first silicon nitride layer 121 to the second silicon nitride layer 161 is less than 0.4, the hydrogenation effect of the second insulating layer 160 may be deteriorated. When the thickness ratio of the first silicon nitride layer 121 to the second silicon nitride layer 161 is greater than 0.67, the hydrogenation effect of the buffer layer 120 may be deteriorated. When the thickness ratio of the first silicon nitride layer 121 to the second silicon nitride layer 161 is between 0.4 and 0.67, the hydrogenation effect of the buffer layer 120 is good, and the thickness of the second insulating layer 160 is moderate, so that the better penetration rate is maintained, and the subsequent processes of hydrogenation and etching are not affected.
Fig. 3 is a schematic cross-sectional view of a display device according to an embodiment of the invention, and fig. 4 is a schematic top view of the display device according to the embodiment of the invention. Referring to fig. 3 and fig. 4, a display device 600 of the present embodiment mainly includes a thin film transistor array substrate 200, a color filter substrate 300, a display molecule layer 400, a gate driving circuit 500, and the like, wherein the thin film transistor array substrate 200 includes a substrate 110, a buffer layer 120, an active layer 130, a first insulating layer 140, a first metal layer 150, a second insulating layer 160, a second metal layer 170, and a third insulating layer 180, and the structure of the low temperature polysilicon transistor 100 can be formed by these film layer structures, and the structural relationship thereof is the same as that in the foregoing embodiments, and will not be described herein again. The tft array substrate 200 may further be divided into a display area a1 and a peripheral area a2, and the color filter substrate 300 includes a color filter structure (not shown) and a light-shielding structure (not shown), wherein the display area a1 of the tft array substrate 200 corresponds to the color filter structure of the color filter substrate 300, the tft array substrate 200 and the color filter substrate 300 are assembled and attached, and the display molecule layer 400 is disposed between the tft array substrate 200 and the color filter substrate 300. For example, when the display device 600 is a color display device, each pixel 230 has at least three colors, i.e., each pixel 230 corresponds to three first ltps transistors 210. In the present embodiment, the first low temperature polysilicon transistor 210 corresponding to each pixel 230 can be formed by the structural features of the above embodiments, for example, in the buffer layer 120 of the first low temperature polysilicon transistor 210, the thickness of the first silicon nitride layer is greater than 130nm, and the thickness of the silicon oxide layer is greater than 150nm, or the thickness ratio of the first silicon nitride layer to the silicon oxide layer is between 0.78-1. Thus, the electron mobility of the transistor 210 of the display device 600 can be improved, thereby further achieving power saving and product reliability.
In the present embodiment, the gate driving circuit 500 of the display device 600 is disposed in the peripheral region a2, and the first low temperature polysilicon transistors 210 located in the pixels 230 are electrically connected to the gate driving circuit 500 through the gate lines G1 to GN, as shown in fig. 4, so that the gate driving circuit 500 provides driving signals to the first low temperature polysilicon transistors 210 for driving the display function. The gate driving circuit 500 includes a plurality of second low temperature polysilicon transistors 220. For example, the gate driving circuit 500 includes a plurality of shift register circuits (not shown) connected in series to form a multi-stage circuit, so as to provide multi-stage driving signals to activate the first ltps transistors 210 of the pixels 230. Each shift register circuit further includes a plurality of second low temperature polysilicon transistors 220, and the second low temperature polysilicon transistors 220 adopt the structure of the low temperature polysilicon transistor 100 of the above embodiment.
The above-mentioned embodiments only express the preferred embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (11)
1. A low temperature polysilicon transistor comprising:
a buffer layer including a first silicon nitride layer and a silicon oxide layer;
the active layer is arranged on the buffer layer and comprises a source region, a drain region, a channel region and a lightly doped region, wherein the source region and the drain region are respectively positioned at two sides of the channel region, and the lightly doped region is positioned between the channel region and the source region and between the channel region and the drain region;
a first insulating layer disposed on the buffer layer such that the active layer is located between the buffer layer and the first insulating layer;
the first metal layer is arranged on the first insulating layer, and the first metal layer and the channel region are provided with an overlapping region in the vertical projection direction;
a second insulating layer disposed on the first insulating layer such that the first metal layer is located between the first insulating layer and the second insulating layer;
a second metal layer disposed on the second insulating layer;
a third insulating layer disposed on the second insulating layer such that the second metal layer is located between the second insulating layer and the third insulating layer;
the silicon oxide layer is 150-300 nm thick, the first silicon nitride layer is greater than 150nm and less than or equal to 250nm thick, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is 0.78-1.
2. The low temperature polysilicon transistor of claim 1, wherein the second insulating layer comprises a second silicon nitride layer, and a thickness ratio of the first silicon nitride layer to the second silicon nitride layer is 0.4 to 0.67.
3. The low temperature polysilicon transistor of claim 2, wherein the low temperature polysilicon transistor has an electron mobility of greater than or equal to 90cm2/(V·s)。
4. A low temperature polysilicon transistor comprising:
a buffer layer including a first silicon nitride layer and a silicon oxide layer;
the active layer is arranged on the buffer layer and comprises a source region, a drain region, a channel region and a lightly doped region, wherein the source region and the drain region are respectively positioned at two sides of the channel region, and the lightly doped region is positioned between the channel region and the source region and between the channel region and the drain region;
a first insulating layer disposed on the buffer layer such that the active layer is located between the buffer layer and the first insulating layer;
the first metal layer is arranged on the first insulating layer, and the first metal layer and the channel region are provided with an overlapping region in the vertical projection direction;
a second insulating layer disposed on the first insulating layer such that the first metal layer is located between the first insulating layer and the second insulating layer, wherein the second insulating layer includes a second silicon nitride layer;
a second metal layer disposed on the second insulating layer; and
a third insulating layer disposed on the second insulating layer such that the second metal layer is located between the second insulating layer and the third insulating layer;
wherein the electron mobility of the low-temperature polysilicon transistor is greater than or equal to 90cm2And V · s, and the thickness ratio of the first silicon nitride layer to the second silicon nitride layer is 0.4 to 0.67.
5. The LTPS-transistor of claim 4, wherein the first silicon nitride layer has a thickness of 130-250 nm and the silicon oxide layer has a thickness of 150-300 nm.
6. The LTPS-transistor of claim 4, wherein the first silicon nitride layer has a thickness greater than 150nm, and the thickness ratio of the first silicon nitride layer to the silicon oxide layer is between 0.78-1.
7. A display device, comprising:
the color filter substrate comprises a plurality of color filter structures;
a thin film transistor array substrate, comprising a plurality of first low temperature polysilicon transistors, and the first low temperature polysilicon transistors are respectively arranged corresponding to the color filter structure, wherein the first low temperature polysilicon transistors are the low temperature polysilicon transistors according to any one of claims 1 to 6;
and the display molecular layer is arranged between the color filter substrate and the thin film transistor array substrate.
8. The display device of claim 7, wherein the color filter substrate and the TFT array substrate together define adjacent display and peripheral regions, and the first LTPS transistor is disposed in the display region.
9. The display device according to claim 8, further comprising a gate driving circuit disposed in the peripheral region, wherein the first LTPS transistors are electrically connected to the gate driving circuit, respectively.
10. The display device according to claim 9, wherein the gate driving circuit comprises a plurality of second low temperature polysilicon transistors, and the second low temperature polysilicon transistors are the low temperature polysilicon transistors according to any one of claims 1 to 7.
11. A display device, comprising:
the color filter substrate comprises a plurality of color filter structures;
the thin film transistor array substrate comprises a plurality of first low-temperature polycrystalline silicon transistors, and the first low-temperature polycrystalline silicon transistors are respectively arranged corresponding to the color filtering structures;
the display molecular layer is arranged between the color filter substrate and the thin film transistor array substrate;
the driving circuit comprises a plurality of second low-temperature polysilicon transistors, and the first low-temperature polysilicon transistors are respectively electrically connected with the driving circuit;
wherein the first low temperature polysilicon transistor or the second low temperature polysilicon transistor is the low temperature polysilicon transistor of any one of claims 1 to 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711464991.9A CN108198862B (en) | 2017-12-28 | 2017-12-28 | Low-temperature polycrystalline silicon transistor and display device thereof |
| TW107108321A TWI643012B (en) | 2017-12-28 | 2018-03-12 | An lpts transistor and its display device |
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| CN201711464991.9A CN108198862B (en) | 2017-12-28 | 2017-12-28 | Low-temperature polycrystalline silicon transistor and display device thereof |
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| TWI643012B (en) | 2018-12-01 |
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