JP2013047852A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which realizes system-on-panel structure, without complicating processes for a TFT and further can suppress a cost.SOLUTION: In a liquid crystal display device, a pixel part comprises a pixel including a liquid crystal element and a TFT controlling voltage applied to the liquid crystal element. A TFT included by a driving circuit and the TFT controlling the voltage applied to the liquid crystal element comprise: a gate electrode; a gate insulating film formed on the gate electrode; a first semiconductor film overlapping with the gate electrode across the gate insulating film; and a couple of second semiconductor films formed on the first semiconductor film. Impurities which impart a one-conductivity type are added to the couple of the second semiconductor films. The first semiconductor film is formed of a semi-amorphous semiconductor.

Description

  The present invention relates to a liquid crystal display device using a thin film transistor in a driver circuit and a pixel portion.

In a liquid crystal display device formed using an inexpensive glass substrate, as the resolution increases, the ratio of the area around the pixel portion used for mounting (frame area) to the substrate tends to increase, and miniaturization tends to be hindered. . Therefore, it is considered that there is a limit to a method for mounting an IC formed using a single crystal silicon wafer on a glass substrate, and an integrated circuit including a driver circuit is integrally formed on the same glass substrate as a pixel portion. Technology, so-called system-on-panel construction, is regarded as important.

A thin film transistor using a polycrystalline semiconductor film (polycrystalline TFT) has a mobility that is two orders of magnitude higher than that of a TFT using an amorphous semiconductor film. It has the advantage that it can be integrally formed on top. However, as compared with the case where an amorphous semiconductor film is used, the process is complicated for crystallization of the semiconductor film, so that there is a problem that the yield is reduced and the cost is increased accordingly.

For example, in the case of a laser annealing method generally used for forming a polycrystalline semiconductor film, it is necessary to secure an energy density necessary for enhancing crystallinity. For this reason, there is a limit to the length of the long axis of the laser beam, which reduces the throughput in the crystallization process and causes variations in crystallinity in the vicinity of the edge of the laser beam. Yes. Further, since the energy of the laser beam itself varies, there is a disadvantage that the crystallinity of the semiconductor film varies and it is difficult to uniformly process the object to be processed.

However, the field effect mobility of a TFT in which a channel formation region is formed of an amorphous semiconductor film can be obtained only about 0.4 to 0.8 cm ² / V · sec at most. Therefore, although it can be used as a switching element in the pixel portion, high-speed operation is required such as a scanning line driving circuit for selecting a pixel and a signal line driving circuit for supplying a video signal to the selected pixel. It is considered that it is not suitable for a drive circuit.

In view of the above-described problems, an object of the present invention is to propose a liquid crystal display device that can realize system-on-panel without complicating the TFT process and can reduce costs.

In the present invention, a thin film transistor (TFT) is manufactured using a semi-amorphous semiconductor film in which crystal grains are dispersed in an amorphous semiconductor film, and the TFT is used in a pixel portion or a driver circuit to form a liquid crystal. A display device is manufactured. A TFT using a semi-amorphous semiconductor film has a mobility of ² to 10 cm ² / V · sec, which is 2 to 20 times the mobility of a TFT using an amorphous semiconductor film. A part or the whole of the pixel portion can be integrally formed on the same substrate as the pixel portion.

Unlike the polycrystalline semiconductor film, the semi-amorphous semiconductor film can be directly formed on the substrate as a semi-amorphous semiconductor film. Specifically, SiH ₄ is H ₂ and the flow ratio is 2 to 2.
The film can be formed using the plasma CVD method after being diluted 1000 times, preferably 10 to 100 times. A semi-amorphous semiconductor film manufactured using the above method has a thickness of 0.5 nm to
A microcrystalline semiconductor film containing 20 nm crystal grains in an amorphous semiconductor is also included. Therefore, unlike the case of using a polycrystalline semiconductor film, it is not necessary to provide a crystallization step after the semiconductor film is formed.
And since the length of the long axis of a laser beam has a limit like crystallization using a laser beam, the dimension of a board | substrate does not produce a restriction | limiting. Further, the number of steps in manufacturing the TFT can be reduced, and accordingly, the yield of the liquid crystal display device can be increased and the cost can be reduced.

In the present invention, a semi-amorphous semiconductor film may be used at least in the channel formation region. In addition, the channel formation region does not necessarily have to be a semi-amorphous semiconductor in the film thickness direction, and it is sufficient that at least a part of the channel formation region includes a semi-amorphous semiconductor.

The liquid crystal display device includes a panel provided with a liquid crystal element and a module in which an IC including a controller is mounted on the panel. Note that the liquid crystal element includes a pixel electrode, a counter electrode, and a liquid crystal provided between the pixel electrode and the counter electrode. Furthermore, the present invention relates to an element substrate corresponding to one mode before the liquid crystal element is completed in the process of manufacturing the liquid crystal display device, in which the potential of the video signal is applied to the pixel electrode of the liquid crystal element. Means for controlling are provided for each of the plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the liquid crystal element is formed, or after the conductive film to be the pixel electrode is formed, the pixel electrode is formed by patterning. The previous state may be used, and all forms are applicable.

The present invention can reduce the crystallization process of the semiconductor film after the film formation, and can realize the system-on-panel of the liquid crystal display device without complicating the TFT process.

Sectional drawing of the liquid crystal display device of this invention. FIG. 6 is a circuit diagram and a cross-sectional view of a pixel in a liquid crystal display device of the present invention. Sectional drawing of the liquid crystal display device of this invention. FIG. 4 is a diagram showing one embodiment of an element substrate in the liquid crystal display device of the present invention. FIG. 4 is a diagram showing one embodiment of an element substrate in the liquid crystal display device of the present invention. 1 is a block diagram illustrating a configuration of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. 4A and 4B illustrate a manufacturing process of a liquid crystal display device of the present invention. FIG. 3 is a diagram showing one mode of a semi-amorphous TFT in a liquid crystal display device of the present invention. FIG. 14 illustrates one mode of a shift register used in the liquid crystal display device of the present invention. 2A and 2B are a top view and a cross-sectional view of a liquid crystal display device of the present invention. FIG. 11 is a diagram of an electronic device using the liquid crystal display device of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

Next, the structure of the TFT used in the liquid crystal display device of the present invention will be described. FIG. 1 shows a cross-sectional view of a TFT used in a driver circuit and a cross-sectional view of a TFT used in a pixel portion. 10
1 corresponds to a cross-sectional view of a TFT used in a drive circuit, and 102 represents a TFT used in a pixel portion.
3 corresponds to a cross-sectional view, and 103 corresponds to a cross-sectional view of a liquid crystal element to which a current is supplied by the TFT 102. The TFTs 101 and 102 are of an inverted stagger type (bottom gate type). Semi-amorphous TFTs are more suitable for use in a drive circuit because n-type TFTs are higher in mobility than p-type, but in the present invention, TFTs may be either n-type or p-type. good. Regardless of which polarity TFT is used, it is desirable that all TFTs formed on the same substrate have the same polarity in order to reduce the number of steps.

The TFT 101 of the driver circuit overlaps with the gate electrode 110 formed on the first substrate 100, the gate insulating film 111 covering the gate electrode 110, and the gate electrode 110 with the gate insulating film 111 interposed therebetween. And a first semiconductor film 112 formed of a semi-amorphous semiconductor film. Further, the TFT 101 includes a pair of second semiconductor films 113 functioning as a source region or a drain region, and a third semiconductor film 114 provided between the first semiconductor film 112 and the second semiconductor film 113. doing.

In FIG. 1, the gate insulating film 111 is formed of two layers of insulating films, but the present invention is not limited to this structure. The gate insulating film 111 may be formed of a single layer or three or more layers of insulating films.

The second semiconductor film 113 is formed using an amorphous semiconductor film or a semi-amorphous semiconductor film, and an impurity imparting one conductivity type is added to the semiconductor film. The pair of second semiconductor films 113 are opposed to each other with a region where the channel of the first semiconductor film 112 is formed therebetween.

The third semiconductor film 114 is formed of an amorphous semiconductor film or a semi-amorphous semiconductor film, has the same conductivity type as that of the second semiconductor film 113, and yet has the second semiconductor film 113.
It has the characteristic that conductivity becomes lower than that. Since the third semiconductor film 114 functions as an LDD region, an electric field concentrated on the end portion of the second semiconductor film 113 functioning as a drain region can be relaxed and the hot carrier effect can be prevented. The third semiconductor film 114 is not necessarily provided, but the provision of the third semiconductor film 114 can increase the withstand voltage of the TFT and improve the reliability. Note that in the case where the TFT 101 is n-type, an n-type conductivity type can be obtained without adding an impurity imparting n-type in particular when the third semiconductor film 114 is formed. Therefore, TFT10
When 1 is n-type, it is not always necessary to add n-type impurities to the third semiconductor film 114.
However, an impurity imparting p-type conductivity is added to the first semiconductor film in which the channel is formed, and the conductivity type is controlled so as to be as close to the I-type as possible.

  A wiring 115 is formed so as to be in contact with the pair of third semiconductor films 114.

The TFT 102 of the driver circuit overlaps with the gate electrode 120 formed on the first substrate 100, the gate insulating film 111 covering the gate electrode 120, and the gate electrode 120 with the gate insulating film 111 interposed therebetween. And a first semiconductor film 122 formed of a semi-amorphous semiconductor film. Further, the TFT 102 includes a pair of second semiconductor films 123 functioning as a source region or a drain region, and a third semiconductor film 124 provided between the first semiconductor film 122 and the second semiconductor film 123. doing.

The second semiconductor film 123 is formed using an amorphous semiconductor film or a semi-amorphous semiconductor film, and an impurity imparting one conductivity type is added to the semiconductor film. The pair of second semiconductor films 123 face each other with a region where the channel of the first semiconductor film 122 is formed therebetween.

The third semiconductor film 124 is formed of an amorphous semiconductor film or a semi-amorphous semiconductor film, has the same conductivity type as that of the second semiconductor film 123, and yet has the second semiconductor film 123.
It has the characteristic that conductivity becomes lower than that. Since the third semiconductor film 124 functions as an LDD region, an electric field concentrated on the end portion of the second semiconductor film 123 functioning as a drain region can be relaxed and the hot carrier effect can be prevented. The third semiconductor film 124 is not necessarily provided, but the provision of the third semiconductor film 124 can increase the withstand voltage of the TFT and improve the reliability. Note that in the case where the TFT 102 is n-type, an n-type conductivity type can be obtained without adding an impurity imparting n-type in particular when the third semiconductor film 124 is formed. Therefore, TFT10
When 2 is n-type, it is not always necessary to add n-type impurities to the third semiconductor film 124.
However, an impurity imparting p-type conductivity is added to the first semiconductor film in which the channel is formed, and the conductivity type is controlled so as to be as close to the I-type as possible.

  A wiring 125 is formed so as to be in contact with the pair of third semiconductor films 124.

A first passivation film 140 and a second passivation film 141 made of an insulating film are formed so as to cover the TFTs 101 and 102 and the wirings 115 and 125. T
The passivation film covering the FTs 101 and 102 is not limited to two layers, and may be a single layer,
Three or more layers may be used. For example, the first passivation film 140 can be formed using silicon nitride, and the second passivation film 141 can be formed using silicon oxide. By forming the passivation film using silicon nitride or silicon nitride oxide, it is possible to prevent the TFTs 101 and 102 from being deteriorated by the influence of moisture, oxygen, or the like.

One of the wirings 125 is connected to the pixel electrode 130 of the liquid crystal element 103 through the wiring 160. An alignment film 131 is formed so as to be in contact with the pixel electrode 130. On the other hand, the second substrate 1 facing the first substrate 100 with the pixel electrode 130 interposed therebetween.
A counter electrode 171 and an alignment film 142 are sequentially stacked on the surface 70. A liquid crystal 143 is provided between the pixel electrode 130 and the alignment film 131 and the counter electrode 171 and the alignment film 142, and a portion where the pixel electrode 130, the liquid crystal 143, and the counter electrode 171 overlap is the liquid crystal element 103. It corresponds to. Note that the distance (cell gap) between the pixel electrode 130 and the counter electrode 171 is controlled by the spacer 161. In FIG. 1, the spacer 161 is formed by patterning the insulating film, but a spherical spacer prepared separately is used as the alignment film 13.
Alternatively, the cell gap may be controlled by being distributed over 1. 162 corresponds to a sealant, and the liquid crystal 143 can be sealed between the first substrate 100 and the second substrate 170 by the sealant 162.

A polarizing plate 150 is provided on the surface of the first substrate 100 opposite to the surface on which the TFT 101 and the TFT 102 are formed. A polarizing plate 151 is provided on the surface of the second substrate 170 opposite to the surface on which the counter electrode 171 is formed. The liquid crystal display device of the present invention is not limited to the configuration shown in FIG.

In the present invention, since the third semiconductor film including the channel formation region is formed using a semi-amorphous semiconductor, a TFT having higher mobility than a TFT using an amorphous semiconductor film can be obtained. Therefore, the driver circuit and the pixel portion can be formed over the same substrate.

Next, another structure of the pixel included in the liquid crystal display device of the present invention will be described. FIG. 2A illustrates one mode of a pixel circuit diagram, and FIG. 2B illustrates one mode of a cross-sectional structure of a pixel corresponding to FIG.

2A and 2B, 201 corresponds to a switching TFT for controlling input of a video signal to a pixel, and 202 corresponds to a liquid crystal element. Specifically, the potential of the video signal input to the pixel through the switching TFT 201 is supplied to the pixel electrode of the liquid crystal element 202. Note that reference numeral 203 corresponds to a capacitor for holding a voltage between the pixel electrode and the counter electrode of the liquid crystal element 202 when the switching TFT 201 is off.

Specifically, the switching TFT 201 has a gate electrode connected to the scanning line G, one of the source region and the drain region is connected to the signal line S, and the other is the pixel electrode 2 of the liquid crystal element 202.
04. One of two electrodes of the capacitor 203 is connected to the pixel electrode 204 of the liquid crystal element 202, and the other is supplied with a constant potential, preferably the same height as the counter electrode.

2A and 2B, the switching TFT 201 is connected in series,
In addition, a multi-gate structure has a structure in which a plurality of TFTs to which gate electrodes are connected share a first semiconductor film. With the multi-gate structure, the off-state current of the switching TFT 201 can be reduced. Specifically, FIG. 2 (A), FIG.
In (B), the switching TFT 201 has a configuration in which two TFTs are connected in series, but a multi-gate structure in which three or more TFTs are connected in series and a gate electrode is connected. It may be. The switching TFT does not necessarily have a multi-gate structure, and may be a normal single-gate TFT having a single gate electrode and channel formation region.

Next, a mode of the TFT included in the liquid crystal display device of the present invention, which is different from those in FIGS. 1 and 2, will be described. FIG. 3 shows a cross-sectional view of a TFT used in a driver circuit and a cross-sectional view of a TFT used in a pixel portion. 301 corresponds to a cross-sectional view of a TFT used in a driver circuit, 302 corresponds to a cross-sectional view of a switching TFT used in a pixel portion, and 303 corresponds to a cross-sectional view of a liquid crystal element.

The TFT 301 of the driving circuit and the TFT 302 of the pixel portion are formed of gate electrodes 310 and 320 formed on the substrate 300, a gate insulating film 311 covering the gate electrodes 310 and 320,
First semiconductor films 312 and 322 formed of semi-amorphous semiconductor films, which overlap with the gate electrodes 310 and 320 with the gate insulating film 311 interposed therebetween, are provided. Then, channel protective films 330 and 331 made of an insulating film are formed so as to cover the channel formation regions of the first semiconductor films 312 and 322. The channel protective films 330 and 331 are provided in order to prevent the channel formation regions of the first semiconductor films 312 and 322 from being etched in the manufacturing process of the TFTs 301 and 302. Furthermore, TFT 301, 302
Is a pair of second semiconductor films 313 and 323 which function as a source region or a drain region.
And a third semiconductor film 31 provided between the first semiconductor film 312 and the second semiconductor film 313.
4 and 324, respectively.

In FIG. 3, the gate insulating film 311 is formed of two insulating films, but the present invention is not limited to this structure. The gate insulating film 311 may be formed of a single layer or three or more layers of insulating films.

The second semiconductor films 313 and 323 are formed using an amorphous semiconductor film or a semi-amorphous semiconductor film, and an impurity imparting one conductivity type is added to the semiconductor film. The pair of second semiconductor films 313 and 323 face each other with a region where the channel of the first semiconductor film 312 is formed therebetween.

The third semiconductor films 314 and 324 are formed of an amorphous semiconductor film or a semi-amorphous semiconductor film, have the same conductivity type as the second semiconductor films 313 and 323, and are second
The semiconductor films 313 and 323 have characteristics that make the conductivity lower. Since the third semiconductor films 314 and 324 function as LDD regions, the second semiconductor films 314 and 324 function as drain regions.
The electric field concentrated on the end portions of the semiconductor films 313 and 323 can be relaxed and the hot carrier effect can be prevented. The third semiconductor films 314 and 324 are not necessarily provided, but the provision of the third semiconductor films 314 and 324 can increase the pressure resistance of the TFT and improve the reliability. TFTs 301 and 30
When 2 is n-type, n-type conductivity can be obtained without adding an impurity imparting n-type when the third semiconductor films 314 and 324 are formed. Therefore, when the TFTs 301 and 302 are n-type, it is not always necessary to add n-type impurities to the third semiconductor films 314 and 324.
However, an impurity imparting p-type conductivity is added to the first semiconductor film in which the channel is formed, and the conductivity type is controlled so as to be as close to the I-type as possible.

In addition, wirings 315 and 325 are formed so as to be in contact with the pair of third semiconductor films 314 and 324.

A first passivation film 340 and a second passivation film 341 made of an insulating film are formed so as to cover the TFTs 301 and 302 and the wirings 315 and 325. T
The passivation film covering the FTs 301 and 302 is not limited to two layers, but may be a single layer,
Three or more layers may be used. For example, the first passivation film 340 can be formed using silicon nitride, and the second passivation film 341 can be formed using silicon oxide. By forming the passivation film using silicon nitride or silicon nitride oxide, it is possible to prevent the TFTs 301 and 302 from being deteriorated by the influence of moisture, oxygen, or the like.

One of the wirings 325 is connected to the pixel electrode 370 of the liquid crystal element 303 through the wiring 360. An alignment film 371 is formed so as to be in contact with the pixel electrode 370. On the other hand, the second substrate 3 facing the first substrate 300 with the pixel electrode 370 interposed therebetween.
A counter electrode 373 and an alignment film 342 are sequentially stacked on 72. A liquid crystal 343 is provided between the pixel electrode 370 and the alignment film 371 and the counter electrode 373 and the alignment film 342, and a portion where the pixel electrode 370, the liquid crystal 343, and the counter electrode 373 overlap is a liquid crystal element 303. It corresponds to. Note that the distance (cell gap) between the pixel electrode 370 and the counter electrode 373 is controlled by the spacer 361. In FIG. 3, the spacer 361 is formed by patterning the insulating film, but a spherical spacer prepared separately is used as the alignment film 37.
Alternatively, the cell gap may be controlled by being distributed over 1. 362 corresponds to a sealant, and the liquid crystal 343 can be sealed between the first substrate 300 and the second substrate 372 by the sealant 362.

A polarizing plate may be provided on the surface of the first substrate 300 opposite to the surface on which the TFT 301 and the TFT 302 are formed. In addition, a polarizing plate may be provided on a surface of the second substrate 372 opposite to the surface on which the counter electrode 373 is formed. Note that the liquid crystal display device of the present invention is not limited to the structure shown in FIG.

  Next, the structure of the element substrate used for the liquid crystal display device of the present invention is shown.

FIG. 4 illustrates a mode of an element substrate in which only the signal line driver circuit 6013 is separately formed and connected to the pixel portion 6012 formed over the first substrate 6011. The pixel portion 6012 and the scan line driver circuit 6014 are formed using semi-amorphous TFTs. By forming the signal line driver circuit using a transistor that can obtain higher mobility than a semi-amorphous TFT, the operation of the signal line driver circuit that requires a higher driving frequency than the scanning line driver circuit can be stabilized. Note that the signal line driver circuit 6013 may be a transistor using a single crystal semiconductor, a TFT using a polycrystalline semiconductor, or a transistor using SOI. Pixel unit 601
2, the signal line driver circuit 6013, and the scanning line driver circuit 6014, respectively,
Various signals and the like are supplied via the FPC 6015.

Note that both the signal line driver circuit and the scan line driver circuit may be formed over the same substrate as the pixel portion.

In the case where the driver circuit is separately formed, the substrate on which the driver circuit is formed is not necessarily attached to the substrate on which the pixel portion is formed, and may be attached to, for example, an FPC. In FIG. 5A, only the signal line driver circuit 6023 is formed separately, and the first substrate 6021 is formed.
A mode of an element substrate connected to the pixel portion 6022 and the scan line driver circuit 6024 formed above is shown. The pixel portion 6022 and the scan line driver circuit 6024 are formed using semi-amorphous TFTs. The signal line driver circuit 6023 is connected to the pixel portion 6022 through the FPC 6025. Pixel portion 6022, signal line driver circuit 6023, and scan line driver circuit 6024
In addition, the potential of the power source, various signals, and the like are supplied via the FPC 6025, respectively.

Further, only a part of the signal line driver circuit or a part of the scanning line driver circuit is made semi-amorphous T
An FT may be formed over the same substrate as the pixel portion, and the rest may be separately formed and electrically connected to the pixel portion. FIG. 5B illustrates an analog switch 6033 included in the signal line driver circuit.
a is formed over the same first substrate 6031 as the pixel portion 6032 and the scan line driver circuit 6034;
A mode of an element substrate in which a shift register 6033b included in a signal line driver circuit is separately formed over another substrate is shown. The pixel portion 6032 and the scan line driver circuit 6034 are formed using semi-amorphous TFTs. The shift register 6033b included in the signal line driver circuit includes
The pixel portion 6032 is connected to the pixel portion 6032 through the FPC 6035. The pixel portion 6032, the signal line driver circuit, and the scan line driver circuit 6034 receive power supply potentials, various signals, and the like from the FPC 6
035.

As shown in FIGS. 4 and 5, in the liquid crystal display device of the present invention, part or all of the driver circuit can be formed on the same substrate as the pixel portion using a semi-amorphous TFT.

Note that a method for connecting a separately formed substrate is not particularly limited, and a known COG method, wire bonding method, TAB method, or the like can be used. Further, the connection position is not limited to the position illustrated in FIG. 6 as long as electrical connection is possible. Also,
A controller, a CPU, a memory, and the like may be separately formed and connected.

Note that the signal line driver circuit used in the present invention is not limited to a mode having only a shift register and an analog switch. In addition to the shift register and the analog switch, other circuits such as a buffer, a level shifter, and a source follower may be included. The shift register and the analog switch are not necessarily provided. For example, another circuit that can select a signal line such as a decoder circuit may be used instead of the shift register, or a latch or the like may be used instead of the analog switch. May be.

FIG. 6A is a block diagram of the liquid crystal display device of the present invention. A liquid crystal display device illustrated in FIG. 6A controls a pixel portion 701 including a plurality of pixels each including a liquid crystal element, a scanning line driver circuit 702 that selects each pixel, and input of a video signal to the selected pixel. And a signal line driver circuit 703.

In FIG. 6A, the signal line driver circuit 703 includes a shift register 704 and an analog switch 705. A clock signal (CLK) and a start pulse signal (SP) are input to the shift register 704. Clock signal (CLK) and start pulse signal (
When (SP) is input, a timing signal is generated in the shift register 704 and input to the analog switch 705.

A video signal (video signal) is supplied to the analog switch 705. The analog switch 705 samples the video signal in accordance with the input timing signal and supplies it to the subsequent signal line.

Next, the configuration of the scan line driver circuit 702 is described. The scan line driver circuit 702 includes a shift register 706 and a buffer 707. In some cases, a level shifter may be provided. In the scan line driver circuit 702, a selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP) to the shift register 706. The generated selection signal is buffered and amplified in the buffer 707 and supplied to the corresponding scanning line. The gate of the transistor of the pixel for one line is connected to the scanning line.
Since the transistors of pixels for one line must be turned on all at once, a buffer 707 that can flow a large current is used.

In a full-color liquid crystal display device, when video signals corresponding to R (red), G (green), and B (blue) are sequentially sampled and supplied to corresponding signal lines, a shift register 704 and an analog switch 705 are provided. Are connected to the analog switch 705 and the pixel portion 7.
This corresponds to about 1/3 of the number of terminals for connecting 01 signal lines. Therefore, by forming the analog switch 705 over the same substrate as the pixel portion 701, the number of terminals used for connecting a separately formed substrate can be reduced as compared with the case where the analog switch 705 is formed over a different substrate from the pixel portion 701. Thus, the probability of occurrence of connection failure can be suppressed, and the yield can be increased.

FIG. 6B is a block diagram of a liquid crystal display device of the present invention, which is different from FIG. In FIG. 6B, the signal line driver circuit 713 includes a shift register 714, a latch A 715, a latch B 716, and a D / A conversion circuit (DAC) 717. The scan line driver circuit 712 has the same structure as that in FIG.

A clock signal (CLK) and a start pulse signal (SP) are input to the shift register 714. When the clock signal (CLK) and the start pulse signal (SP) are input, a timing signal is generated in the shift register 714 and sequentially input to the first-stage latch A715. When a timing signal is input to the latch A715, video signals are sequentially written and held in the latch A715 in synchronization with the timing signal. Note that FIG.
), It is assumed that video signals are sequentially written in the latch A 715, but the present invention is not limited to this configuration. A plurality of stages of latches A715 may be divided into several groups, and so-called divided driving may be performed in which video signals are input in parallel for each group. Note that the number of groups at this time is called the number of divisions. For example, when the latches are divided into groups for every four stages, it is said that the driving is divided into four.

The time until video signal writing to all the latches of the latch A 715 is completed is called a line period. Actually, the line period may include a period in which a horizontal blanking period is added to the line period.

When one line period ends, the latch signal (Latch Si) is sent to the second-stage latch B716.
gnal) is supplied, and the video signal held in the latch A 715 is simultaneously written and held in the latch B 716 in synchronization with the latch signal. Latch video signal B716
The next video signal is sequentially written to the latch A 715 that has been transmitted to the second time in synchronization with the timing signal from the shift register 714 again. During the second line period, the video signal written and held in the latch B 716 is input to the DAC 717.

The DAC 717 converts the input video signal from digital to analog and supplies it to the corresponding signal line.

Note that the structures illustrated in FIGS. 6A and 6B are merely examples of the liquid crystal display device of the present invention, and the structures of the signal line driver circuit and the scan line driver circuit are not limited thereto. .

  Next, a specific manufacturing method of the liquid crystal display device of the present invention will be described.

The first substrate 10 can be made of a plastic material other than glass or quartz.
Further, an insulating film formed on a metal material such as stainless steel or aluminum may be used. A conductive film 11 for forming a gate electrode and a gate wiring (scanning line) is formed on the first substrate 10. For the first conductive film 11, a metal material such as chromium, molybdenum, titanium, tantalum, tungsten, aluminum, or an alloy material thereof is used. The conductive film 11 can be formed by a sputtering method or a vacuum evaporation method. (Fig. 7 (A))

The conductive film 11 is etched to form gate electrodes 12 and 13. Since the first semiconductor film and the wiring layer are formed over the gate electrode, it is desirable to process the end portion of the gate electrode into a tapered shape. In the case where the conductive film 11 is formed using a material containing aluminum as a main component, it is preferable to insulate the surface by performing anodization after etching. Although not shown, a wiring connected to the gate electrode can be formed at the same time in this step. (Fig. 7 (
B))

Next, as shown in FIG. 7C, the first insulating film 14 and the second insulating film 15 are formed of the gate electrode 12.
, 13 can function as a gate insulating film. in this case,
It is preferable to form a silicon oxide film as the first insulating film 14 and a silicon nitride film as the second insulating film 15. These insulating films can be formed by a glow discharge decomposition method or a sputtering method. In particular, in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film.

Then, the first semiconductor film 16 is formed on the first insulating film 14 and the second insulating film 15. The first semiconductor film 16 is formed of a film including a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). This semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline material having a short-range order and lattice strain, and having a grain size of 0.5 to 20 nm. It can be dispersed in a semiconductor. Further, hydrogen or halogen is contained at least 1 atomic% or more as a neutralizing agent for dangling bonds. Here, for convenience, such a semiconductor is referred to as a semi-amorphous semiconductor (SAS). Furthermore, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and good SA is obtained.
S is obtained. Such a SAS semiconductor is described in, for example, US Pat. No. 4,409,
No. 134.

This SAS can be obtained by glow discharge decomposition of a silicide gas. A typical silicide gas is SiH ₄ , and other Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl _{3 are also used.}
SiCl ₄ , SiF ₄ or the like can be used. The formation of the SAS can be facilitated by diluting the silicide gas with one or plural kinds of rare gas elements selected from hydrogen, hydrogen and helium, argon, krypton, and neon. Dilution rate is 10 to 100
It is preferable to dilute the silicide gas in a range of 0 times. Of course, the reaction of the coating by glow discharge decomposition is performed under reduced pressure, but the pressure may be in the range of about 0.1 Pa to 133 Pa. The power for forming the glow discharge is 1 MHz to 120 MHz, preferably 13 MHz to
What is necessary is just to supply high frequency electric power of 60 MHz. The substrate heating temperature is preferably 300 ° C. or less.
A substrate heating temperature of 00-200 degrees is recommended.

Further, a carbide gas such as CH ₄ and C ₂ H ₆ and a germanium gas such as GeH ₄ and GeF ₄ are mixed in the silicide gas, and the energy bandwidth is 1.5 to 2.4 eV, or 0.
. You may adjust to 9-1.1 eV.

In addition, since SAS exhibits weak n-type conductivity when an impurity element for the purpose of valence electron control is not intentionally added, the first semiconductor film provided with a TFT channel formation region is The threshold value can be controlled by adding an impurity element imparting p-type simultaneously with or after the film formation. The impurity element imparting p-type is typically boron, and an impurity gas such as B ₂ H ₆ or BF ₃ may be mixed into the silicide gas at a rate of 1 ppm to 1000 ppm. The concentration of boron is, for example, 1 × 10 ^{14 to} 6 × 10 ¹⁶ a.
Toms / cm ³ is preferable.

Next, as shown in FIG. 8A, a second semiconductor film 17 is formed. The second semiconductor film 17 is formed without intentionally adding an impurity element for the purpose of valence electron control.
Like the semiconductor film 16, it is preferably formed of SAS. The second semiconductor film 17 is
A third semiconductor film 18 having one conductivity type for forming a source and a drain and a first semiconductor film 1
By forming between the two, it has a buffer layer (buffer layer) function. Therefore, weak n
When the third semiconductor film 18 having the same conductivity type and the one conductivity type is formed on the first semiconductor film 16 having the electrical conductivity of the mold, it is not always necessary. For the purpose of threshold control, when an impurity element imparting p-type is added, the second semiconductor film 17 has an effect of changing the impurity concentration stepwise, and in order to improve the junction formation. This is a preferred form. That is, the formed TFT can have a function as a low concentration impurity region (LDD region) formed between the channel formation region and the source or drain region.

The third semiconductor film 18 having one conductivity type may be formed by adding phosphorus as a typical impurity element when an n-channel TFT is formed, and by adding an impurity gas such as PH ₃ to a silicide gas. good. The third semiconductor film 18 having one conductivity type is formed of a semiconductor such as SAS, an amorphous semiconductor, or a microcrystalline semiconductor except that valence electron control is performed.

As described above, the first insulating film 14 to the third semiconductor film 18 having one conductivity type can be continuously formed without being exposed to the atmosphere. In other words, each stacked interface can be formed without being contaminated by atmospheric components or contaminating impurity elements floating in the atmosphere, so that variations in TFT characteristics can be reduced.

Next, a mask 19 is formed using a photoresist, and the first semiconductor film 16, the second semiconductor film 17, and the third semiconductor film 18 having one conductivity type are etched and separated into island shapes.
(Fig. 8 (B))

Thereafter, a second conductive film 20 for forming wirings connected to the source and drain is formed. The second conductive film 20 is formed of aluminum or a conductive material containing aluminum as a main component, but the layer on the side in contact with the semiconductor film may be formed of titanium, tantalum, molybdenum, or a nitride of these elements. good. In order to improve heat resistance, aluminum such as titanium, silicon, scandium, neodymium, or copper may be added to aluminum in an amount of 0.5 to 5 atomic% (FIG. 8C).

Next, a mask 21 is formed. The mask 21 is a mask formed in order to form wirings connected to the source and drain, and at the same time, the second semiconductor film 17 and the third semiconductor film 18 having one conductivity type are removed to form a channel formation region. It is used together as an etching mask. Etching of aluminum or a conductive film containing this as a main component may be performed using a chloride gas such as BCl ₃ or Cl ₂ . Wirings 23 to 26 are formed by this etching process. For etching to form a channel formation region, SF is used.
_6. Etching is performed using a fluoride gas such as NF ₃ , CF _4, etc., but in this case, the etching selection ratio with the first semiconductor film 16 serving as the base cannot be taken, so that the processing time is appropriately adjusted. Will be done. As described above, a channel-etch TFT structure can be formed. (Fig. 9 (A))

Next, a third insulating film 27 for the purpose of protecting the channel formation region is formed using a silicon nitride film. This silicon nitride film can be formed by sputtering or glow discharge decomposition, but it is intended to prevent the entry of contaminants such as organic substances, metal substances, and water vapor floating in the atmosphere, and it must be a dense film. Is required. By using a silicon nitride film for the third insulating film 27, the oxygen concentration in the first semiconductor film 16 is 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁹ at.
oms / cm ³ or less. For this purpose, using silicon as a target,
A silicon nitride film that has been subjected to high-frequency sputtering with a sputtering gas in which a rare gas element such as nitrogen and argon is mixed. By including the rare gas element in the film, densification is promoted. Also, in the glow discharge decomposition method, the silicide gas is 100 times as much as rare gas such as argon.
A silicon nitride film formed by diluting 500 times is preferable because a dense film can be formed even at a low temperature of 100 degrees or less. Further, if necessary, the fourth insulating film 28 may be laminated with a silicon oxide film. The third insulating film 27 and the fourth insulating film 28 correspond to a passivation film.

Next, a planarizing film 29 is formed on the third insulating film 27 and / or the fourth insulating film 28.
The planarizing film 29 is preferably formed of an insulating film including Si—O bonds and Si—CHx crystal hands formed using an organic resin such as acrylic, polyimide, or polyamide, or a siloxane-based material as a starting material. Next, contact holes are formed in the third insulating film 27, the fourth insulating film 28, and the planarizing film 29, and wirings 30 to 33 connected to the wirings 23 to 26 on the planarizing film 29.
Form. (Fig. 9 (B))

The wirings 30 to 33 can be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy or compound containing the element as a main component. Alternatively, these conductive films may be stacked. For example, the first layer is Ta, the second layer is W, the first layer is TaN, and the second layer is A.
l A combination in which the first layer is TaN, the second layer is Cu, the first layer is Ti, the second layer is Al, and the third layer is Ti is also conceivable. Further, an AgPdCu alloy may be used for either the first layer or the second layer. A three-layer structure in which W, an alloy of Al and Si (Al-Si), and TiN are sequentially stacked may be employed. Instead of W, tungsten nitride may be used, or an alloy of Al and Si (Al-
An alloy film of Al and Ti (Al-Ti) may be used instead of Si), or T instead of TiN.
i may be used.

Next, as shown in FIG. 10A, the pixel electrode 3 on the planarizing film 29 is in contact with the wiring 33.
5 is formed. Although FIG. 10 shows an example in which the pixel electrode 35 is formed of a transparent conductive film and a transmissive liquid crystal display device is manufactured, the liquid crystal display device of the present invention is not limited to this structure. By forming the pixel electrode using a conductive film that easily reflects light, a reflective liquid crystal display device can be formed. In this case, a part of the wiring 33 can be used as a pixel electrode.

The channel-etched TFT formed as described above can obtain a field effect mobility of ² to 10 cm ² / V · sec by forming a channel formation region with SAS. Therefore, the TFT can be used as a pixel switching element and an element for forming a driving circuit on the scanning line (gate line) side.

The pixel switching element and the scanning line side drive circuit are the same TFT, and the element substrate is a gate electrode forming mask, a semiconductor region forming mask, a wiring forming mask, a contact hole forming mask, and a pixel electrode forming mask. A total of five masks can be formed.

Next, a spacer 36 is formed of an insulating film on the wiring 32 or the wiring 33. Note that FIG.
A) shows an example in which the spacer 36 is formed on the wiring 32 using silicon oxide. Either the pixel electrode 35 or the spacer 36 may be formed first.

Then, an alignment film 37 is formed so as to cover the wirings 30 to 33, the spacer 36, and the pixel electrode 35, and a rubbing process is performed.

Next, as shown in FIG. 10B, a sealing material 40 for sealing the liquid crystal is formed. On the other hand, a second substrate 42 on which a counter electrode 43 using a transparent conductive film and an alignment film 44 subjected to rubbing treatment are prepared. Then, the liquid crystal 41 is dropped on a region surrounded by the sealing material 40, and a separately prepared second substrate 42 is attached using the sealing material 40 so that the counter electrode 43 and the pixel electrode 35 face each other. Match. The sealing material 40 may be mixed with a filler.

Note that a color filter, a shielding film (black matrix) for preventing disclination, or the like may be formed. Further, the polarizing plate 51 is bonded to the surface opposite to the surface of the first substrate 10 on which the TFT is formed, and the surface opposite to the surface on which the counter electrode 43 of the second substrate 42 is formed. The polarizing plate 52 is pasted together.

The transparent conductive film used for the pixel electrode 35 or the counter electrode 43 is made of ITO, IZO, ITS.
In addition to O, a material in which indium oxide is mixed with 2 to 20% zinc oxide (ZnO) can be used. A liquid crystal element 55 is formed by overlapping the pixel electrode 35, the liquid crystal 41, and the counter electrode 43.

The liquid crystal injection described above uses a dispenser type (dropping type), but the present invention is not limited to this. A dip type (pumping type) in which liquid crystal is injected using a capillary phenomenon after the second substrate is bonded may be used.

7 to 10 show the manufacturing method of the TFT having the structure shown in FIG. 1, the TFT having the structure shown in FIG. 3 can be similarly manufactured. However, in the case of the TFT shown in FIG. 3, channel protective films 330 and 331 are formed on the first semiconductor films 312 and 322 made of SAS so as to overlap with the gate electrodes 310 and 320, respectively. 7 to 1
It is different from zero.

In this embodiment, one mode of a semi-amorphous TFT included in the liquid crystal display device of the present invention will be described.

FIG. 11A shows a top view of the semi-amorphous TFT of this example, and FIG. 11B shows a cross-sectional view taken along line AA ′ of FIG. 11A. A part 1301 is a gate wiring functioning as a gate electrode, and overlaps a first semiconductor film 1303 formed of a semi-amorphous semiconductor with a gate insulating film 1302 interposed therebetween. In addition, the first semiconductor film 1303
Second semiconductor films 1304a and 1304b functioning as LDD regions are formed so as to be in contact with each other, and third semiconductor films 1305a and 1305b having one conductivity type are provided so as to be in contact with the second semiconductor films 1304a and 1304b. Is formed. Reference numerals 1306 and 1307 correspond to wirings in contact with the third semiconductor films 1305a and 1305b, respectively.

In the semi-amorphous TFT shown in FIG. 11, the channel length can be kept constant by keeping the distance between the third semiconductor film 1305a and the third semiconductor film 1305b constant. Further, by laying out the end portion of the third semiconductor film 1305b so as to be surrounded by the third semiconductor film 1305a, concentration of an electric field on the drain region side of the channel formation region can be reduced. Furthermore, since the ratio of the channel width to the channel length can be increased, the on-state current can be increased.

In this embodiment, an example of a shift register using semi-amorphous TFTs having the same polarity will be described. FIG. 12A shows the structure of the shift register of this embodiment. The shift register illustrated in FIG. 12A includes a first clock signal CLK and a second clock signal C.
It operates using LKb and start pulse signal SP. 1401 is a pulse output circuit,
A specific structure thereof is shown in FIG.

The pulse output circuit 1401 includes TFTs 801 to 806 and a capacitor 807. TF
In T801, the gate is connected to the node 2, the source is connected to the gate of the TFT 805, and the potential Vdd is applied to the drain. The TFT 802 has a gate connected to the gate of the TFT 806, a drain connected to the gate of the TFT 805, and a potential Vss applied to the source. The TFT 803 has a gate connected to the node 3, a source connected to the gate of the TFT 806, and a potential Vdd applied to the drain. The gate of the TFT 804 is node 2
Further, the drain is connected to the gate of the TFT 805, and the potential Vss is applied to the source. The TFT 805 has a gate connected to one electrode of the capacitor 807 and a drain connected to the node 1.
Further, the source is connected to the other electrode of the capacitor 807 and the node 4. TFT8
In 06, the gate is connected to one electrode of the capacitor 807, the drain is connected to the node 4, and the potential Vss is applied to the source.

Next, operation of the pulse output circuit 1401 illustrated in FIG. However,
CLK, CLKb, and SP are assumed to be Vdd when H level, Vss when L level, and Vss = 0 for simplicity of explanation.

When SP becomes H level, the TFT 801 is turned on, so that the gate potential of the TFT 805 rises. Finally, the gate potential of the TFT 805 is Vdd−Vth (
When Vth becomes the threshold value of the TFTs 801 to 806), the TFT 801 is turned off and enters a floating state. On the other hand, since the TFT 804 is turned on when SP becomes H level,
The potentials of the gates of the TFTs 802 and 806 drop and finally become Vss.
, 806 is turned off. At this time, the gate of the TFT 803 is at the L level and is turned off.

Next, SP becomes L level, the TFTs 801 and 804 are turned off, and the gate potential of the TFT 805 is held at Vdd−Vth. Here, if the gate-source voltage of the TFT 805 exceeds the threshold value Vth, the TFT 805 is turned on.

Next, when the CLK applied to the node 1 changes from the L level to the H level, the TFT 8
Since 05 is on, the potential of the node 4, that is, the source of the TFT 805 starts to rise. Since capacitive coupling due to the capacitive element 807 exists between the gate and the source of the TFT 805, the potential of the gate of the TFT 805 in a floating state rises again as the potential of the node 4 rises. Eventually, the potential of the gate of the TFT 805 becomes higher than Vdd + Vth, and the potential of the node 4 becomes equal to Vdd. Then, the above-described operation is similarly performed in the pulse output circuit 1401 in the second and subsequent stages, and pulses are output in order.

In this embodiment, the appearance of a panel corresponding to one mode of the liquid crystal display device of the present invention is shown in FIG.
3 will be described. FIG. 13 shows a semi-amorphous T formed on the first substrate 4001.
FIG. 13B is a top view of the panel in which the FT 4010 and the liquid crystal element 4011 are sealed with a sealant 4005 between the second substrate 4006 and FIG. 13B is a cross-sectional view taken along line AA ′ of FIG. It corresponds to the figure.

A sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 include the first substrate 4001, the sealant 4005, and the second substrate 400.
6 and the liquid crystal 4007. In addition, a signal line driver circuit 4003 formed using a polycrystalline semiconductor film is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. Note that in this embodiment, an example in which a signal line driver circuit including a TFT using a polycrystalline semiconductor film is attached to the first substrate 4001 is described; however, the signal line driver circuit is formed using a transistor using a single crystal semiconductor. However, they may be bonded together. In FIG. 13, the signal line driver circuit 4003 includes
A TFT 4009 formed using a polycrystalline semiconductor film is illustrated.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of TFTs. In FIG. 13B, the TFT 401 included in the pixel portion 4002 is provided.
0 is illustrated. The TFT 4010 corresponds to a TFT using a semi-amorphous semiconductor.

Reference numeral 4011 corresponds to a liquid crystal element, and the pixel electrode 4030 included in the liquid crystal element 4011 includes T
The FT 4010 is electrically connected to the wiring 4040 and the wiring 4041. The counter electrode 4031 of the liquid crystal element 4011 is formed over the second substrate 4006. A portion where the pixel electrode 4030, the counter electrode 4031, and the liquid crystal 4007 overlap is a liquid crystal element 4011.
It corresponds to.

Reference numeral 4035 denotes a spherical spacer, which is provided to control the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031. Note that a spacer obtained by patterning the insulating film may be used.

Further, a variety of signals and potentials are supplied to the signal line driver circuit 4003 which is formed separately, the scan line driver circuit 4004, or the pixel portion 4002, although they are not shown in the cross-sectional view in FIG. It is supplied from the connection terminal 4016 via 4015.

In this embodiment, the connection terminal 4016 is formed using the same conductive film as the pixel electrode 4030 included in the liquid crystal element 4011. In addition, the lead wiring 4014 is formed using the same conductive film as the wiring 4041. The lead wiring 4015 is formed using the same conductive film as the wiring 4040.

The connection terminal 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

Note that as the first substrate 4001 and the second substrate 4006, glass, ceramics, or plastic can be used. As plastic, FRP (Fiberglass
s-Reinforced Plastics) board, PVF (polyvinyl fluoride)
A film, mylar film, polyester film or acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

However, the second substrate must be transparent to the substrate located in the direction in which light is extracted from the liquid crystal element 4011. In that case, a light-transmitting material such as a glass plate, a plastic, a polyester film, or an acrylic film is used.

Although not shown, the liquid crystal display device described in this embodiment includes an alignment film and a polarizing plate, and may further include a color filter and a shielding film.

FIG. 13 illustrates an example in which the signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

  This embodiment can be implemented in combination with the structure described in other embodiments.

As an electronic device using the liquid crystal display device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device , A portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.), an image playback device (specifically, DVD: Digital Ver) equipped with a recording medium
apparatus including a display capable of reproducing a recording medium such as a satellite disc) and displaying the image. In the present invention, since it is not necessary to provide a crystallization step after the formation of the semiconductor film, it is relatively easy to increase the size of the panel. Therefore, the present invention is very useful for an electronic device using a large panel of 10 to 50 inches. It is. Specific examples of these electronic devices are shown in FIGS.

FIG. 14A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. By using the liquid crystal display device of the present invention for the display portion 2003, the display device of the present invention is completed. Since the liquid crystal display device is a self-luminous type, a backlight is not required and a display portion thinner than a liquid crystal display can be obtained.
The liquid crystal element display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 14B illustrates a laptop personal computer, which includes a main body 2201 and a housing 2202.
A display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The notebook personal computer of the present invention is completed by using the liquid crystal display device of the present invention for the display portion 2203.

FIG. 14C shows a portable image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
A main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, a recording medium (DVD or the like) reading portion 2405, operation keys 2406, a speaker portion 2407, and the like.
A display portion A2403 mainly displays image information, and a display portion B2404 mainly displays character information. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
By using the liquid crystal display device of the present invention for the display portions A2403 and B2404, the image reproducing device of the present invention is completed.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. Further, the electronic apparatus of this embodiment may use the liquid crystal display device having any configuration shown in the first to third embodiments.

100 Substrate 101 TFT
102 TFT
103 Liquid crystal element 110 Gate electrode 111 Gate insulating film 112 Semiconductor film 113 Semiconductor film 114 Semiconductor film 115 Wiring 120 Gate electrode 122 Semiconductor film 123 Semiconductor film 124 Semiconductor film 125 Wiring 130 Pixel electrode 131 Alignment film 140 Passivation film 141 Passivation film 142 Alignment film 143 Liquid crystal 150 Polarizing plate 151 Polarizing plate 160 Wiring 161 Spacer 162 Sealing material 170 Substrate 171 Counter electrode 201 Switching TFT
202 Liquid crystal element 203 Capacitor element 204 Pixel electrode 300 Substrate 301 TFT
302 TFT
303 Liquid crystal element 310 Gate electrode 311 Gate insulating film 312 Semiconductor film 313 Semiconductor film 314 Semiconductor film 315 Wiring 325 Wiring 330 Channel protection film 340 Passivation film 341 Passivation film 342 Alignment film 343 Liquid crystal 360 Wiring 361 Spacer 362 Sealing material 370 Pixel electrode 371 Alignment Film 372 Substrate 373 Counter electrode

Claims (1)

Having a pixel portion and a scanning line driving circuit on the same substrate;
The pixel portion is provided with a liquid crystal element and a TFT for controlling a voltage applied to the liquid crystal element.
The TFT included in the scanning line driving circuit and the TFT for controlling the voltage applied to the liquid crystal element are formed on a gate electrode, a gate insulating film formed on the gate electrode, and the gate insulating film. A first semiconductor film, a buffer layer formed on the first semiconductor film and made of an amorphous semiconductor to which an impurity imparting one conductivity type is not added, and a pair formed on the buffer layer A second semiconductor film, and
An impurity imparting one conductivity type is added to the pair of second semiconductor films,
The first semiconductor film is formed of a semiconductor including a microcrystalline semiconductor film including crystal grains in an amorphous semiconductor;
The interface between the gate insulating film and the first semiconductor film, the interface between the first semiconductor film and the buffer layer, and the interface between the buffer layer and the second semiconductor film are in atmospheric components or in the atmosphere. A liquid crystal display device characterized by being not contaminated by floating impurity elements.

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