JP2000259111A - Semiconductor display device and its driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the semiconductor display device which has low power consumption and small electromagnetic noise and small necessary radiation. SOLUTION: In a peripheral driving circuit, the clock signal whose level is raised by a level shifter circuit is inputted to a shift register circuit. The timing signal from the shift register circuit is inputted to the level shifter circuit and its voltage is raised in two stages. Consequently, the power consumption of the driving circuit is reduced, electromagnetic noise is suppressed, and unnecessary radiation is made small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor display device. Among them, pixel TFTs arranged in a matrix
The present invention relates to a semiconductor display device that displays an image by driving the same and a driving circuit of the semiconductor display device. Also,
The present invention relates to electronic devices using these semiconductor display devices.

[0002]

2. Description of the Related Art Recently, a technique for manufacturing a semiconductor display device in which a semiconductor thin film is formed on an inexpensive glass substrate, for example, a thin film transistor (TFT) has been rapidly developed.
The reason is that the demand for the active matrix type liquid crystal display device has been increased.

In an active matrix type liquid crystal display device, TFTs are arranged in tens to millions of pixel regions arranged in a matrix. The charge flowing into and out of each pixel electrode is controlled by the switching function of the TFT arranged in the pixel region.

FIG. 18 shows a configuration of a conventional active matrix type liquid crystal display device. Source signal line side drive circuit 18
01 and the gate signal line side drive circuit 1802 are generally collectively referred to as drive circuits. In recent years, this drive circuit has been integrally formed on the same substrate as a pixel matrix portion composed of an active matrix circuit.

[0005] In the pixel matrix portion 1808, a source signal line 1803 connected to the source signal line side driving circuit 1801 and a gate signal line 1804 connected to the gate signal line side driving circuit 1802 intersect. In a region surrounded by the source signal line 1803 and the gate signal line 1804, a pixel thin film transistor (pixel TFT) 1805 is provided.
And a liquid crystal cell 1 having a liquid crystal interposed between a counter electrode and a pixel electrode.
806 and a storage capacitor 1807 are provided.

[0006] An image signal input to the source signal line 1803 is selected by the pixel TFT 1805 and written to a predetermined pixel electrode.

[0007] An image signal sampled by the timing signal output from the source signal line side driving circuit 1801 is supplied to the source signal line 1803.

The pixel TFT 1805 operates according to a selection signal input from the gate signal line side driving circuit 1802 via the gate signal line 1804.

[0009]

[Prior Art A] FIG.
FIG. 1A is a block diagram illustrating an example of a conventional source signal line side driving circuit 1801.

An input signal input from outside the source signal line side driving circuit, in this case, a clock signal (CLK) (for example, 3 V) is input to the source signal line side driving circuit. The input clock signal is output by the level shifter circuit.
The voltage amplitude level is increased (for example, 3V → 16
V).

Here, in this specification, the voltage amplitude level means an absolute value of a difference (potential difference) between the highest potential and the lowest potential of a signal, and a higher (increased) voltage amplitude level means a potential difference. Means that the voltage difference level becomes large, and that the voltage amplitude level becomes low means that the potential difference becomes small.

Then, the clock signal whose voltage amplitude level has been raised is input to the shift register circuit. The shift register circuit operates by the input clock signal and the start pulse signal input to the shift register circuit at the same time, and sequentially generates a timing signal for sampling the image signal. This timing signal is input to the sampling circuit, and the sampling circuit performs an operation of sampling the image signal based on the input timing signal.

FIG. 21 shows an example of a specific circuit configuration of FIG. The level shifter circuit 11, shift register circuit 12, sampling circuit 13, and image signal line 14 are arranged as shown in the figure.

The clock signal (CLK) and the inverted clock signal (CLKb) are input to the level shifter circuit 11, and the start pulse signal (SP) and the drive direction switching signal (SL / R) are shifted from the wiring shown in FIG. Input to the register circuit.

A clock signal (CLK) (for example, 3 V) is supplied from the outside of the source signal line side driving circuit to the level shifter circuit 1.
1 is input. The voltage amplitude level of the clock signal needs to be a voltage amplitude level at which the level shifter circuit can operate.

Unwanted radiation is a problem in setting by a clock signal. Unwanted radiation is due to the generation of high frequency components in a digital circuit using a very sharp rising rectangular wave train. Unwanted radiation increases as the frequency of the signal increases, but can be suppressed to some extent by lowering the voltage amplitude level of the signal.

Unwanted radiation is generated by the International Commission on Radio Interference, commonly known as CISPR (International Speci
al Committee on Radio Int
, it is necessary to keep it smaller than the range that conforms to the standard defined in the above. Also, CIS
In addition to PR, within the range that conforms to domestic and international standards such as the US Federal Commission (FCCI), the Voluntary Control Council for Interference from Information Technology Equipment (VCCI), and the West German Electrical Engineering Association Standard (VDE). It is necessary to be. For example, FCCI
According to the standard set forth in the above, in the case of industrial equipment, the allowable value is 1000 μV when the frequency is 0.45 to 1.6 MHz, and 3000 μV when the frequency is 1.6 to 30 MHz. The voltage amplitude level of the clock signal input from the outside of the source signal line side driving circuit is set to
It must be lowered to a level that does not cause a problem so that it conforms to standards set in Japan and abroad.

The voltage amplitude level of the clock signal input to the level shifter circuit is increased. FIG. 20 shows an equivalent circuit diagram of the level shifter circuit 11. Vin means that a signal is input, and Vinb means that an inverted signal of Vin is input. Vddh indicates the application of a positive voltage, and Vss indicates the application of a negative voltage.
The level shifter circuit 11 is designed so that a signal obtained by increasing the voltage of the signal input to Vin and inverting the signal is output from Voutb. That is, when Hi is input to Vin, a signal corresponding to Vss is output from Voutb, and when Lo is input, a signal corresponding to Vddh is output from Vout.

The voltage amplitude level of the clock signal is shown in FIG.
By using the level shifter as shown in (1), the voltage amplitude level (saturation voltage of the liquid crystal) at which the liquid crystal is driven to a saturated state can be raised to a voltage amplitude level having a certain margin voltage. Further, in the present application, the saturation voltage indicates the saturation voltage of the liquid crystal. The state in which the liquid crystal is driven to a saturated state refers to a state (saturated state) in which even if the voltage applied to the liquid crystal is further increased, the electro-optical characteristics due to the change in the alignment of the liquid crystal do not change.

A signal for sampling the image signal input to the sampling circuit is a timing signal.
TFT of which the voltage of the timing signal input to the sampling circuit constitutes the analog switch of the sampling circuit
Is applied to the gate electrode. As a result, a channel is formed in the TFT constituting the analog switch, and a current flows from the source to the drain. Therefore, the image signal is sampled and supplied to the source of the pixel TFT via the source signal line.

For example, a TN (Twisted) driven by 5 V
In the case of a nematic liquid crystal, 5 V is a saturation voltage.
Since the liquid crystal is driven by AC, as a result, -5V to + 5V,
That is, a voltage amplitude level of 10 V is applied to the liquid crystal.
When driving the liquid crystal in a saturated state, it is necessary to sample a 10 V image signal (in this case, the saturation voltage is equal to the image signal) and supply it to the source of the pixel TFT.

In order to sample this image signal, a certain margin voltage (for example, ± 3
It is required to apply a timing signal of the voltage amplitude level provided with V) to the gate of the TFT constituting the analog switch. That is, a voltage of -5V to + 5V, that is, 1
In order to sample an image signal having a voltage amplitude level of 0 V, the voltage amplitude level of the timing signal is -8 to +8 V
, That is, a voltage amplitude level of 16V.

This margin voltage is for surely supplying the image signal of the saturation voltage to the source of the pixel TFT. Even if an attempt is made to sample an image signal having a voltage amplitude level of ± 5 V with a timing signal having the same voltage amplitude level of ± 5 V without providing a margin, the problem that the n-channel TFT forming the analog switch does not operate and is not sampled. is there. This is because the difference between the voltage amplitude level (5V) of the image signal applied to the source of the n-channel TFT constituting the analog switch and the voltage amplitude level of the timing signal (5V) applied to the gate electrode is 0V.
This is because the n-channel TFT does not operate. Also, the p-channel TFT does not operate for the same reason. Therefore, in order to drive the liquid crystal to a saturated state,
It is necessary to provide a margin voltage for the timing signal. It is necessary that the magnitude of the margin voltage is large enough that the image signal of the saturation voltage is sampled by the timing signal and supplied to the source signal line without fail.

In recent years, a liquid crystal display device having a large screen and high resolution has been developed. Assuming that display is performed at the same frame rate, it is necessary to operate the shift register circuit at higher speed as the number of pixels of the liquid crystal display device increases, and it is required to increase the drive frequency of the shift register.

The operating speed of the shift register circuit is proportional to the mobility of the TFT of the shift register circuit and the voltage amplitude level of the clock signal applied to the source, and is inversely proportional to the square of the channel length. The operating speed of the shift register circuit is inversely proportional to the square of the channel length because the shorter the channel length of the TFT, the smaller the on-resistance and the smaller the gate capacitance.

In order to operate the shift register circuit at higher speed, the mobility of the TFT has a limit.
It is required to increase the power supply voltage of the shift register circuit or shorten the channel length.

However, when the power supply voltage of the shift register circuit is made higher and the channel length is made shorter, the TFT easily breaks down due to punch-through due to the short channel effect and hot electrons. Therefore, it is necessary to reduce the power supply voltage of the shift register circuit to such an extent that the TFT does not fail.

Further, the voltage amplitude level of the clock signal applied to the source is reduced to such an extent that the TFT of the shift register circuit does not fail due to punch-through due to the short channel effect or hot electrons, so as to shorten the channel length of the TFT. Then, the TFT cannot be manufactured because there is a design limit to the short channel length of the TFT.
Therefore, the shift register circuit cannot operate at a high speed above a certain speed. Therefore, in order to operate the shift register circuit at a higher speed, the channel length of the TFT is increased to a range where the TFT can be created, and the voltage amplitude level of the clock signal applied to the source is increased so that the TFT having the channel length that can be created operates. Needed to be high enough.

In other words, in order to operate the shift register circuit at a higher speed, the power supply voltage of the shift register circuit can be reduced to such a level that the TFT of the shift register circuit does not fail due to punch-through due to a short channel effect or hot electrons. It has to be high enough to operate a TFT having a long channel length.

In the conventional circuit configuration shown in FIG.
Since there is no level shifter circuit between the shift register circuit and the sampling circuit, clock signals (CLK, CLKb) input to the TFT of the shift register circuit have the same voltage amplitude level as the timing signal input to the sampling circuit. . That is, the voltage amplitude level of the clock signal input to the shift register circuit cannot be reduced to such an extent that the TFTs constituting the shift register circuit do not fail due to punch-through due to short channel effect or hot electrons. Therefore, the TFT of the shift register circuit is easily broken.

The above problem can be solved by using a liquid crystal display device composed of an LCD material that can be driven at a relatively low voltage of less than 3V. However, the liquid crystal used has a low voltage holding ratio, and a current leaks when a voltage is applied to the liquid crystal. An LCD material that can be driven at a voltage of 3 V or more has a relatively high voltage holding ratio of 95% or more, and a liquid crystal display device using an LCD material driven at a voltage of 3 V or more has high reliability.

[Prior Art B] FIG. 19B is a block diagram showing another example of a conventional source signal line side driving circuit 1801.

A clock signal (CLK) (for example, 10 V) input from outside the source signal line side driving circuit is directly input to the shift register circuit. The shift register circuit operates by the input clock signal and the start pulse signal input to the shift register circuit at the same time, and sequentially generates a timing signal for sampling an image.

The generated timing signal is input to the level shifter circuit to increase the voltage amplitude level. The timing signal whose voltage amplitude level has been increased is input to the sampling circuit, and the sampling circuit performs an operation of sampling the image signal based on the input timing signal.

FIG. 22 shows an example of a specific circuit configuration of FIG. 19B. A shift register circuit 21, a level shifter circuit 22, a sampling circuit 23, and an image signal line 24 are arranged as shown in the figure.

The clock signal (CLK), the inverted clock signal (CLKb), the start pulse signal (SP), and the drive direction switching signal (SL / R) are input to the shift register circuit from the wiring shown in the figure.

A clock signal (CLK) (for example, 10 V) is input to the shift register circuit 21 from outside the source signal line side driving circuit. The voltage amplitude level of the clock signal input at this time is a voltage amplitude level high enough to drive the shift register circuit 21.

The shift register circuit 21 operates according to the input clock signal and the start pulse signal input to the shift register circuit at the same time, and sequentially generates a timing signal for sampling an image. The generated timing signal is input to the level shifter circuit 22.

As described above, in order to drive the liquid crystal in a saturated state, it is necessary to input a timing signal of a voltage amplitude level provided with a certain margin voltage to the sampling voltage to the sampling circuit 23. . Therefore, when the voltage amplitude level of the timing signal input to the sampling circuit 23 is less than the saturation voltage and the voltage amplitude level provided with a certain margin voltage, it is necessary to increase the voltage amplitude level of the timing signal. The timing signal input to the level shifter circuit 22 is output after being raised to a voltage amplitude level (for example, 16 V) provided with a certain margin voltage in the saturation voltage. The output timing signal is input to the sampling circuit 23.

In order to operate the shift register circuit at high speed, the power supply voltage of the shift register circuit is so low that the TFT of the shift register circuit 21 does not fail due to punch-through due to a short channel effect or hot electrons, and the channel that can be manufactured is manufactured. It had to be high enough to operate long TFTs. However, in the circuit configuration of the prior art B, when the voltage amplitude level of the clock signal input from the outside of the source signal line side driving circuit is increased to a voltage amplitude level at which the shift register circuit can operate at high speed, the source signal It is difficult to suppress the voltage amplitude level of the clock signal input from the outside of the line-side drive circuit to such a level that unnecessary radiation is not a problem. Further, the higher the voltage amplitude level of the clock signal input from the outside of the source signal line side driving circuit, the higher the power consumption, which is not preferable.

The above problem can be solved by using a liquid crystal display device composed of an LCD material which can be driven at a relatively low voltage of less than 3V. However, the liquid crystal used has a low voltage holding ratio, and a current leaks when a voltage is applied to the liquid crystal. An LCD material that can be driven at a voltage of 3 V or more has a relatively high voltage holding ratio of 95% or more, and a liquid crystal display device using an LCD material driven at a voltage of 3 V or more has high reliability.

[Prior Art C] FIG. 19C is a block diagram showing another example of a conventional source signal line side driving circuit 1801.

A clock signal (for example, 9 V) is input to the source signal line side driving circuit from outside the source signal line side driving circuit. Then, based on the input clock signal, the shift register circuit operates by the start pulse signal input to the shift register circuit at the same time, and sequentially generates a timing signal for sampling an image. The sampling circuit operates based on this timing signal, and the image signal is sampled.

FIG. 23 shows an example of a specific circuit configuration of the block diagram shown in FIG. A shift register circuit 31, a sampling circuit 32, and an image signal line 33 are arranged as shown in the figure.

A clock signal (CLK), an inverted clock signal (CLKb), a start pulse signal (SP), and a drive direction switching signal (SL / R) are input to the shift register circuit from the wiring shown in the figure.

A clock signal (CLK) (for example, 9 V) is input to the shift register circuit 31 from outside the source signal line side driving circuit.

The shift register circuit 31 operates according to the input clock signal and the start pulse signal input to the shift register circuit at the same time, and sequentially generates a timing signal for sampling an image. The generated timing signal is input to the sampling circuit 32.

It is obvious that prior art C has the disadvantages of both prior art A and prior art B. To drive the liquid crystal to a saturated state, the shift register circuit T
Since the FT easily breaks down due to punch-through or hot electrons due to the short channel effect, the channel length cannot be shortened, so that there is a problem that high-speed operation cannot be performed.

Further, in the circuit configuration of this conventional example, the voltage amplitude level of the clock signal is a voltage amplitude level provided with a certain margin voltage at the saturation voltage at the time of input from the outside of the source signal line side drive circuit. . For this reason, unnecessary radiation and power consumption cannot be suppressed to a level that does not cause a problem.

The above problem can be solved by using a liquid crystal display device composed of an LCD material which can be driven at a relatively low voltage of less than 3V. However, the liquid crystal used has a low voltage holding ratio, and a current leaks when a voltage is applied to the liquid crystal. An LCD material that can be driven at a voltage of 3 V or more has a relatively high voltage holding ratio of 95% or more, and a liquid crystal display device using an LCD material driven at a voltage of 3 V or more has high reliability.

[Prior Art D] FIG. 24A is a block diagram showing a conventional example of a conventional gate signal line side driving circuit.

A clock signal (CLK) (for example, 3 V) is input to the level shifter circuit from outside the gate signal line side drive circuit. The voltage amplitude level of the clock signal needs to be a voltage amplitude level at which the level shifter circuit can operate.

The voltage amplitude level of the clock signal input to the level shifter circuit is increased (for example, 3 V →
25V).

The selection signal input to the gate signal line is applied to all the pixels TF connected to the selected gate signal line.
It is necessary that T be a voltage amplitude level that ensures operation. The voltage of the selection signal is applied to the gate electrode of the pixel TFT connected to the gate signal line, so that a channel is formed in the pixel TFT. As a result, the pixel TF
A current flows from the source to the drain of T, an image signal is supplied to the liquid crystal, and the liquid crystal is driven.

Since the gate signal line has a long wiring and high wiring resistance, the selection signal input to the gate signal line causes a voltage drop when applied to the farthest pixel TFT. The greater the voltage drop, the lower the voltage applied to the gate electrode of the pixel TFT, and in the worst case, no channel is formed in the pixel TFT.

In order to reliably operate all the pixel TFTs and supply an image signal to the liquid crystal, the voltage amplitude level of the selection signal input to the gate signal line is set to a certain margin voltage at the voltage amplitude level of the image signal. It is necessary to provide and raise. Further, the selection signal is required to have a high voltage amplitude level so that a voltage drop due to the wiring resistance of the gate wiring does not matter.

This margin voltage is for surely supplying an image signal having the same voltage amplitude level as the saturation voltage to the pixel electrode of the liquid crystal cell. The margin voltage needs to be large enough to reliably supply the image signal of the saturation voltage to the pixel electrode.

The clock signal whose voltage amplitude level has been raised (for example, 25 V) is input to the shift register circuit.
The shift register circuit operates by the input clock signal and the start pulse signal input to the shift register circuit at the same time, and sequentially generates a selection signal for operating the pixel TFT. The generated selection signal is input to the gate signal line, a channel is formed in the pixel TFT, and an image signal is supplied to the liquid crystal.

In the case of the gate signal line side driving circuit, it is not necessary to operate the shift register circuit at a higher speed than the source signal line side driving circuit. As described above, the operation speed of the TFT is inversely proportional to the square of the channel length. The gate signal line side driving circuit, which has a lower operation speed than the source signal line side driving circuit, has a longer TFT channel length of the shift register circuit than the source signal line side driving circuit, and punch-through or hot due to a short channel effect. Failure due to electrons is unlikely to occur.

However, in recent years, development of a large-screen, high-resolution liquid crystal display device has been advanced as described above. Assuming that display is performed at the same frame rate, as the number of pixels of the liquid crystal display device increases, it is necessary to operate the shift register circuit of the gate signal line side drive circuit at a higher speed similarly to the source signal line side drive circuit. It is becoming. Therefore, it is required to further increase the driving frequency of the gate signal line side driving circuit shift register.

Then, the clock signal whose voltage amplitude level has been increased is input to the shift register circuit. The shift register circuit operates by the input clock signal and the start pulse signal input to the shift register circuit at the same time, and sequentially generates a selection signal for reliably operating the pixel TFT. The generated selection signal is input to the gate signal line.

It is obvious that prior art D has the same disadvantages as prior art A. In the prior art D, in order to ensure that all the pixel TFTs can operate, the voltage amplitude level of the selection signal input to the shift register circuit is reduced by punch-through due to a short channel effect or failure of the TFT of the shift register circuit due to hot electrons. It was difficult to make it low enough not to.

The above problem can be solved by using a liquid crystal display device composed of an LCD material which can be driven at a relatively low voltage of less than 3V. However, the liquid crystal used has a low voltage holding ratio, and a current leaks when a voltage is applied to the liquid crystal. An LCD material that can be driven at a voltage of 3 V or more has a relatively high voltage holding ratio of 95% or more, and a liquid crystal display device using an LCD material driven at a voltage of 3 V or more has high reliability.

[Prior Art E] FIG. 24B is a block diagram showing another example of a conventional gate signal line side driving circuit.

A clock signal (CLK) (for example, 10 V) input from outside the gate signal line side driving circuit is directly input to the shift register circuit. The input clock signal has a voltage amplitude level at which the shift register circuit can operate. Then, the shift register circuit operates by the input clock signal and the start pulse signal input to the shift register circuit at the same time, and sequentially generates a selection signal for operating the pixel TFT.

The generated selection signal is input to the level shifter circuit, and its voltage amplitude level is raised to a voltage amplitude level at which all the pixel TFTs can operate reliably (for example, 10 V → 30 V). The selection signal having the increased voltage amplitude level is supplied to the gate signal line.

It is obvious that prior art E has the same disadvantages as prior art B. In the prior art B, when the input clock signal is set to a voltage amplitude level that enables high-speed driving of the shift register circuit, it is difficult to reduce the unnecessary radiation to a level that does not cause a problem, and power consumption is suppressed as described above. There was another problem.

The above problem can be solved by using a liquid crystal display device composed of an LCD material which can be driven at a relatively low voltage of less than 3V. However, the liquid crystal used has a low voltage holding ratio, and a current leaks when a voltage is applied to the liquid crystal. An LCD material that can be driven at a voltage of 3 V or more has a relatively high voltage holding ratio of 95% or more, and a liquid crystal display device using an LCD material driven at a voltage of 3 V or more has high reliability.

[Prior Art F] FIG. 24C is a block diagram showing another example of a conventional gate signal line side driving circuit.

A clock signal (for example, 20 V) is input to the shift register circuit from outside the gate signal line side driving circuit. The voltage amplitude level of the clock signal input at this time is the voltage amplitude level of the selection signal necessary for driving the liquid crystal to a saturated state.

Based on the clock signal input to the shift register circuit, the shift register circuit operates by the start pulse signal input to the shift register circuit at the same time, and sequentially generates a selection signal for operating the pixel TFT. The generated selection signal is input to the gate signal line.

It is obvious that Prior Art F has the same disadvantages as Prior Art C. If all pixel TFTs are to be operated reliably, there is a problem that the TFTs of the shift register circuit are liable to be damaged due to punch-through or hot electrons due to a short channel effect, so that the channel length cannot be shortened, and thus high-speed operation cannot be performed. Was.

The above problem can be solved by using a liquid crystal display device composed of an LCD material which can be driven at a relatively low voltage of less than 3V. However, the liquid crystal used has a low voltage holding ratio, and a current leaks when a voltage is applied to the liquid crystal. An LCD material that can be driven at a voltage of 3 V or more has a relatively high voltage holding ratio of 95% or more, and a liquid crystal display device using an LCD material driven at a voltage of 3 V or more has high reliability.

The problems of the prior arts A to F are summarized below. A liquid crystal display device that can be driven at a relatively low voltage of 3 V or less has a low voltage holding ratio, leaks current when a voltage is applied to the liquid crystal, and tends to deteriorate the liquid crystal, so that the reliability is low. Therefore, it has been desired to increase the reliability of the liquid crystal display device by using a liquid crystal display device driven at a relatively high voltage with a high voltage holding ratio. However, in the case of using a liquid crystal display device driven at a relatively high voltage, in a conventional source signal line side driving circuit, when the liquid crystal is driven to a saturated state, the TFT of the shift register circuit causes punch-through or hot electron emission due to a short channel effect. It was easy to break down. In addition, with the recent increase in screen size of liquid crystal panels, high-speed operation of shift register circuits has been required. However, in the conventional source signal line side drive circuit, if power consumption and unnecessary radiation are suppressed, it is difficult to operate the shift register circuit at high speed, and it has not been possible to meet the demands associated with a large-sized liquid crystal panel.

Similarly, in the conventional gate signal line side driving circuit, if all the pixel TFTs are reliably operated, the TFTs of the shift register circuit are likely to be broken down by punch-through due to short channel effect or hot electrons. If power consumption and unnecessary radiation were suppressed, it was difficult to operate the shift register circuit at high speed, and it was not possible to meet the demands for a larger liquid crystal panel.

It is required to realize a driving circuit capable of driving without such a problem and a highly reliable semiconductor display device having the driving circuit.

[0077]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize a drive circuit capable of obtaining a voltage amplitude level of a clock signal input to a shift register circuit, a voltage for operating the shift register circuit at high speed, and a channel length. . As a result, the liquid crystal is driven to a saturated state, or all the pixels TF
It is an object of the present invention to realize a high-speed driving circuit and a semiconductor display device having the driving circuit, in which the shift register circuit does not fail even if T is operated reliably. Another object of the present invention is to enable high-speed operation of a shift register circuit even when the voltage amplitude level of a clock signal input from the outside of a driving circuit is suppressed to such a level that power consumption and unnecessary radiation do not matter.

In the present invention, the voltage amplitude level of the clock signal input from the outside of the drive circuit is raised by the level shifter circuit and input to the shift register circuit. Then, the timing signal generated by the shift register circuit is further input to the level shifter circuit,
I will increase the voltage amplitude level in stages.

As described above, according to the present invention, by providing the level shifter circuit before and after the shift register circuit, the power supply voltage of the shift register circuit can be reduced by the short-channel effect and the TFT of the shift register circuit can be damaged by hot electrons. Low enough to not. Further, the channel length of the TFT of the shift register circuit is increased to a range that can be created, and the voltage amplitude level of the clock signal applied to the source of the TFT is increased to such an extent that the TFT operates, and the shift register circuit operates. Let it. As a result, even if the liquid crystal is driven to a saturated state or all the pixel TFTs are reliably operated, the shift register circuit does not break down,
A driving circuit which operates at high speed and a semiconductor display device having the driving circuit are provided. Another object is to provide a semiconductor display device including a drive circuit capable of suppressing power consumption and unnecessary radiation to a level that does not cause a problem even when a shift register circuit operates at high speed.

The configuration of the present invention will be described below.

According to one embodiment of the present invention, the first level shifter circuit is a source signal line side drive circuit having a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit. Is
An input signal input from the outside of the source signal line side drive circuit to the first level shifter circuit is raised to a voltage amplitude level at which the shift register circuit can operate, and input to the shift register circuit, The shift register circuit generates a timing signal for sampling an image signal supplied from outside of the source signal line side driving circuit based on the input signal, and generates the generated timing signal. Input to a second level shifter circuit, wherein the second level shifter circuit further increases the voltage amplitude level of the input timing signal to a higher voltage and inputs the voltage amplitude level to the sampling circuit. The image signal is sampled by a timing signal, and a source connected to the source signal line side drive circuit is sampled. The source signal line side driving circuit and supplying to the signal line is provided. This achieves the above object.

According to an embodiment of the present invention,
A source signal line side drive circuit including a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit, wherein the first level shifter circuit is provided from outside the source signal line side drive circuit. A clock signal having a voltage amplitude level operable by the first level shifter circuit, which is input to the first level shifter circuit, is raised to a voltage amplitude level operable by the shift register circuit, and the shift register circuit And the shift register circuit generates a timing signal for sampling an image signal supplied from outside the source signal line side driving circuit based on the clock signal input to the shift register circuit. Then, the generated timing signal is input to the second level shifter circuit, and the second The shifter circuit increases the voltage amplitude level of the timing signal input to the second level shifter circuit to a voltage amplitude level provided with a certain margin voltage in the saturation voltage of the liquid crystal, and inputs the voltage to the sampling circuit. Wherein the sampling circuit samples the image signal according to the timing signal input to the sampling circuit, and supplies the image signal to a source signal line connected to the source signal line side driving circuit. A drive circuit is provided. This achieves the above object.

According to an embodiment of the present invention,
A gate signal line side driving circuit including a first level shifter circuit, a second level shifter circuit, and a shift register circuit, wherein the first level shifter circuit is configured to receive an input from outside the gate signal line side driving circuit. The signal is raised to a voltage amplitude level at which the shift register circuit can operate, and input to the shift register circuit.The shift register circuit, based on the input signal input to the shift register circuit, A selection signal is generated, and the generated selection signal is input to the second level shifter circuit. The second level shifter circuit connects the voltage amplitude level of the input selection signal to a gate signal line. Voltage to a voltage amplitude level at which all of the pixel TFTs that can be operated can be reliably operated, and the high voltage is applied to the gate signal line. The gate signal line side driving circuit and supplying directly or via the buffer circuit a signal is provided. This achieves the above object.

According to an embodiment of the present invention,
A gate signal line side drive circuit including a first level shifter circuit, a second level shifter circuit, and a shift register circuit, wherein the first level shifter circuit is configured to receive the first level shifter circuit from outside the gate signal line side drive circuit; A clock signal input to a level shifter circuit and having a voltage amplitude level at which the first level shifter circuit can operate is raised to a voltage amplitude level at which the shift register circuit can operate,
The shift register circuit inputs a pixel TFT connected to a gate signal line side driving circuit via a gate signal line based on the clock signal input to the shift register circuit. A selection signal to be operated is generated, and the generated selection signal is input to the second level shifter circuit. The second level shifter circuit outputs a voltage amplitude level of the selection signal input to the second level shifter circuit. Is increased to a voltage amplitude level at which all the pixel TFTs connected to the gate signal line can be reliably operated, and the voltage is increased to the gate signal line by the second level shifter circuit. A gate signal line side driving circuit is provided which supplies the selection signal. This achieves the above object.

According to an embodiment of the present invention,
An active matrix circuit in which a plurality of pixel TFTs are arranged in a matrix; a plurality of source signal lines connected to respective source electrodes of the plurality of pixel TFTs; and a plurality of source signal lines connected to respective gate electrodes of the plurality of pixel TFTs A plurality of gate signal lines, a source signal line side driving circuit connected to the plurality of source signal lines, and a gate signal line side driving circuit connected to the plurality of gate signal lines. The source signal line side driving circuit includes a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit,
The first level shifter circuit outputs a clock signal of a voltage amplitude level that is operable by the first level shifter circuit, which is input to the first level shifter circuit from outside the source signal line side driving circuit, by the shift register. The voltage is increased to a voltage amplitude level at which the circuit can operate, and the voltage is input to the shift register circuit.
Based on the clock signal input to the shift register circuit, a timing signal for sampling an image signal supplied from outside the source signal line side driving circuit is generated, and the generated timing signal is generated. Second
And the second level shifter circuit converts the voltage amplitude level of the timing signal input to the second level shifter circuit to a voltage amplitude level provided with a certain margin voltage in the saturation voltage of the liquid crystal. Input to the sampling circuit after increasing the voltage, the sampling circuit samples the image signal by the timing signal input to the sampling circuit,
A semiconductor display device is provided that supplies the signal to the source signal line. This achieves the above object.

The source signal line side driving circuit may be formed on the same substrate as the active matrix circuit.

According to an embodiment of the present invention,
An active matrix circuit in which a plurality of pixel TFTs are arranged in a matrix; a plurality of source signal lines connected to respective source electrodes of the plurality of pixel TFTs; and a plurality of source signal lines connected to respective gate electrodes of the plurality of pixel TFTs A plurality of gate signal lines, a source signal line side driving circuit connected to the plurality of source signal lines, and a gate signal line side driving circuit connected to the plurality of gate signal lines. The gate signal line side driving circuit has a first level shifter circuit, a second level shifter circuit, and a shift register circuit, and the first level shifter circuit is provided from outside the gate signal line side driving circuit. A clock signal having a voltage amplitude level that is operable by the first level shifter circuit and that is input to the first level shifter circuit is shifted by the shift operation. A voltage is raised to a voltage amplitude level at which the register circuit can operate, and the voltage is input to the shift register circuit.The shift register circuit sets the gate signal line based on the clock signal input to the shift register circuit. Generating a selection signal for operating the pixel TFT connected to the gate signal line side driving circuit through the second level shifter circuit, and inputting the generated selection signal to the second level shifter circuit; Raising the voltage amplitude level of the timing signal input to the second level shifter circuit to a voltage amplitude level capable of reliably operating all the pixel TFTs connected to the gate signal line; A semiconductor device for supplying a selection signal whose voltage is increased by the second level shifter circuit to the gate signal line. Apparatus is provided. This achieves the above object.

The gate signal line side driving circuit may be formed on the same substrate as the active matrix circuit.

According to an embodiment of the present invention,
An active matrix circuit in which a plurality of pixel TFTs are arranged in a matrix; a plurality of source signal lines connected to respective source electrodes of the plurality of pixel TFTs; and a plurality of source signal lines connected to respective gate electrodes of the plurality of pixel TFTs A plurality of gate signal lines, a source signal line side driving circuit connected to the plurality of source signal lines, and a gate signal line side driving circuit connected to the plurality of gate signal lines. The source signal line side driving circuit has a first level shifter circuit, a second level shifter circuit, a first shift register circuit, and a first sampling circuit, and the first level shifter circuit is provided with the source signal line side driving circuit. A clock signal having a voltage amplitude level that is operable by the first level shifter circuit and is input to the first level shifter circuit from outside the circuit. Is increased to a voltage amplitude level at which the first shift register circuit can operate, and is input to the first shift register circuit, and the first shift register circuit is configured to input the first shift register circuit A timing signal for sampling an image signal supplied from outside the source signal line side driving circuit is generated based on a clock signal, and the generated timing signal is input to the second level shifter circuit. The two-level shifter circuit raises the voltage amplitude level of the timing signal input to the second level shifter circuit to a voltage amplitude level provided with a certain margin voltage in the saturation voltage of the liquid crystal, and sends the voltage to the first sampling circuit. And the first sampling circuit receives the timing signal input to the first sampling circuit. The image signal is sampled and supplied to the source signal line, and the gate signal line side driving circuit has a third level shifter circuit, a fourth level shifter circuit, and a second shift register circuit, The level shifter circuit is capable of operating the second shift register circuit with a clock signal having a voltage amplitude level that is operable by the third level shifter circuit and that is input to the third level shifter circuit from outside the gate signal line side drive circuit. The voltage is increased to an appropriate voltage amplitude level and input to the second shift register circuit. The second shift register circuit generates the gate signal line based on the clock signal input to the second shift register circuit. A selection signal for operating the pixel TFT connected to the gate signal line side driving circuit through the gate signal line side driving circuit, and generating the selection signal. Select signal is input to the fourth level shifter circuit, and the fourth level shifter circuit changes the voltage amplitude level of the timing signal input to the fourth level shifter circuit to all of the gate signal lines connected to the gate signal line. Pixel TFT
A semiconductor display device characterized in that the voltage is increased to a voltage amplitude level at which the voltage can be reliably operated, and a selection signal whose voltage is increased by the fourth level shifter circuit is supplied to the gate signal line. . This achieves the above object.

The source signal line side drive circuit and the gate signal line side drive circuit may be formed on the same substrate as the active matrix circuit.

According to an embodiment of the present invention,
A first level shifter circuit, a second level shifter circuit, a third level shifter circuit, a first latch circuit,
In a drive circuit of a digitally driven semiconductor display device including a second latch circuit, a shift register circuit, and a D / A conversion circuit, the first level shifter circuit includes a first level shifter external to the drive circuit. The input signal input to the circuit is raised to a voltage amplitude level at which the shift register circuit can operate, and is input to the shift register circuit.The shift register circuit is configured based on the input signal. Generating a timing signal for determining a timing at which a digital signal supplied from outside of the driving circuit is written to the first latch circuit;
, The digital signal is input to the third level shifter circuit, and the digital signal output from the third level shifter circuit is input to the first latch circuit at a timing determined by the timing signal. The digital signal that is input and input to the first latch circuit is output after performing logic rendering in the second latch circuit after the logical rendering, and the output digital signal is output from the second latch circuit. A driving circuit for a semiconductor display device, which is input to a D / A conversion circuit via a level shifter circuit and is converted into an analog signal, is provided. This achieves the above object.

[0092]

BEST MODE FOR CARRYING OUT THE INVENTION

The drive circuit of the present invention will be described by taking a source signal line side drive circuit as an example. First, a block diagram of a configuration of a source signal line side driver circuit is shown in FIG.

A clock signal (CLK) is input to the source signal line side driving circuit from outside the source signal line side driving circuit.

The input clock signal is input to the first level shifter circuit, and its voltage amplitude level is raised. Then, the clock signal whose voltage amplitude level has been increased by the first level shifter circuit is input to the shift register circuit. Based on the input clock signal, the shift register circuit operates by a start pulse signal input to the shift register circuit at the same time, and a timing signal for sampling an image is sequentially generated.

This timing signal is input to the second level shifter circuit, and its voltage amplitude level is raised again. The sampling circuit operates based on the timing signal whose voltage amplitude level has been raised by the second level shifter circuit, and the image signal is sampled. The sampled image signal is supplied to a source signal line, and is input to a source of a pixel TFT connected to the source signal line.

FIG. 2 shows an example of the circuit configuration of the block diagram shown in FIG.

The first level shifter circuit 201 receives clock signals (CLK, CL) from outside the source signal line side drive circuit.
Kb) is input. The voltage amplitude level of the clock signal is required to be as low as possible within a range in which the first level shifter circuit 201 can be driven, in order to suppress unnecessary radiation to a degree that does not cause a problem. It is also necessary to suppress power consumption.

The clock signal input to the first level shifter circuit 201 is raised in voltage and output. At this time, the voltage amplitude level of the clock signal is high enough that the TFT of the shift register circuit 202 does not fail due to punch-through or hot electrons due to the short channel effect and that the TFT having a manufacturable channel length operates. It is necessary to increase the voltage.

The clock signal whose voltage amplitude level has been increased by the first level shifter circuit 201 is input to the shift register circuit 202. The start pulse signal (SP) whose voltage amplitude level has been increased by the level shifter circuit is input to the shift register circuit 202. Based on the clock signal input to the shift register circuit 202, the start pulse signal input to the shift register circuit 202 at the same time changes the shift register circuit 202
Are the pixel TFTs corresponding to the source signal lines (S1, S2)
An operation of generating a timing signal for determining the timing of sampling the image signal to the image signal is started. The timing signal generated by the shift register circuit 202 is the second
Is input to the level shifter circuit 203.

The timing signal input to the second level shifter circuit 203 is raised in voltage. At this time, the timing signal is used to sample an image signal of a voltage amplitude level (saturation voltage) at which the liquid crystal is driven into a saturated state.
It is necessary to increase the voltage to a voltage amplitude level at which a certain margin voltage is provided at the saturation voltage.

This margin voltage is for surely supplying the image signal of the saturation voltage to the source of the pixel TFT. It is necessary that the magnitude of the margin voltage is large enough that the image signal of the saturation voltage is sampled by the timing signal and supplied to the source signal lines (S1, S2) reliably.

The timing signal raised in voltage by the second level shifter circuit 203 is supplied to the sampling circuit 20.
4 is input.

The sampling circuit 204 is a set of analog switches connected to each source line (S1, S2). When a timing signal is input to the sampling circuit 204, a voltage of the timing signal is applied to a gate electrode of a TFT constituting an analog switch of the sampling circuit 204. As a result, a channel is formed in the TFT constituting the analog switch, and a current flows from the source to the drain. Therefore, the image signal is sampled and supplied to the source of the pixel TFT via the source signal line (S1, S2).

In the present invention, by providing the level shifter circuit before and after the shift register circuit, the TFT of the shift register circuit does not fail due to punch-through or hot electrons due to the short channel effect, and the TFT having a channel length that can be manufactured operates. The shift register circuit can be operated with a clock signal having a voltage amplitude level that is small enough. As a result, the shift register circuit can be operated at high speed without failure, and the liquid crystal can be driven to a saturated state. Further, even if the voltage amplitude level of the clock signal input from the outside of the source signal line side driving circuit is made as low as possible within the range in which the operation of the level shifter circuit is possible, high speed operation of the shift register circuit becomes possible. Power consumption and unnecessary radiation can be suppressed to a level that does not cause a problem.

[0106]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The driving circuit of the present invention and a semiconductor display device having the driving circuit will be described in detail with reference to FIGS.

(Embodiment 1) In this embodiment, by providing a level shifter circuit before and after a shift register circuit,
An example in which the configuration of the present invention for raising the voltage amplitude level of a signal in two stages before and after a shift register circuit is used in a source signal line side driving circuit will be described. FIG. 3 shows a configuration of the semiconductor display device of the present embodiment, particularly, an active matrix type liquid crystal display device.

The source signal line side driving circuit 301 and the gate signal line side driving circuit 302 are integrally formed on the same substrate as the pixel matrix portion 308 composed of an active matrix circuit.

Further, in the pixel matrix portion 308, a plurality of source signal lines 303 connected to the source signal line side driving circuit 301 and a plurality of gate signal lines 304 connected to the gate signal line side driving circuit 302 intersect. ing. In a region surrounded by the source signal line 303 and the gate signal line 304, a plurality of pixel TFTs 305 connected to the source signal line 303 and the gate signal line 304 are respectively provided, and a liquid crystal is disposed between the counter electrode and the pixel electrode. Liquid crystal cell 306 sandwiching
And a storage capacitor 307 are provided.

An image signal input to the source signal line 303 is selected by the pixel TFT 305 and written to a predetermined pixel electrode.

An image signal sampled by the timing signal output from the source signal line side driving circuit 301 is supplied to the source signal line 303 by the sampling circuit.

The pixel TFT 305 operates by a selection signal input from the gate signal line side driving circuit 302 via the gate signal line 304.

Next, FIG. 4 shows a block diagram of the source signal line side driving circuit of this embodiment. In this embodiment, a liquid crystal having a saturation voltage of 5 V is used. A clock signal (CLK) having a voltage amplitude level of 2.5 V is input from the outside of the source signal line side driving circuit to the first level shifter circuit of the source signal line side driving circuit. The voltage amplitude level of the clock signal input to the first level shifter circuit is required to be as low as possible within a range in which the first level shifter circuit can be driven, in order to suppress unnecessary radiation to a degree that does not cause a problem. It is also necessary to suppress power consumption.

The voltage level of the clock signal input to the first level shifter circuit is increased from 2.5 V to 5 V in this embodiment (increased voltage) by the first level shifter circuit, and the clock signal is supplied to the shift register circuit. Is entered.

The voltage amplitude level of the clock signal input to the shift register circuit is required to be within a range in which the shift register circuit can operate. In this embodiment, the shift register circuit can operate at 5V. For example, in this embodiment, in order to operate a shift register circuit including a TFT having a channel length of 2 μm of the source signal line side driving circuit at a frequency of 12.5 MHz or more, the voltage of a clock signal input to the shift register circuit is required. The amplitude level needs to be 4 V or more. In the present embodiment, the voltage amplitude level is increased to 5 V, but the voltage amplitude level is not limited to this value in the present invention. A necessary condition is that the voltage amplitude level of the clock signal input to the shift register circuit be within a range in which the shift register circuit can operate. The level shifter circuit may be used not only for the clock signal but also for other start pulse signals.

A clock signal having a voltage amplitude level of 5 V output from the level shifter circuit is input to the shift register circuit. Based on the clock signal input to the shift register circuit, the shift register circuit uses the start pulse signal input to the shift register circuit at the same time,
An operation of sequentially generating a timing signal for sampling the image signal supplied from the image signal line is performed. The generated timing signal is input to the second level shifter circuit.

The voltage amplitude level of the timing signal input to the second level shifter circuit is increased by the second level shifter circuit. This timing signal needs to be raised to a voltage amplitude level at which a certain margin voltage is provided at the saturation voltage. The timing signal input to the second level shifter at 5V is raised to 12V, and the 12V timing signal is input to the sampling circuit. The sampling circuit performs an operation of sampling the image signal supplied from the image signal line according to the timing signal input to the sampling circuit.

The sampled image signal is supplied to a source signal line, and is input to a pixel TFT connected to the source signal line to drive a liquid crystal.

FIG. 5 shows a specific circuit configuration of the source signal line side driving circuit of this embodiment, and FIG. 6 shows a clock signal and a point A of the specific circuit of this embodiment shown in FIG. , B1, B2, C1, C2 and the source signal line S
1 and 2 show timing charts.

A clock signal (CLK) having a voltage amplitude level of 2.5 V is supplied to the first level shifter
It is amplified to V (point A). The clock signal having the increased voltage amplitude level is input to the shift register circuit 502, and at the same time, the start pulse signal (SP) whose voltage amplitude level has been increased by the level shifter circuit is input to the shift register circuit 502 to generate a timing signal. (Points B1, B2).

This timing signal is further amplified by the second level shifter circuit 503 to become 12 V (points C1 and C2). Then, the timing signal is input to the analog switch 505, the image signal is sampled, and the source signal line (S1, S1) from which the image signal is selected.
2).

As described above, in the present invention, by providing the level shifter circuit before and after the shift register circuit,
A clock signal with a voltage amplitude level that is low enough that the TFTs of the shift register circuit do not fail due to punch-through or hot electrons due to the short channel effect and high enough to operate a TFT having a manufacturable channel length is input to the shift register circuit. Can be. As a result, the shift register circuit can operate at higher speed. Also,
Even if the voltage amplitude level of the clock signal input from the outside of the source signal line side drive circuit is made as low as possible within the range in which the level shifter circuit can operate, high-speed operation of the shift register circuit is possible, so that power consumption is reduced. In addition, unnecessary radiation can be suppressed to a level that does not cause a problem. In this embodiment, an example in which the present invention is applied to the source signal line side driving circuit has been described. However, the present invention is not limited to this embodiment.

(Embodiment 2) In this embodiment, the level shifter circuit is provided before and after the shift register circuit,
Another example in which the configuration of the present invention for raising the voltage amplitude level of a signal in two stages before and after a shift register circuit is used in a source signal line side driving circuit will be described.

Next, FIG. 7 shows a block diagram of the source signal line side driving circuit of this embodiment. In this embodiment, a liquid crystal having a saturation voltage of 6 V is used. 3 from outside of the source signal line side drive circuit
A clock signal (CLK) having a voltage amplitude level of V is input to the first level shifter circuit of the source signal line side drive circuit. The voltage amplitude level of the clock signal input to the first level shifter circuit is required to be as low as possible within a range in which the first level shifter circuit can be driven, in order to suppress unnecessary radiation to a degree that does not cause a problem. It is also necessary to suppress power consumption.

The clock signal input to the first level shifter circuit is raised (increased in voltage) from 3 V to 10 V in this embodiment by the first level shifter circuit, and is input to the shift register circuit. You.

The voltage amplitude level of the clock signal input to the shift register circuit is required to be within a range in which the shift register circuit can operate. In this embodiment, the shift register circuit can operate at 10 V. For example, in this embodiment, in order to operate the shift register circuit including the TFT having a channel length of 3 μm of the source signal line side driving circuit at a frequency of 5 MHz or more, the voltage amplitude level of the clock signal input to the shift register circuit is required. Needs to be 8 V or more. In the present embodiment, the voltage amplitude level is increased to 10 V, but the voltage amplitude level is not limited to this value in the present invention. A necessary condition is that the voltage amplitude level of the clock signal input to the shift register circuit be within a range in which the shift register circuit can operate. The level shifter circuit may be used not only for the clock signal but also for other start pulse signals.

A clock signal having a voltage amplitude level of 10 V output from the level shifter circuit is input to the shift register circuit. Based on the clock signal input to the shift register circuit, the start register signal input to the shift register circuit at the same time causes the shift register circuit to sequentially execute timing signals for sampling the image signal supplied from the image signal line. Perform the operation to generate. The generated timing signal is input to the second level shifter circuit.

The voltage amplitude level of the timing signal input to the second level shifter circuit is increased by the second level shifter circuit. This timing signal needs to be raised to a voltage amplitude level at which a certain margin voltage is provided at the saturation voltage. At 10 V, the timing signal input to the second level shifter is raised to 15 V, and the 15 V timing signal is input to the sampling circuit. The sampling circuit performs an operation of sampling the image signal supplied from the image signal line according to the timing signal input to the sampling circuit.

The sampled image signal is supplied to a source signal line, and is input to a pixel TFT connected to the source signal line to drive a liquid crystal.

As described above, in the present invention, by providing the level shifter circuit before and after the shift register circuit,
A clock signal with a voltage amplitude level that is low enough that the TFTs of the shift register circuit do not fail due to punch-through or hot electrons due to the short channel effect and high enough to operate a TFT having a manufacturable channel length is input to the shift register circuit. Can be. As a result, the shift register circuit can operate at higher speed. Also,
Even if the voltage amplitude level of the clock signal input from the outside of the source signal line side drive circuit is made as low as possible within the range in which the level shifter circuit can operate, high-speed operation of the shift register circuit is possible, so that power consumption is reduced. In this embodiment, in which unnecessary radiation can be suppressed to a level that does not cause a problem, an example in which the present invention is applied to the source signal line side driving circuit has been described. However, the present invention is not limited to this embodiment.

(Embodiment 3) In this embodiment, by providing a level shifter circuit before and after a shift register circuit,
Another example in which the configuration of the present invention for raising the voltage amplitude level of a signal in two stages before and after a shift register circuit is used in a source signal line side driving circuit will be described.

Next, FIG. 8 shows a block diagram of the source signal line side driving circuit of this embodiment. In this embodiment, a liquid crystal having a saturation voltage of 7 V is used. 5 from outside of the source signal line side drive circuit
A clock signal (CLK) having a voltage amplitude level of V is input to the first level shifter circuit of the source signal line side drive circuit. The voltage amplitude level of the clock signal input to the first level shifter circuit is required to be as low as possible within a range in which the first level shifter circuit can be driven, in order to suppress unnecessary radiation to a degree that does not cause a problem. It is also necessary to suppress power consumption.

The clock signal input to the first level shifter circuit is raised (increased in voltage) from 5 V to 12 V in this embodiment by the first level shifter circuit, and is input to the shift register circuit. You.

The voltage amplitude level of the clock signal input to the shift register circuit is required to be within a range in which the shift register circuit can operate. In this embodiment, the shift register circuit can operate at 12V. For example, in this embodiment, in order to operate the shift register circuit including the TFT having a channel length of 5 μm of the source signal line side driving circuit at a frequency of 3 MHz or more, the voltage amplitude level of the clock signal input to the shift register circuit is required. Must be 10 V or more. In this embodiment, the voltage amplitude level is increased to 12 V, but the voltage amplitude level is not limited to this value in the present invention. A necessary condition is that the voltage amplitude level of the clock signal input to the shift register circuit be within a range in which the shift register circuit can operate. The level shifter circuit may be used not only for the clock signal but also for other start pulse signals.

A clock signal having a voltage amplitude level of 12 V output from the level shifter circuit is input to the shift register circuit. Based on the clock signal input to the shift register circuit, the start register signal input to the shift register circuit at the same time causes the shift register circuit to sequentially execute timing signals for sampling the image signal supplied from the image signal line. Perform the operation to generate. The generated timing signal is input to the second level shifter circuit.

The voltage amplitude level of the timing signal input to the second level shifter circuit is increased by the second level shifter circuit. This timing signal needs to be raised to a voltage amplitude level at which a certain margin voltage is provided at the saturation voltage. At 12 V, the timing signal input to the second level shifter circuit is raised to 18 V, and the 18 V timing signal is input to the sampling circuit. The sampling circuit performs an operation of sampling the image signal supplied from the image signal line according to the timing signal input to the sampling circuit.

The sampled image signal is supplied to a source signal line, and is input to a pixel TFT connected to the source signal line to drive a liquid crystal.

As described above, in the present invention, by providing the level shifter circuit before and after the shift register circuit,
A clock signal with a voltage amplitude level that is low enough that the TFTs of the shift register circuit do not fail due to punch-through or hot electrons due to the short channel effect and high enough to operate a TFT having a manufacturable channel length is input to the shift register circuit. Can be. As a result, the shift register circuit can operate at higher speed. Also,
Even if the voltage amplitude level of the clock signal input from the outside of the source signal line side drive circuit is made as low as possible within the range in which the level shifter circuit can operate, high-speed operation of the shift register circuit is possible, so that power consumption is reduced. In this embodiment, in which unnecessary radiation can be suppressed to a level that does not cause a problem, an example in which the present invention is applied to the source signal line side driving circuit has been described. However, the present invention is not limited to this embodiment.

(Embodiment 4) In this embodiment, an example in which the configuration of the present invention is applied to a gate signal line side driving circuit will be described.

FIG. 9 is a block diagram of the gate signal line side driving circuit of this embodiment. In this embodiment, a liquid crystal having a saturation voltage of 15 V is used. 3 V from outside the gate signal line side drive circuit
Is input to the first level shifter circuit of the gate signal line side drive circuit. The voltage amplitude level of the clock signal input to the first level shifter circuit is required to be as low as possible within a range in which the first level shifter circuit can be driven, in order to suppress unnecessary radiation to a degree that does not cause a problem. It is also necessary to suppress power consumption.

The clock signal input to the first level shifter circuit has its voltage amplitude level raised from 3 V to 10 V (increased voltage) by the first level shifter circuit, and is input to the shift register circuit.

The voltage amplitude level of the clock signal input to the shift register circuit is required to be within a range in which the shift register circuit can operate. In the present embodiment, the voltage amplitude level is increased to 10 V, but the voltage amplitude level is not limited to this value in the present invention. A necessary condition is that the voltage amplitude level of the clock signal input to the shift register circuit be within a range in which the shift register circuit can operate. The level shifter circuit may be used not only for the clock signal but also for other start pulse signals.

A clock signal having a voltage amplitude level of 10 V output from the level shifter circuit is input to the shift register circuit. Based on the clock signal input to the shift register circuit, the start pulse signal input to the shift register circuit at the same time allows the shift register circuit to reliably operate all the pixel TFTs connected to the gate signal line. The operation of sequentially generating the selection signals is performed. The generated selection signal is input to the second level shifter circuit.

The voltage amplitude level of the selection signal input to the second level shifter circuit is increased by the second level shifter circuit. This selection signal needs to be raised to a voltage amplitude level necessary for reliably operating all the pixel TFTs. At 10 V, the selection signal input to the second level shifter is raised to 20 V, the 20 V selection signal is input to the gate signal line, and the pixel TFT operates to supply an image signal to the liquid crystal.

FIG. 10 shows a specific circuit configuration of the block diagram shown in FIG.

[0146] The clock signal (CLK) input to the first level shifter circuit 1001 is raised in voltage and output. At this time, the voltage amplitude level is
001 is a voltage amplitude level that allows the operation of the pixel TF.
It is preferable that T is lower than the voltage amplitude level of the selection signal necessary to operate T reliably. The clock signal is input to the shift register circuit 1002.

The start pulse signal (SP) whose voltage amplitude level has been increased by the level shifter circuit is input to the shift register circuit 1002. The shift register circuit 1002 starts operating at a predetermined timing in response to the input of the start pulse signal. Accordingly, based on the clock signal input to the shift register circuit 1002, the pixel T
Selection signals for operating the FT are sequentially output and input to the second level shifter circuit 1003.

The selection signal input to the second level shifter circuit 1003 is raised to a higher voltage again and output. The high-voltage selection signal is supplied to the gate signal lines (g1, g2, g).
Input to 3). At this time, it is necessary to increase the voltage amplitude level to the voltage amplitude level of the selection signal necessary for reliably operating all the pixel TFTs.

As described above, by providing the level shifter circuits before and after the shift register circuit, the TFTs of the shift register circuit have TFTs whose channel length is low enough to prevent failure due to punch-through due to a short channel effect or hot electrons, and which can be manufactured. Can input a clock signal having a voltage amplitude level high enough to operate the shift register circuit, thereby suppressing power consumption. Further, even if the voltage amplitude level of the clock signal input from the outside of the gate signal line side driving circuit is made as low as possible within the range in which the operation of the level shifter circuit is possible, high speed operation of the shift register circuit becomes possible. In the present embodiment, in which power consumption and unnecessary radiation can be suppressed to a level that does not cause a problem, an example in which the present invention is applied to the gate signal line side driving circuit has been described. However, the present invention is not limited to this embodiment.

Note that the gate signal line side driving circuit shown in this embodiment can be used in the active matrix type liquid crystal display device shown in FIG. 3 of the first embodiment.

(Embodiment 5) In this embodiment, another example in which the configuration of the present invention is applied to a gate signal line side driving circuit will be described.

FIG. 11 is a block diagram of the gate signal line side driving circuit of this embodiment. In this embodiment, a liquid crystal having a saturation voltage of 14 V is used. 5 from the outside of the gate signal line side drive circuit
A clock signal (CLK) having a voltage amplitude level of V is input to the first level shifter circuit of the gate signal line side drive circuit. The voltage amplitude level of the clock signal input to the first level shifter circuit is required to be as low as possible within a range in which the first level shifter circuit can operate, in order to suppress unnecessary radiation to such an extent that no problem occurs. It is also necessary to suppress power consumption.

The clock signal input to the first level shifter circuit has its voltage amplitude level increased from 5 V to 12 V (increased voltage) by the first level shifter circuit, and is input to the shift register circuit.

The voltage amplitude level of the clock signal input to the shift register circuit is required to be within a range in which the shift register circuit can operate. In this embodiment, the voltage amplitude level is increased to 12 V, but the voltage amplitude level is not limited to this value in the present invention. A necessary condition is that the voltage amplitude level of the clock signal input to the shift register circuit be within a range in which the shift register circuit can operate. The level shifter circuit may be used not only for the clock signal but also for other start pulse signals.

A clock signal having a voltage amplitude level of 12 V output from the first level shifter circuit is input to the shift register circuit. Based on the clock signal input to the shift register circuit, the start pulse signal input to the shift register circuit at the same time allows the shift register circuit to reliably operate all the pixel TFTs connected to the gate signal line. The operation of sequentially generating the selection signals is performed. The generated selection signal is input to the second level shifter circuit.

The voltage amplitude level of the selection signal input to the second level shifter circuit is increased by the second level shifter circuit. This selection signal needs to be raised to a voltage amplitude level necessary for reliably operating all the pixel TFTs. At 12 V, the selection signal input to the second level shifter is raised to 25 V, the 25 V selection signal is input to the gate signal line, and the pixel TFT operates to supply an image signal to the liquid crystal. As a result, an image is displayed on the liquid crystal display.

As described above, in the present invention, by providing the level shifter circuit before and after the shift register circuit,
A clock signal having a voltage amplitude level that is low enough that the TFTs of the shift register circuit do not fail due to punch-through or hot electrons due to the short channel effect and high enough to operate a TFT having a manufacturable channel length can be input to the shift register circuit. it can. As a result, the shift register circuit can operate at higher speed, and power consumption can be suppressed. Further, even if the voltage amplitude level of the clock signal input from the outside of the gate signal line side driving circuit is made as low as possible within the range in which the operation of the level shifter circuit is possible, high speed operation of the shift register circuit becomes possible. Power consumption and unnecessary radiation can be suppressed to a level that does not cause a problem. In the present embodiment, an example in which the present invention is applied to the gate signal line side driving circuit has been described. However, the present invention is not limited to this embodiment.

(Embodiment 6) The present invention may be applied to both the source signal line side drive circuit and the gate signal line side drive circuit. In this case, the first and second level shifter circuits are used for the source signal line side drive circuit and the gate signal line side drive circuit, respectively. For example, the above embodiments may be combined.

(Embodiment 7) In this embodiment, the manufacturing process of the active matrix type liquid crystal display device of the above-described Embodiments 1 to 6 will be described.

This embodiment shows an example in which a plurality of top gate type TFTs are formed on a substrate having an insulating surface, and a pixel matrix circuit and an operation circuit including a level shifter circuit and a shift register circuit are monolithically constructed. FIG.
Shown in In this embodiment, a CMOS circuit which is a basic circuit is shown as an example of a driving circuit such as a driving circuit or a logic circuit. In this embodiment, the P-channel type and the N-channel type each have one gate electrode.
Although a manufacturing process of the circuit is described, a CMOS circuit including a plurality of gate electrodes such as a double gate type can be manufactured in a similar manner.

Referring to FIG. First, a glass substrate 601 is prepared as a substrate having an insulating surface. Instead of a glass substrate, a quartz substrate or a silicon substrate on which a thermal oxide film is formed can be used. Alternatively, a method may be employed in which an amorphous silicon film is formed once on a quartz substrate and then completely thermally oxidized to form an insulating film. Further, a quartz substrate, a ceramics substrate, or a silicon substrate on which a silicon nitride film is formed as an insulating film may be used. In this embodiment, a base film made of a silicon oxide film 602 is
It was formed to a thickness of 00 nm. As the base film, a silicon nitride film may be stacked, or only a silicon nitride film may be used.

Reference numeral 603 denotes an amorphous silicon film having a final film thickness (thickness in consideration of film reduction after thermal oxidation) of 10 to 75 n.
m (preferably 15 to 45 nm).
It is important to thoroughly control the impurity concentration in the film when forming the film.

In this embodiment, typical impurities in the amorphous silicon film 603 are C (carbon), N (nitrogen),
The concentration of O (oxygen) and S (sulfur) is 5 × 10 ¹⁸ a
less than toms / cm ³ (preferably 1 × 10 ¹⁸ atom
s / cm ³ or less). If each impurity concentration is higher than this, it will have an adverse effect on crystallization and may cause deterioration of the film quality after crystallization.

Note that the hydrogen concentration in the amorphous silicon film 603 is also a very important parameter, and a film with good crystallinity can be obtained by keeping the hydrogen content low. for that reason,
The amorphous silicon film 603 is preferably formed by a low pressure thermal CVD method. Note that the plasma CVD method can be used by optimizing the film formation conditions.

Next, a crystallization step of the amorphous silicon film 603 is performed. As a means for crystallization, a technique described in JP-A-7-130652 is used. In this embodiment, it is preferable to use the technical content (detailed in JP-A-8-78329) described in Example 2 of the same publication, although either means of Embodiment 1 or Embodiment 2 of the publication may be used. .

The technique described in Japanese Patent Application Laid-Open No. 8-78329 discloses a technique in which a mask insulating film 6 for selecting a region to which a catalyst element is added is first used.
04 is formed. The mask insulating film 604 has a plurality of openings for adding a catalyst element. The position of the crystal region can be determined by the position of the opening.

Then, a solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film 603 is applied by a spin coating method to form a Ni-containing layer 605. In addition, as a catalyst element, in addition to nickel, cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), or the like can be used (see FIG. B)).

In the step of adding the catalyst element, an ion implantation method using a resist mask or a plasma doping method can be used. In this case, the reduction of the occupied area of the addition region and the control of the growth distance of the lateral growth region are facilitated, so that this is an effective technique when configuring a miniaturized circuit.

Next, when the catalyst element addition step is completed,
After dehydrogenation at 450 ° C for about 1 hour, inert atmosphere,
500-70 in hydrogen atmosphere or oxygen atmosphere
4-24 at a temperature of 0 ° C. (typically 550-650 ° C.)
The amorphous silicon film 603 is crystallized by applying heat treatment for a long time. In this embodiment, heat treatment is performed at 570 ° C. for 14 hours in a nitrogen atmosphere.

At this time, the crystallization of the amorphous silicon film 603 proceeds preferentially from the nuclei generated in the nickel-added regions 606 and 606, and grows substantially parallel to the substrate surface of the glass substrate 601. A region 607 is formed. This crystal region 607 is called a lateral growth region. Since the individual crystals are gathered in the lateral growth region in a relatively uniform state, there is an advantage that the overall crystallinity is excellent (FIG. 12).
(C)).

When the technique described in the first embodiment of Japanese Patent Application Laid-Open No. Hei 7-130652 is used, a region which can be microscopically called a lateral growth region is formed. However, since nucleation occurs unevenly in the plane, there is a difficulty in controllability of crystal grain boundaries.

Next, phosphorus is doped in this state to remove nickel in the film. Then, only the region 606 to which nickel is added is doped with phosphorus. These regions are referred to as phosphorus added regions 608. At this time, the doping acceleration voltage and the mask insulating film 604 made of an oxide film are used.
The thickness is optimized so that phosphorus does not substantially penetrate the mask insulating film 604. (FIG. 12 (D))

The dose of phosphorus is from 1 × 10 ¹⁴ to 1 × 1
It is preferably about 0 ¹⁵ ions / cm ² . In this embodiment, 5 × 1
A dose of 0 ¹⁴ ions / cm ² was performed using an ion doping apparatus.

The acceleration voltage during ion doping is 10
kv. For an accelerating voltage of 10 kv, phosphorus is 10
Almost cannot pass through the insulating film mask of 00 °.

Next, reference will be made to FIG. afterwards,
Thermal annealing was performed in a nitrogen atmosphere at 600 ° C. for 1 to 12 hours (12 hours in this embodiment) to perform nickel element gettering. The heating causes nickel to be attracted to the phosphorus. At a temperature of 600 ° C., phosphorus atoms hardly move in the film, while nickel atoms are several hundred μm.
It can move about or more distances. From this, it can be understood that phosphorus is one of the most suitable elements for gettering nickel.

After the heat treatment for crystallization is completed, the mask insulating film 604 is removed and patterning is performed, and the island-like semiconductor layers (active layers) 609 and 6 formed of the lateral growth regions 607 are formed.
10 and 611 are formed (FIG. 13A).

Here, reference numeral 609 denotes N constituting a CMOS circuit.
610 is an active layer of a type TFT, and 610 is a P
An active layer 611 of the type TFT is an active layer of an N-type TFT (pixel TFT) constituting a pixel matrix circuit.

After forming the active layers 609, 610, and 611, a gate insulating film 612 made of an insulating film containing silicon is formed thereon.

Next, a not-shown metal film containing aluminum as a main component is formed, and a prototype of a gate electrode to be formed later is formed by patterning. In this embodiment, an aluminum film containing 2 wt% of scandium is used.

Next, the porous anodic oxide films 613 to 620, the nonporous anodic oxide films 621 to 624, and the gate electrode 62 are formed by the technique described in JP-A-7-135318.
5 to 628 are formed (FIG. 13B).

After the state shown in FIG. 13B is obtained, the gate insulating film 61 is next formed using the gate electrodes 625 to 628 and the porous anodic oxide films 613 to 620 as a mask.
2 is etched. Then, the porous anodic oxide film 61
13 to 620 are removed to obtain the state shown in FIG. Note that reference numerals 629 to 632 in FIG. 13C denote the processed gate insulating films.

Referring to FIG. Next, a step of adding an impurity element imparting one conductivity is performed. As an impurity element, P (phosphorus) or As (arsenic) for N-channel type, B (boron) or Ga (gallium) for P-type
May be used. In this embodiment, the impurity addition for forming the N-channel and P-channel TFTs is performed in two steps.

First, an impurity is added for forming an N-channel type TFT. First, the first impurity addition (in this embodiment, P (phosphorus) is used) is performed at a high acceleration voltage of 80 ke
This is performed at about V to form an n ⁻ region. This n ^- region is
P ion concentration is 1 × 10 ¹⁸ ions / cm ² -1 × 10
¹⁹ ions / cm ² Adjust in this way.

Further, the second impurity addition is performed at a low acceleration voltage of about 10 keV to form an n ⁺ region. At this time,
Since the acceleration voltage is low, the gate insulating film functions as a mask. The n ⁺ region is adjusted so that the sheet resistance is 500Ω or less (preferably 300Ω or less).

Through the above steps, the source and drain regions 633 and 634 of the n-channel TFT constituting the CMOS circuit, the low concentration impurity region (LDD region)
637, a channel formation region 640 is formed. Also,
Source and drain regions 635 and 636, low-concentration impurity regions (LDD regions) 638 and 639, and channel formation regions 641 and 642 of the n-channel TFT constituting the pixel TFT are determined (FIG. 14A).

Note that, in the state shown in FIG.
The active layer of the p-channel TFT forming the S circuit has the same configuration as the active layer of the n-channel TFT.

Next, as shown in FIG. 14B, a resist mask 643 is provided to cover the n-channel type TFT,
An impurity ion for imparting a mold (boron is used in this embodiment) is added.

This step is also performed in two steps, similarly to the above-described impurity addition step. However, since it is necessary to invert the N-channel type to the P-channel type, the concentration is several times the P-ion addition concentration. B (boron) ion is added.

Thus, the source and drain regions 644 and 645 of the p-channel TFT constituting the CMOS circuit, the low concentration impurity region (LDD region) 646, and the channel formation region 647 are formed (FIG. 14B).

In this embodiment, the gate electrode is formed using an aluminum film containing 2 wt% of scandium. However, the gate electrode may be formed using a polycrystalline silicon film. In this case, the LDD region is formed using a sidewall such as SiO ² or SiN.

Next, impurity ions are activated by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer caused by the addition process is repaired.

Referring to FIG. Next, a stacked film of a silicon oxide film and a silicon nitride film is formed as the first interlayer insulating film 648, contact holes are formed, and source and drain electrodes 649 to 653 are formed. Get the state shown. Note that an organic resin film can also be used as the first interlayer insulating film 648.

When the state shown in FIG. 14C is obtained, the second interlayer insulating film 654 made of an organic resin film is
It is formed to a thickness of μm (FIG. 15A). As the organic resin film, polyimide, acrylic, polyimide amide or the like is used. The advantages of the organic resin film are that the film formation method is simple, the film thickness can be easily increased, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. . Note that an organic resin film other than those described above can be used.

Next, a part of the second interlayer insulating film 654 is removed, and a black matrix 655 made of a film having a light-shielding property is formed.
To form In this embodiment, the black matrix 655 is used.
Is used to form a storage capacitor 658 between the drain electrode 653 of the pixel TFT and the black matrix 655. Further, as the black matrix 655, a resin film or the like containing a black pigment can be used.

Next, a third interlayer insulating film 656 made of an organic resin film is formed to a thickness of 0.5 to 3 μm. As the organic resin film, polyimide, acrylic, polyimide amide or the like is used. Note that an organic resin film other than those described above can be used.

Then, contact holes are formed in the second interlayer insulating film 654 and the third interlayer insulating film 656, and a transparent pixel electrode 657 is formed to a thickness of 120 nm. Since this embodiment is an example of a transmission type active matrix liquid crystal display device, a transparent conductive film such as ITO is used as a conductive film forming the transparent pixel electrode 657.

Next, the entire substrate is heated in a hydrogen atmosphere at 350 ° C. for 1 to 2 hours, and hydrogenation of the entire device is performed, whereby dangling bonds (unpaired bonds) in the film (especially in the active layer) are formed.
To compensate. Through the above steps, a CMOS circuit and a pixel matrix circuit can be manufactured over the same substrate.

Next, a process for manufacturing an active matrix type liquid crystal display device based on the active matrix substrate manufactured by the above process will be described.

An alignment film 659 is formed on the active matrix substrate in the state shown in FIG. In this embodiment, polyimide is used for the alignment film 659. Next, a counter substrate is prepared. The opposing substrate is a glass substrate 660, an opposing electrode 6
61 and an alignment film 662.

In this embodiment, the alignment film 662 includes
A polyimide film was used. After the formation of the alignment film, a rubbing treatment was performed. In this embodiment, polyimide having a relatively small pre-tilt angle is used.

Next, the active matrix substrate and the counter substrate having undergone the above-described steps are subjected to a well-known cell assembling step.
They are attached via a sealing material or a spacer (both not shown). Thereafter, a liquid crystal 663 is injected between the two substrates, and completely sealed with a sealing agent (not shown). In this embodiment, a nematic liquid crystal is used as the liquid crystal 663.

Thus, a transmission type active matrix liquid crystal display device as shown in FIG. 15C is completed.

(Embodiment 8) In this embodiment, an example will be described in which the active matrix liquid crystal display devices of Embodiments 1 to 6 described above are manufactured in a process different from that of Embodiment 7.

Referring to FIG. First, the glass substrate 50
A base film made of a silicon oxide film 5002 is
It was formed to a thickness of nm. As the base film, a silicon nitride film may be stacked, or only a silicon nitride film may be used.

Next, 30n is formed on the silicon oxide film 5002.
An amorphous silicon film (amorphous silicon film) having a thickness of m was formed by a plasma CVD method, and after dehydrogenation treatment, excimer laser annealing was performed to form a polysilicon film (a crystalline silicon film or a polycrystalline silicon film).

For this crystallization step, a known laser crystallization technique or thermal crystallization technique may be used. In this embodiment, the amorphous silicon film is crystallized by processing a pulse oscillation type KrF excimer laser into a linear shape.

In this embodiment, a polysilicon film is obtained by crystallizing the initial film as an amorphous silicon film by laser annealing, but a microcrystalline silicon film may be used as the initial film, or the polysilicon film may be formed directly. It may be a film. Of course, laser annealing may be performed on the formed polysilicon film. Further, furnace annealing may be performed instead of laser annealing.

The crystalline silicon film thus formed is patterned to form an active layer 500 made of an island-like silicon layer.
3,5004 were formed.

Then, a gate insulating film 5005 made of a silicon oxide film is formed to cover the active layers 5003 and 5004,
Gate wirings (including gate electrodes) 5006 and 5007 each having a stacked structure of tantalum and tantalum nitride were formed thereon (FIG. 25A).

[0210] The thickness of the gate insulating film 5005 was 100 nm. Needless to say, a stacked structure of a silicon oxide film and a silicon nitride film or a silicon oxynitride film may be used instead of the silicon oxide film. Further, other metals can be used for the gate wirings 5006 and 5007, but a material having a high etching selectivity with silicon in a later step is preferable.

When the state shown in FIG. 25A was obtained, a first phosphorus doping step (a step of adding phosphorus) was performed. In this case, the acceleration voltage is set to be as high as 80 KeV because of the addition through the gate insulating film 5005. The first impurity regions 5008 and 5009 thus formed have a length (width) of 0.5 μm and a phosphorus concentration of 1 × 10 ¹⁷ atoms / cm ^3.
The dose was adjusted so that The phosphorus concentration at this time is represented by (n-). Note that arsenic could be used instead of phosphorus.

The first impurity regions 5008 and 5009
Were formed in a self-aligned manner using the gate wirings 5006 and 5007 as a mask. At this time, the gate wires 5006, 50
07, an intrinsic crystalline silicon layer remains, and channel formation regions 5010 and 5011 are formed. However,
Actually, there is a part that is added around the inside of the gate wiring, so that the gate wirings 5006 and 5007 overlap with the first impurity regions 5008 and 5009 (FIG. 25B). ).

Next, 0.1-1 μm (typically 0.2-0.
An amorphous silicon layer having a thickness of 3 μm) is formed, and anisotropic etching is performed to thereby form sidewalls 5012, 5.
013 was formed. Side walls 5012, 5013
(Thickness viewed from the side wall of the gate wiring) was 0.2 μm (FIG. 25C).

In this embodiment, since an amorphous silicon layer to which no impurity is added is used, a sidewall made of an intrinsic silicon layer is formed.

When the state shown in FIG. 25C was obtained, a second phosphorus doping step was performed. Also in this case, the acceleration voltage was set to 80 KeV as in the first time. Also, the second formed this time
Phosphorus is 1 × 10 ¹⁸ at in the impurity regions 5014 and 5015.
The dose was adjusted to be contained at a concentration of oms / cm ³ .
The phosphorus concentration at this time is represented by (n).

In the phosphorus doping step shown in FIG. 25D, first impurity regions 5008 and 5009 remain only under sidewalls 5012 and 5013. These first impurity regions 5008 and 5009 function as 1st LDD regions.

In the step of FIG. 25D, phosphorus was also added to the side walls 5012 and 5013. Actually, phosphorus was distributed in such a state that the tail of the phosphorus concentration profile extended to the inside of the sidewall due to the high acceleration voltage. Although the resistance component of the sidewall can be adjusted by phosphorus, if the concentration distribution of phosphorus varies extremely, the gate voltage applied to the second impurity region 5014 may be a factor that varies for each element. Requires precise control.

Next, a resist mask 5016 covering part of the n-channel TFT and a resist mask 5017 covering all of the p-channel TFT were formed. Then, in this state, a gate insulating film 5018 processed by dry etching the gate insulating film 5005 is formed (FIG. 25).
(E)).

At this time, the length of the portion where the gate insulating film 5018 protrudes outside the sidewall 5012 (the length of the portion where the gate insulating film 5018 is in contact with the second impurity region 5014) is the second impurity. The length (width) of the region 5014 was determined. Therefore, the resist mask 5016
It was necessary to perform mask alignment with high accuracy.

When the state shown in FIG. 25E was obtained, a third phosphorus doping step was performed. In this case, since the phosphorus is added to the exposed active layer, the acceleration voltage is set to be as low as 10 KeV. The dose was adjusted so that the third impurity region 5019 thus formed contained phosphorus at a concentration of 5 × 10 ²⁰ atoms / cm ³ . The phosphorus concentration at this time is represented by (n +) (FIG. 26A).

In this step, since phosphorus is not added to portions shielded by resist masks 5016 and 5017, second impurity regions 5014 and 5015 remain in those portions. Therefore, the second impurity region 50
14 are defined. At the same time, the third impurity region 5019
Is defined.

This second impurity region 5014 has a 2nd LDD
The third impurity region 5019 functions as a source region or a drain region.

Next, the resist masks 5016 and 5017
Was removed, and a resist mask 5021 newly covering the entire n-channel TFT was formed. Then, first, the sidewall 5013 of the p-channel TFT was removed, and the gate insulating film 5005 was dry-etched to form a gate insulating film 5022 having the same shape as the gate wiring 5007 (FIG. 26B).

When the state shown in FIG. 26B was obtained, a boron doping step (boron adding step) was performed. Here, the acceleration voltage is set to 10 KeV, and the formed fourth impurity region 50 is formed.
The dose was adjusted so that 23 contained boron at a concentration of 3 × 10 ²⁰ atoms / cm ³ . The boron concentration at this time is (p
++) (FIG. 26C).

At this time, boron is also added around the inside of the gate wiring 5007 and is added.
11 is formed inside the gate wiring 5007. Also,
In this step, the first impurity region 5009 and the second impurity region 5015 formed on the side of the p-channel TFT are inverted to be P-type by boron. Accordingly, although the resistance value actually changes between the portion that was originally the first impurity region and the portion that was the second impurity region, it does not pose a problem because boron is added at a sufficiently high concentration.

Thus, the fourth impurity region 5023 is defined. The fourth impurity region 5023 is a gate wiring 500
7 is formed in a completely self-aligned manner by using as a mask, and functions as a source region or a drain region. In this embodiment, p
Neither the LDD region nor the offset region is formed for the channel type TFT. However, there is no problem since the p-channel type TFT is originally high in reliability, and on-state current can be increased by not providing the LDD region. In some cases it is convenient.

As a result, as shown in FIG. 26C, a channel formation region, a first impurity region, a second impurity region, and a third impurity region are finally formed in the active layer of the n-channel TFT. Only the channel forming region and the fourth impurity region are formed in the active layer of the channel type TFT.

When the state shown in FIG. 26C was obtained, the first interlayer insulating film 5024 was formed to a thickness of 1 μm. As the first interlayer insulating film 5024, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, an acrylic resin film is employed.

After forming the first interlayer insulating film 5024, source wirings 5025 and 5026 and a drain wiring 5027 made of a metal material were formed. In this embodiment, a three-layer wiring having a structure in which an aluminum film containing titanium is sandwiched between titanium is used.

Further, as the first interlayer insulating film 5024, BC
When a resin film called B (benzocyclobutene) is used, flatness is improved and copper can be used as a wiring material. Copper is very effective as a wiring material because of its low wiring resistance.

After forming the source wiring and the drain wiring in this way, a 50 nm thick silicon nitride film 5028 was formed as a passivation film. Further thereon, a second interlayer insulating film 5029 was formed as a protective film. As the second interlayer insulating film 5029, the first interlayer insulating film 5024 is used.
It is possible to use the same material as described above. In this embodiment, a structure in which an acrylic resin film is laminated on a silicon oxide film having a thickness of 50 nm is employed.

Through the above steps, a CMOS circuit having a structure as shown in FIG. 26D is completed. The CMOS circuit formed by this embodiment is an n-channel TFT
Has excellent reliability, so that the reliability of the entire circuit is significantly improved. Further, with the structure as in the present embodiment, the characteristic balance (balance of electric characteristics) between the n-channel TFT and the p-channel TFT becomes excellent.

[0233] Similarly, the pixel TFT can also be constituted by an n-channel TFT.

When the state shown in FIG. 26D is obtained, a contact hole is opened and a pixel electrode connected to the drain electrode of the pixel TFT is formed. Then, a third interlayer film is formed, and an alignment film is formed. Further, a black matrix may be formed as needed.

Next, a counter substrate is prepared. The counter substrate is
It is composed of a glass substrate, a counter electrode made of a transparent conductive film, and an alignment film.

In this example, a polyimide film was used as the alignment film. After the formation of the alignment film, a rubbing treatment was performed. In this example, polyimide having a relatively large pre-tilt angle was used for the alignment film.

Next, the active matrix substrate and the counter substrate having undergone the above-described steps are subjected to a known cell assembling step to perform
Laminate via a sealing material or spacer. Thereafter, a liquid crystal is injected between the two substrates and completely sealed with a sealant. In this embodiment, a nematic liquid crystal is used as the liquid crystal.

Thus, a transmission type active matrix type liquid crystal display device is completed.

(Embodiment 9)

In this embodiment, an example is described in which the crystalline semiconductor film to be an active layer in Embodiments 7 and 8 is formed by a thermal crystallization method using a catalytic element. In the case of using a catalyst element, Japanese Patent Application Laid-Open Nos. 7-130652 and 8
It is preferable to use the technique described in -78329.

FIG. 27 shows an example in which the technique disclosed in JP-A-7-130652 is applied to the present invention. First, a silicon oxide film 6002 is provided on a silicon substrate 6001 by a thermal oxidation method, and an amorphous silicon film 6 is formed thereon.
003 was formed. Further, a nickel acetate salt solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 6004 (FIG. 27A).

Next, after the hydrogenation step at 500 ° C. for 1 hour, the temperature is set at 500 to 650 ° C. for 4 to 12 hours.
Heat treatment at 50 ° C. for 8 hours) to form a polysilicon film 600.
5 was formed. The polysilicon film 600 thus obtained
No. 5 had very excellent crystallinity (FIG. 27 (B)).

Thereafter, the polysilicon film 6005 was patterned to form an active layer, and a TFT was manufactured through the same steps as in Examples 7 and 8.

In the above two technologies, besides nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (C
o), elements such as platinum (Pt), copper (Cu), and gold (Au) may be used.

(Embodiment 10) In this embodiment, an example of a manufacturing method different from the active matrix type liquid crystal display device described in Embodiment 8 will be described.

Referring to FIG. 28 and FIG. First, as the substrate 7001, an alkali-free glass substrate typified by, for example, a 1737 glass substrate manufactured by Corning Incorporated was used. Then, a base film 7002 made of silicon oxide was formed with a thickness of 200 nm on the surface of the substrate 7001 where the TFT was formed. As the base film 7002, a silicon nitride film may be further stacked, or a silicon nitride film alone may be used.

Next, a 50 nm film is formed on the underlayer 7002.
An amorphous silicon film was formed by the plasma CVD method so as to have a thickness. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable to carry out dehydrogenation treatment by heating to 400 to 500 ° C. to reduce the amount of hydrogen contained in the amorphous silicon film to 5 atm% or less and to carry out the crystallization step. This was performed to obtain a crystalline silicon film.

For this crystallization step, a known laser crystallization technique or thermal crystallization technique may be used. In this embodiment, a pulse oscillation type KrF excimer laser beam is condensed linearly and applied to an amorphous silicon film to form a crystalline silicon film. In this embodiment, a polysilicon film is obtained by crystallizing the initial film as an amorphous silicon film by laser annealing, but a microcrystalline silicon film may be used as the initial film, or a polysilicon film may be formed directly. Is also good. Of course, laser annealing may be performed on the formed polysilicon film. Further, furnace annealing may be performed instead of laser annealing. Further, the method described in the ninth embodiment may be used.

The crystalline silicon film thus formed is patterned to form island-like semiconductor layers 7003, 7004, and 70.
05 was formed.

Next, the semiconductor layers 7003, 7004, 70
05, a gate insulating film 7006 containing silicon oxide or silicon nitride as a main component was formed. Here, plasma C
A silicon nitride oxide film was formed to a thickness of 100 nm by a VD method. Although not described in FIG. 28, the gate insulating film 7
The first gate electrode is formed on the surface of 006. Tantalum (Ta) is used as a first conductive film in a thickness of 10 to 200 nm, for example, 50 nm, and aluminum (A) is used as a second conductive film.
1) was formed with a thickness of 100 to 1000 nm, for example, 200 nm by a sputtering method. Then, first conductive films 7007, 7008, 7009, and 7010 constituting the first gate electrode and 7012, 7013, 7014, and 7015 of the second conductive film were formed by a known patterning technique.

When aluminum is used as the second conductive film forming the first gate electrode, pure aluminum may be used, or an element selected from titanium, silicon, and scandium may be 0.1 to 5 atm. % Added aluminum alloy may be used. In the case of using copper, although not shown, a silicon nitride film is preferably provided on the surface of the gate insulating film 7006.

FIG. 28 shows a structure in which an additional capacitance section is provided on the drain side of the n-channel TFT forming the pixel matrix circuit. At this time, the wiring electrodes 7011 and 7016 of the additional capacitance portion are made of the same material as the first gate electrode.
Is formed.

After the structure shown in FIG. 28A is formed, a first step of adding an n-type impurity is performed.
As an impurity element that imparts n-type to the crystalline semiconductor material, phosphorus (P), arsenic (As), antimony (S
b) and the like are known, but here, the ion doping method using phosphorous and phosphine (PH ₃ ) was used. In this step, the accelerating voltage is set to 80 because phosphorus is added through the gate insulating film 7006 to the semiconductor layer thereunder.
KeV was set higher. The impurity regions formed in this manner form first impurity regions 7034 and 7042 of an n-channel TFT described later, and function as LDD regions. Therefore, the concentration of phosphorus in this region is preferably set in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atms / cm ³ , and here, it is set to 1 × 10 ¹⁸ atms / cm ³ .

The impurity element added to the semiconductor layer had to be activated by laser annealing or heat treatment. This step may be performed after the step of adding impurities for forming the source / drain regions, but activation at this stage by the laser annealing method was effective.

In this step, the first conductive films 7007, 7008, 7009, 7010 forming the first gate electrode
And second conductive films 7012, 7013, 7014, 701
5 served as a mask for the addition of phosphorus. As a result, no or almost no phosphorus was added to the region immediately below the first gate electrode of the semiconductor layer existing via the gate insulating film. Then, as shown in FIG. 28B, low-concentration impurity regions 7017, 70
18, 7019, 7020, 7021, 7022, 70
23 were formed.

Next, using the photoresist film as a mask, n
A region for forming a channel type TFT is formed by a resist mask 70.
The step of adding an impurity for imparting p-type was performed only on the region where the p-channel TFT was formed, which was covered with 24 and 7025. As an impurity element imparting p-type, boron (B), aluminum (Al), and gallium (Ga) are known. Here, boron is used as the impurity element, and diborane (B ₂ H) is ion-doped. ₆ ). Here, the acceleration voltage is set to 80 keV and 2 × 10
Boron was added to a concentration of ²⁰ atms / cm ³ . And FIG.
As shown in (C), the region 7 where boron is added at a high concentration
026 and 7027 were formed. This region will later be the source / drain region of the p-channel TFT.

Then, resist masks 7024 and 702
After removing No. 5, a step of forming a second gate electrode was performed. Here, tantalum (Ta) is used as the material of the second gate electrode, and the thickness is 100 to 1000 nm, for example, 200 nm.
It was formed to a thickness of nm. Then, patterning is performed by a known technique, and second gate electrodes 7028 and 702 are formed.
9, 7030, 7031 were formed. At this time, patterning was performed so that the length of the second gate electrode was 5 μm. As a result, in the second gate electrode, regions were formed on both sides of the first gate electrode, each having a length of 1.5 μm and in contact with the gate insulating film.

A storage capacitor is provided on the drain side of the n-channel TFT forming the pixel matrix circuit. The electrode 7028 of this storage capacitor was formed simultaneously with the second gate electrode.

Then, the second gate electrodes 7025 and 7025
26, 7027 are used as a mask to give a second n-type
A step of adding an impurity element is performed. Here as well
And phosphine (PH_Three) Using ion doping method
went. Also in this step, through the gate insulating film 7006
To add phosphorus to the underlying semiconductor layer, the accelerating voltage is
It was set as high as 80 keV. And here is the phosphorus
The added region is a source region 70 of an n-channel TFT.
32, 7042, and drain regions 7033, 7043
In this case, the concentration of phosphorus in this region is 1 ×
10¹⁹~ 1 × 10 ^{twenty one}atms / cm^ThreePreferably, here
Then 1 × 10²⁰atms / cm^ThreeAnd

Although not shown here, source regions 7035 and 7043 and drain regions 7036 and 7036
The gate insulating film covering 47 may be removed to expose the semiconductor layer in that region, and phosphorus may be directly added. By adding this step, the acceleration voltage of the ion doping method could be reduced to 10 keV, and phosphorus could be added efficiently.

The source region 7 of the p-channel TFT is
Phosphorus is added to the drain region 7039 and the drain region 7040 at the same concentration. However, since boron is added at twice the concentration in the previous step, the conductivity type is not inverted, and the p-channel TF
There was no problem in the operation of T.

N-type or p-type added at each concentration
Since the impurity element imparting the mold does not activate as it is and does not work effectively, it is necessary to perform an activation step. This step includes a thermal annealing method using an electric heating furnace,
The laser annealing using an excimer laser and the rapid thermal annealing (RTA) using a halogen lamp can be performed.

In the thermal annealing method, activation was performed by heating at 550 ° C. for 2 hours in a nitrogen atmosphere. In the present embodiment, aluminum is used for the second conductive film constituting the first gate electrode.
Since the conductive film of No. 2 and the gate electrode of the large 2 are formed to cover aluminum, the tantalum functions as a blocking layer and aluminum atoms can be prevented from diffusing into other regions. In the laser annealing method, activation was performed by condensing and irradiating a pulsed KrF excimer laser beam in a linear manner. Further, when the thermal annealing method was performed after the laser annealing method, even better results were obtained. This step also has the effect of annealing the region where the crystallinity has been destroyed by the ion doping, and has improved the crystallinity of the region.

In the above steps, the gate electrode is provided with the first gate electrode, and the second gate electrode is provided so as to cover the first gate electrode. In the case of the n-channel type TFT, both sides of the second gate electrode are provided. Then, a source region and a drain region were formed. Further, a structure in which a first impurity region provided in a semiconductor layer with a gate insulating film interposed therebetween and a region where a second gate electrode is in contact with the gate insulating film is formed in a self-aligned manner is provided. Was done. On the other hand, in a p-channel TFT,
Although the source region and the drain region partially overlap with the second gate electrode, there was no problem in practical use.

When the state shown in FIG. 28D was obtained, a first interlayer insulating film 7049 was formed to a thickness of 1000 nm.
As the first interlayer insulating film 7049, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, although not shown, a two-layer structure in which a silicon nitride film is first formed to a thickness of 50 nm and a silicon oxide film is further formed to a thickness of 950 nm.

Thereafter, the first interlayer insulating film 7049 was patterned to form contact holes in the source region and the drain region of each TFT. Then, the source electrodes 7050, 7052, 7053 and the drain electrode 70
51, 7054 were formed. Although not shown, in the present embodiment, this electrode is formed by patterning a three-layer structure film in which a titanium film is continuously formed by a sputtering method with a titanium film of 100 nm, a titanium-containing aluminum film of 300 nm, and a titanium film of 150 nm. .

As shown in FIG. 28E, a CMOS circuit and an active matrix circuit were formed over the substrate 7001. Further, n of the active matrix circuit
On the drain side of the channel type TFT, an additional capacitance portion was simultaneously formed. As described above, an active matrix substrate was manufactured.

Next, a process for manufacturing an active matrix type liquid crystal display device based on the CMOS circuit manufactured on the same substrate and the active matrix circuit by the above process will be described with reference to FIG. First, FIG.
With respect to the substrate in the state of FIG.
052, 7053 and drain electrodes 7051, 7054
Then, a passivation film 7055 was formed to cover the first interlayer insulating film 7045. Passivation film 7055
Was formed with a thickness of 50 nm using a silicon nitride film. further,
The second interlayer insulating film 7056 made of an organic resin is
It was formed to a thickness of 0 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film forming method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can also be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

Next, a light-shielding layer 7057 was formed in part of the pixel region of the second interlayer insulating film 7056. Light shielding layer 705
7 may be formed of a metal film or an organic resin film containing a pigment. Here, titanium was formed by a sputtering method.

After the formation of the light shielding film 7057, a third interlayer insulating film 7058 is formed. This third interlayer insulating film 70
58 is preferably formed using an organic resin film, like the second interlayer insulating film 7056. Then, a contact hole reaching the drain electrode 7054 was formed in the second interlayer insulating film 7056 and the third interlayer insulating film 7058, and a pixel electrode 7059 was formed. The pixel electrode 7059 may be formed using a transparent conductive film in the case of a transmissive liquid crystal display device, or a metal film in the case of a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method, so that a pixel electrode 7055 was formed.

When the state shown in FIG. 29A is formed, an alignment film 7060 is formed. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. Opposite substrate 7
At 071, a counter electrode 7072 and an alignment film 7073 were formed. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were parallel-aligned with a certain pretilt angle.

Through the above steps, the substrate on which the active matrix circuit, the CMOS circuit is formed, and the counter substrate are bonded together by a well-known cell assembling step via a sealing material or a spacer (both not shown). afterwards,
A liquid crystal material (nematic liquid crystal) 7074 was injected between both substrates, and completely sealed with a sealant (not shown).
Thus, an active matrix liquid crystal display device shown in FIG. 29B was completed.

(Embodiment 11) In Embodiments 1 to 10, the nematic liquid crystal is used, but a ferroelectric liquid crystal may be used. This embodiment is not limited to a liquid crystal material. Further, the driving circuit of the present invention can be used for a semiconductor display device using any material whose optical parameter changes depending on voltage.

(Embodiment 12) In Embodiments 7 and 8, a top gate type thin film transistor has been described, but a bottom gate type thin film transistor may be used in the present invention.

[0275] (Example 13) Although the active layer in Example 7, 8 TFT Si is used, a thin film transistor used for the semiconductor display device of the present invention, Ge, Si _x G
A semiconductor film having e _1-x may be used.

(Embodiment 14) Electronic devices using a semiconductor display device (typically, a liquid crystal display device) manufactured according to the present invention have various uses. Example 1 In this example, an electronic device incorporating a semiconductor display device using a driver circuit manufactured according to the present invention will be described.

[0277] Such electronic devices include a video camera,
Still cameras, projectors, head mounted displays, car navigation systems, personal computers,
Personal digital assistants (mobile computers, mobile phones, etc.)
And the like. Examples of these are shown in FIGS.

FIG. 16A shows a mobile phone,
01, an audio output unit 1102, an audio input unit 1103, a semiconductor display device 1104, operation switches 1105, and an antenna 1106.

FIG. 16B shows a video camera, which includes a main body 1107, a semiconductor display device 1108, and an audio input unit 110.
9, an operation switch 1110, a battery 1111 and an image receiving unit 1112.

FIG. 16C shows a mobile computer, which includes a main body 1113, a camera section 1114, and an image receiving section 111.
5, an operation switch 1116, and a semiconductor display device 1117.

FIG. 16D shows a head-mounted display, which includes a main body 1118, a semiconductor display device 1119, a mirror 1120, and a backlight 1121.

FIG. 16E shows a head-mounted display, which includes a semiconductor display device 1123 and a band portion 1124.
It consists of. The head mounted display shown in FIG. 16E is provided with only one semiconductor display device.

FIG. 17A shows a rear type projector, 1201 is a main body, 1202 is a semiconductor display device, and 12
03 is a light source, 1204 is an optical system, and 1205 is a screen. In addition, it is preferable that the angle of the screen of the rear type projector can be changed while the main body is fixed depending on the viewing position of the viewer. Note that by using three semiconductor display devices 1202 (corresponding to R, G, and B lights, respectively), a rear-type projector with higher resolution and higher definition can be realized.

FIG. 17B shows a front type projector, in which a main body 1206, a semiconductor display device 1207, a light source 1
208, a reflector 1209, and a screen 1210. Note that by using three semiconductor display devices 1207 (corresponding to R, G, and B lights, respectively), a front projector with higher resolution and higher definition can be realized.

(Embodiment 15) This embodiment is an example in which the present invention is applied to a source signal line side driving circuit of a digital drive type active matrix type liquid crystal display device. FIG.
FIG. 1 is a block diagram showing an example of a source signal line side driving circuit of a digital driving system according to the present embodiment.

[0286] The source signal line side driving circuit of the digital driving method of this embodiment includes a first level shifter circuit, a third level shifter circuit, a shift register circuit, and a latch circuit (1).
(First latch circuit), latch circuit (2) (second latch circuit), second level shifter circuit, and D / A conversion circuit are provided in the order shown in FIG.

FIG. 31 shows an example of a specific circuit diagram of the digital drive type source signal line side drive circuit shown in FIG. Here, an active matrix type liquid crystal display device in the case of a 4-bit digital driving method is taken as an example.

A first level shifter circuit 3100, a shift register circuit 3101, address lines (a to d) 3102 of a digital decoder, and a latch circuit (1) (LAT1) 3
103, a latch circuit (2) (LAT2) 3104, a latch pulse line 3105, a D / A conversion circuit 3106, a gradation voltage line 3107, a source signal line 3108, a second level shifter circuit 3109, and a third level shifter circuit 3110. It is arranged as shown at 31. In the latch circuits (LAT1 and LAT2), four latch circuits are collectively shown for convenience. In addition, a level shifter circuit for increasing the voltage amplitude level of the clock signal and a level shifter circuit for increasing the voltage amplitude level of the start pulse signal are grouped together for the sake of convenience, and are shown as a first level shifter circuit 3100.

A clock signal (CLK) is input to the first level shifter circuit 3100 from outside the source signal line side driving circuit. The voltage amplitude level of the clock signal is required to be as low as possible within a range in which the first level shifter circuit 3100 can be driven, in order to suppress unnecessary radiation to a degree that does not cause a problem. It is also necessary to suppress power consumption.

[0290] The clock signal input to first level shifter circuit 3100 is raised in voltage and output. At this time, the voltage amplitude level of the clock signal is such that the TFT of the shift register circuit 3101 does not fail due to punch-through due to the short channel effect or hot electrons.
In addition, it is necessary to increase the voltage to a voltage amplitude level at which a TFT having a channel length that can be manufactured operates.

The clock signal whose voltage amplitude level has been increased by the first level shifter circuit 3100 is input to the shift register circuit 3101. A start pulse signal whose voltage amplitude level has been increased by the first level shifter circuit 3100 is input to the shift register circuit 3101 through the wiring shown in FIG. Based on the clock signal input to the shift register circuit 3101, the shift register circuit 3101 determines the timing at which the shift register circuit 3101 writes a digital signal to the latch circuit (1) 3103 by the start pulse signal (SP) input to the shift register circuit 3101. An operation for generating a timing signal to be performed is started.

Address lines (ad) of the digital decoder
Digital signal (digital gradation signal) via 3102
Is input to the third level shifter circuit 3110. The input digital signal is converted to a higher voltage and output.
At this time, the voltage amplitude level of the digital signal is high enough that the TFT of the shift register circuit 3101 does not fail due to punch-through or hot electrons due to the short channel effect and that the TFT having a manufacturable channel length operates. It is necessary to increase the voltage. The high-voltage output digital signal is sequentially written to the latch circuit (1) 3103 by a timing signal generated by the shift register circuit 3101. The most significant bit (MSB) of the digital signal is inputted from the address line 3102a of the digital decoder, and the least significant bit (LSB) of the digital signal is inputted from the address line 3102b of the digital decoder.
B) is input.

After the writing of the digital signal to the latch circuit (1) 3103 is completed, the latch circuit (1) 31
The digital signal written to 03 is sent to the latch circuit (2) 3104 at the same time when a latch pulse flows through the latch pulse line 3105 in accordance with the operation timing of the shift register circuit 3101, and is written.

A digital signal is latched by a latch circuit (2) 3104.
In the latch circuit (1) 3103 which has finished sending the digital signals, the digital signals supplied to the digital decoder are sequentially written again by the signal from the shift register circuit 3101.

During the second one-line period, the latch circuit (2) 31 is synchronized with the start of the second one-line period.
A digital signal having a voltage amplitude level corresponding to the digital signal transmitted to the second level shifter circuit 04 is input to the second level shifter circuit 3104.

The digital signal input to the second level shifter circuit 3109 is raised in voltage. At this time, it is necessary to increase the voltage of the digital signal to a voltage amplitude level provided with a certain margin voltage.

This margin voltage is applied to the D / A conversion circuit 310.
6 is for converting a digital signal input to 6 into an analog signal. The magnitude of the margin voltage depends on the voltage of the largest analog signal output from the D / A conversion circuit 3106.

The digital signal whose voltage has been increased by the second level shifter circuit 3109 is
6 is converted into an analog signal, and the analog signal is supplied to the corresponding source signal line 3108 for one line period. The switching of the corresponding pixel TFT is performed by the selection signal from the shift register circuit of the gate signal line side driving circuit, and the liquid crystal molecules are driven.

By repeating the above operation by the number of scanning lines, one screen (one frame) is formed. Generally, in an active matrix type liquid crystal display device, 1
Rewriting of an image of 60 frames per second is performed.

As described above, in the present invention, the level shifter circuit is provided before and after the shift register circuit in the digital drive type source signal line side drive circuit,
A clock signal with a voltage amplitude level that is low enough that the TFTs of the shift register circuit do not fail due to punch-through or hot electrons due to the short channel effect and high enough to operate a TFT having a manufacturable channel length is input to the shift register circuit. Can be. As a result, the shift register circuit can operate at higher speed.

Further, even if the voltage amplitude level of the clock signal input from the outside of the source signal line side drive circuit of the digital drive system is made as low as possible within the range in which the operation of the level shifter circuit is possible, the high speed operation of the shift register circuit Since operation becomes possible, power consumption and unnecessary radiation can be suppressed to a level that does not cause a problem.

The frequency of the digital signal is several tens of MHz.
Since the frequency is higher than the frequency of the image signal of the analog driving circuit, unnecessary radiation has been a problem. Therefore, it has been desired to lower the voltage of the digital signal. However, if the voltage level of the digital signal is lower than the gradation voltage, it becomes difficult to convert the digital signal into an analog signal by the D / A conversion circuit. According to the present invention, the voltage amplitude level of a digital signal input to the latch circuit from the outside of the source signal line side driving circuit of the digital driving method can be made as low as possible within the range where the level shifter circuit can operate. Therefore, the voltage of a digital signal input to the latch circuit can be suppressed, and unnecessary radiation and power consumption can be suppressed.

In this embodiment, an example in which the present invention is applied to a source signal line side driving circuit of a digital circuit has been described. However, the present invention is not limited to this embodiment, and a gate signal line side driving circuit of a digital circuit is used. It may be used for both the source signal line side drive circuit and the gate signal line side drive circuit of the digital circuit. (Example 16)

In the liquid crystal display device of the present invention described above, various liquid crystals can be used in addition to the nematic liquid crystal. For example, 1998, SID, "Characteristics and Drivin
g Scheme of Polymer-Stabilized Monostable FLCD Exh
ibiting Fast Response Time and High Contrast Ratio
with Gray-Scale Capability "by H. Furue et al.
And 1997, SID DIGEST, 841, "A Full-Color Threshold
less Antiferroelectric LCD Exhibiting Wide Viewing
Angle with Fast Response Time "by T. Yoshidaet a
l., 1996, J. Mater. Chem. 6 (4), 671-673, "Thresh
oldless antiferroelectricity in liquid crystals an
d its application to displays "by S. Inui et al.
Alternatively, the liquid crystal disclosed in U.S. Pat. No. 5,594,569 can be used.

Ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 33 shows the electro-optical characteristics of a monostable FLC in which a cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage, and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 33 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 33 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Tsuki, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 19, No. 19
See page 0 for details.

As shown in FIG. 33, it can be seen that the use of such a ferroelectric mixed liquid crystal enables low-voltage driving and gradation display. The liquid crystal display device of the present invention includes:
A ferroelectric liquid crystal having such electro-optical characteristics can also be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low-voltage driving can be realized, so that low power consumption can be realized.

(Embodiment 17) In this embodiment, an example in which an EL (electroluminescence) display device having the structure of the present invention will be described.

FIG. 34A is a top view of an EL display device using the present invention. In FIG. 34A, 4010
Denotes a substrate, 4011 denotes a pixel matrix portion, 4012 denotes a source signal line side driving circuit, 4013 denotes a gate signal line side driving circuit, and each driving circuit has wirings 4014 to 401.
6 to the FPC 4017, which is connected to an external device.

At this time, at least the pixel matrix portion,
Preferably, a cover material 6000, a sealing material (also referred to as a housing material) 7000, and a sealing material (a second sealing material) 70 surround the driving circuit and the pixel matrix portion.
01 is provided.

FIG. 34B shows a cross-sectional structure of the EL display device of this embodiment.
A TFT for a driving circuit (here, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined is illustrated) 4022 and a TFT for a pixel matrix portion (pixel TFT) 4023 (here, Only the TFT for controlling the current to the EL element is shown). These TFTs may use a known structure (top gate structure or bottom gate structure).

In the present invention, 4012 can be used for a source signal line side driving circuit or 4013 can be used for a gate signal line side driving circuit.

After the TFT 4022 for the drive circuit and the TFT 4023 for the pixel matrix portion are formed by a known method, the TFT 4022 for the pixel matrix portion is electrically connected to the drain region of the TFT 4023 for the pixel matrix portion on an interlayer insulating film (flattening film) 4026 made of a resin material. A pixel electrode 4027 made of a transparent conductive film is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

[0316] Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

[0317] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After the EL layer 4029 is formed, a cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 4030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

The cathode 40 in the region indicated by 4031
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Further, the sealing material 7000 and the sealing material 7 are placed inside the substrate 4010 so as to surround the EL element portion.
000 is provided, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0324] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

In this embodiment, after the filler 6004 is provided, the cover 6000 is adhered, and the sealing material 7000 is attached so as to cover the side surface (exposed surface) of the filler 6004. Lumber 70
After attaching 00, the filler 6004 may be provided. In this case, an injection port for a filler is provided to communicate with a space formed by the substrate 4010, the cover material 6000, and the sealing material 7000. Then, the gap is vacuumed (10
^-2 Torr or less), immerse the injection port in the water tank containing the filler, and then fill the gap with the filler by setting the pressure outside the gap higher than the pressure inside the gap.

(Embodiment 18) In this embodiment, an example of manufacturing an EL display device different from that of Embodiment 17 using the present invention will be described with reference to FIGS. 35 (A) and 35 (B). . 34 (A) and 34 (B) denote the same parts, and a description thereof will not be repeated.

FIG. 35A is a top view of the EL display device of this embodiment, and FIG. 35B is a cross-sectional view taken along line AA ′ of FIG. 35A.

In accordance with the seventeenth embodiment, a passivation film 6003 is formed to cover the surface of the EL element.

[0333] Further, the filling material 6 was formed so as to cover the EL element.
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0334] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light transmitting property.

[0338] Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of a sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

In this embodiment, the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filler material 6004 after the filler material 6004 is provided and then the cover material 6000 is bonded. Lumber 6001
And then the filler 6004 may be provided. In this case, an inlet for a filler is provided to communicate with a gap formed by the substrate 4010, the cover member 6000, and the frame member 6001. Then, the gap is evacuated (10 ^-2 Torr).
r), the filler is filled in the gap by immersing the injection port in the water tank containing the filler, and then making the pressure outside the gap higher than the pressure inside the gap.

[Embodiment 17] FIG. 35 shows a more detailed sectional structure of a pixel portion in an EL display panel, FIG. 36A shows a top view structure thereof, and FIG. 36B shows a circuit diagram thereof. In FIG. 35, FIG. 36 (A) and FIG. 36 (B), a common reference numeral is used, so that they may be referred to each other.

In FIG. 35, as a switching TFT 3502 provided on a substrate 3501, an n-channel TFT formed by a known method is used. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. In addition, p formed by a known method
It may be formed using a channel type TFT.

As the current control TFT 3503, an n-channel TFT formed by a known method is used. The source wiring 34 of the switching TFT 3502 and the drain wiring 35 of the switching TFT 3502 are electrically connected to the gate electrode 37 of the current controlling TFT by a wiring 36. The wiring indicated by 38 is the gate electrodes 39a and 39b of the switching TFT 3502.
Are electrically connected to each other.

Since the current control TFT 3503 is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the current control TF
A structure in which an LDD region is provided on the drain side of T3503 so as to overlap a gate electrode with a gate insulating film interposed therebetween is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 36A, the wiring 36 serving as the gate electrode 37 of the current control TFT 3503 is located in the region 3504 in the current control TFT 3503.
Overlap with the drain wiring 40 via the insulating film. At this time, a capacitor is formed in a region indicated by 3504. The storage capacitor 3503 is formed between the semiconductor film 3520 electrically connected to the power supply line 3506, an insulating film (not shown) in the same layer as the gate insulating film, and the wiring 36. Further, a capacitor formed by the wiring 36, the same layer (not shown) as the first interlayer insulating film, and the power supply line 3506 can be used as a storage capacitor. This capacitor 3
Reference numeral 504 functions as a capacitor for holding a voltage applied to the gate electrode 37 of the current controlling TFT 3503. The drain of the current controlling TFT is connected to a power supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a highly reflective conductive film.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). FIG. 36
In (A), some banks are omitted in order to clarify the position of the storage capacitor 3504, and only the banks 44a and 44b are shown.
Power supply line 3506 and source wiring 3 so as to partially cover
4 are provided. Although only two pixels are shown here, light-emitting layers corresponding to R (red), G (green), and B (blue) colors may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Representative polymer-based materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PV
K) type, polyfluorene type and the like.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylene vinylene is used for a red light emitting layer, polyphenylene vinylene is used for a green light emitting layer, and polyphenylene vinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
This is an EL layer having a laminated structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, so that the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In this embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 35, and a switching TFT having a sufficiently low off-current value and a current control device which is resistant to hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of this embodiment is similar to that of Embodiments 1 to 18
Can be freely combined with the above configuration.

(Embodiment 20) In this embodiment, Embodiment 19 will be described.
In the pixel matrix portion shown in FIG.
A structure obtained by inverting the structure described above will be described. FIG. 38 is used for the description. It should be noted that the point different from the structure of FIG. 36 is only the EL element portion and the current controlling TFT, and the other description is omitted.

In FIG. 38, the current controlling TFT 350
3 is a p-channel TFT manufactured by using a known method.
It is. As a manufacturing process, a known method can be used.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

The structure of this embodiment is similar to those of Embodiments 1 to 18.
Can be freely combined with the above configuration.

(Embodiment 21) In this embodiment, FIG.
FIGS. 39A to 39C show examples in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, reference numeral 3801 denotes a switching TFT 380.
2 is a source signal line, 3803 is a switching TFT 3
A gate signal line 802, a current control TFT 3804,
3805 is a capacitor, 3806 and 3808 are power supply lines, and 3807 is an EL element.

FIG. 39A shows an example in which a power supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the power supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel matrix portion can have higher definition.

FIG. 39B shows a power supply line 380.
8 is provided in parallel with the gate signal line 3803. Note that FIG. 39B illustrates a structure in which the power supply line 3808 and the gate signal line 3803 are provided so as not to overlap with each other. It can also be provided so as to overlap.
In this case, the power supply line 3808 and the gate signal line 3803
Since the occupied area can be shared with the pixel matrix portion, the pixel matrix portion can be further refined.

FIG. 39C shows a power supply line 3808 connected to a gate signal line 3803 as in the structure of FIG. 39B.
And two pixels are connected to the power supply line 380
It is characterized in that it is formed so as to be line-symmetric with respect to 8. Further, the power supply line 3808 is connected to the gate signal line 3803.
It is also effective to provide any one of them. In this case, the number of power supply lines can be reduced, so that the pixel matrix portion can have higher definition.

The structure of this embodiment is similar to that of Embodiments 1 to 18.
Can be freely combined with the above configuration.

(Embodiment 22) FIG. 37 shown in Embodiment 19
37A and 37B, a capacitor 35 for holding a voltage applied to the gate electrode of the current controlling TFT 3503 is used.
04 is provided, but the capacitor 3504 can be omitted. In the case of the nineteenth embodiment, since an n-channel TFT is used as the current control TFT 3503, an LDD region provided so as to overlap the gate electrode with a gate insulating film interposed therebetween is provided. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, the capacitance is determined by the length of the LDD region included in the overlapping region.

Further, FIG. 39 (A) and FIG.
Similarly, in the structures (B) and (C), the capacitor 3
It is possible to omit 805.

The structure of this embodiment is similar to those of Embodiments 1 to 21.
Can be freely combined with the above configuration.

Embodiment 23 A semiconductor display device using a semiconductor display device (active matrix liquid crystal display, active matrix EL display, active matrix EC display) manufactured according to the present invention has various uses. Example 1 In this example, electronic devices incorporating a semiconductor display device using a driver circuit manufactured according to the present invention will be described.

As such electronic equipment, a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), game machine, car navigation, personal computer, portable information terminal (mobile computer) , A mobile phone or an electronic book).
One example of them is shown in FIG.

FIG. 32A shows a personal computer, which includes a main body 7001, a video input section 7002, and a display device 7.
003 and a keyboard 7004. The present invention can be applied to the video input unit 7002, the semiconductor display device 7003, and other signal control circuits.

[0377] FIG. 32B shows a video camera, which includes a main body 7101, a semiconductor display device 7102, and an audio input portion 710.
3, an operation switch 7104, a battery 7105, and an image receiving unit 7106. Semiconductor display device 7 according to the present invention
102, the audio input unit 7103, and other signal control circuits.

FIG. 32C shows a mobile computer (mobile computer), which includes a main body 7201, a camera portion 7202, an image receiving portion 7203, operation switches 7204, and a semiconductor display device 7205. The present invention can be applied to the semiconductor display device 7205 and other signal control circuits.

FIG. 32D shows a goggle type display, which includes a main body 7301, a semiconductor display device 7302, and an arm portion 7303. The present invention is a semiconductor display device 7
302 and other signal control circuits.

FIG. 32E shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 7401, a semiconductor display device 7402, a speaker portion 7403, a recording medium 7404, and operation switches 7405.
It consists of. This device uses a DVD as a recording medium.
(Digital Versatile Disc),
Using a CD or the like, music viewing, movie viewing, games, and the Internet can be performed. The present invention can be applied to the semiconductor display device 7402 and other signal control circuits.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the semiconductor display device of the present embodiment corresponds to the first to first embodiments.
3, 15 to 16 can be realized by using any combination of the configurations.

[0382]

According to the present invention, the TFTs of the shift register circuit are provided with a level shifter circuit before and after the shift register circuit. The shift register circuit can be operated with a clock signal having a voltage amplitude level sufficient to operate the shift register circuit. As a result, the shift register circuit can be operated at high speed without failure, and the liquid crystal can be driven to a saturated state. Further, even if the voltage amplitude level of the clock signal input from the outside of the source signal line side driving circuit is made as low as possible within the range in which the operation of the level shifter circuit is possible, high speed operation of the shift register circuit becomes possible. Power consumption and unnecessary radiation can be suppressed to a level that does not cause a problem.

[0383]

[Brief description of the drawings]

FIG. 1 is a block diagram of a source signal line side driving circuit of the present invention.

FIG. 2 is a circuit diagram of a source signal line side driving circuit of the present invention.

FIG. 3 is a schematic diagram of an active matrix display device.

FIG. 4 is a block diagram of a source signal line side driving circuit of the present invention.

FIG. 5 is a circuit diagram of a source signal line side driving circuit of the present invention.

FIG. 6 is a timing chart of a source signal line side driving circuit of the present invention.

FIG. 7 is a block diagram of a source signal line side driving circuit of the present invention.

FIG. 8 is a block diagram of a source signal line side driving circuit of the present invention.

FIG. 9 is a block diagram of a gate signal line side driving circuit of the present invention.

FIG. 10 is a circuit diagram of a gate signal line side driving circuit of the present invention.

FIG. 11 is a block diagram of a gate signal line side driving circuit of the present invention.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 15 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 16 is a configuration diagram of an electronic device using the present invention.

FIG. 17 is a configuration diagram of an electronic device using the present invention.

FIG. 18 is a schematic view of an active matrix display device.

FIG. 19 is a block diagram of a conventional source signal line side driving circuit.

FIG. 20 is an equivalent circuit diagram of a level shifter circuit.

FIG. 21 is a circuit diagram of a source signal line side driving circuit of a conventional example.

FIG. 22 is a circuit diagram of a source signal line side driving circuit of a conventional example.

FIG. 23 is a circuit diagram of a source signal line side driving circuit of a conventional example.

FIG. 24 is a block diagram of a conventional source signal line side driving circuit.

FIG. 25 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 26 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 27 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 28 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 29 is a cross-sectional view illustrating a manufacturing process of a TFT.

FIG. 30 is a block diagram of a digital drive type source signal line side drive circuit of the present invention.

FIG. 31 is a circuit diagram of a digital drive type source signal line side driving circuit of the present invention.

FIG. 32 is a configuration diagram of an electronic device using the present invention.

FIG. 33 is a graph showing electro-optical characteristics of a monostable FLC.

34A and 34B are a top view and a cross-sectional view of an EL display device using the present invention.

35A and 35B are a top view and a cross-sectional view of an EL display device using the present invention.

FIG. 36 is a cross-sectional view of a pixel matrix portion of an EL display device using the present invention.

FIG. 37 is a top view and a circuit diagram of a pixel matrix portion of an EL display device using the present invention.

FIG. 38 is a cross-sectional view of a pixel matrix portion of an EL display device using the present invention.

FIG. 39 is a circuit diagram of a pixel matrix portion of an EL display device using the present invention.

[Explanation of symbols]

 201 first level shifter circuit 202 shift register circuit 203 second level shifter circuit 204 sampling circuit 205 analog switch 206 image signal line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) G09F 9/30 338 G09G 3/36 G09G 3/36 G02F 1/136 500 H01L 29/786 H01L 29/78 612B

Claims (17)

[Claims] 1. A source signal line side driving circuit having a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit, wherein the first level shifter circuit is connected to the source signal line side. An input signal input from the outside of the drive circuit to the first level shifter circuit is raised to a voltage amplitude level at which the shift register circuit can operate, and input to the shift register circuit. The shift register circuit includes: A timing signal for sampling an image signal supplied from outside of the source signal line side driving circuit is generated based on the input signal, and the generated timing signal is generated by the second level shifter circuit. The second level shifter circuit further raises the voltage amplitude level of the input timing signal to a higher level. The sampling signal is input to the sampling circuit, and the sampling circuit samples the image signal according to the input timing signal, and supplies the image signal to a source signal line connected to the source signal line side driving circuit. Source signal line side driving circuit. 2. A source signal line side driving circuit having a first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit, wherein the first level shifter circuit is connected to the source signal line side. A clock signal having a voltage amplitude level that is operable by the first level shifter circuit and that is input to the first level shifter circuit from outside the driving circuit is raised to a voltage amplitude level at which the shift register circuit is operable. , Input to the shift register circuit, and the shift register circuit samples an image signal supplied from outside the source signal line side driving circuit based on the clock signal input to the shift register circuit. And inputting the generated timing signal to the second level shifter circuit The second level shifter circuit increases the voltage amplitude level of the timing signal input to the second level shifter circuit to a voltage amplitude level provided with a certain margin voltage in the saturation voltage of the liquid crystal, and performs the sampling. The sampling circuit inputs the image signal according to the timing signal input to the sampling circuit, and supplies the image signal to a source signal line connected to the source signal line side driving circuit. Source signal line side drive circuit. 3. A gate signal line side drive circuit having a first level shifter circuit, a second level shifter circuit, and a shift register circuit, wherein the first level shifter circuit is external to the gate signal line side drive circuit. The input signal input from is input to the shift register circuit after raising the voltage to a voltage amplitude level at which the shift register circuit can operate, and the shift register circuit inputs the input signal input to the shift register circuit. A selection signal is generated based on the selected signal, and the generated selection signal is input to the second level shifter circuit. The second level shifter circuit determines a voltage amplitude level of the input selection signal by a gate signal. Voltage to a voltage amplitude level at which all pixel TFTs connected to the line can be reliably operated, and a high voltage is applied to the gate signal line. The gate signal line side driving circuit and supplying directly or via the buffer circuit said selection signal. 4. A gate signal line side drive circuit having a first level shifter circuit, a second level shifter circuit, and a shift register circuit, wherein the first level shifter circuit is provided outside the gate signal line side drive circuit. A clock signal having a voltage amplitude level operable by the first level shifter circuit, which is input to the first level shifter circuit from, is increased to a voltage amplitude level operable by the shift register circuit, and the shift register The shift register circuit receives the clock signal input to the shift register circuit, and the pixel T connected to a gate signal line side driving circuit via a gate signal line based on the clock signal input to the shift register circuit.
A selection signal for operating the FT is generated, and the generated selection signal is input to the second level shifter circuit. The second level shifter circuit outputs a voltage of the selection signal input to the second level shifter circuit. The amplitude level,
All the pixels TF connected to the gate signal line
A gate signal line side, wherein the voltage is increased to a voltage amplitude level at which T can be operated reliably, and the selection signal whose voltage is increased by the second level shifter circuit is supplied to the gate signal line. Drive circuit. 5. An active matrix circuit in which a plurality of pixel TFTs are arranged in a matrix;
A plurality of source signal lines connected to respective source electrodes of T; a plurality of gate signal lines connected to respective gate electrodes of the plurality of pixel TFTs; and a source signal connected to the plurality of source signal lines. A semiconductor display device having a line side drive circuit and a gate signal line side drive circuit connected to the plurality of gate signal lines, wherein the source signal line side drive circuit has a first level shifter circuit and a second level shifter circuit , A shift register circuit, and a sampling circuit, wherein the first level shifter circuit is a first level shifter that is input to the first level shifter circuit from outside the source signal line side drive circuit. A clock signal having a voltage amplitude level at which the circuit can operate is raised to a voltage amplitude level at which the shift register circuit can operate, and A timing signal for sampling an image signal supplied from outside the source signal line side driving circuit based on the clock signal input to the shift register circuit; And the generated timing signal is input to the second level shifter circuit. The second level shifter circuit converts the voltage amplitude level of the timing signal input to the second level shifter circuit into The voltage is increased to a voltage amplitude level provided with a certain margin voltage at the saturation voltage and input to the sampling circuit.The sampling circuit samples the image signal by the timing signal input to the sampling circuit, A semiconductor display device for supplying to a source signal line. 6. The semiconductor display device according to claim 5, wherein said source signal line side drive circuit is formed on the same substrate as said active matrix circuit. 7. An active matrix circuit in which a plurality of pixel TFTs are arranged in a matrix;
A plurality of source signal lines connected to respective source electrodes of T; a plurality of gate signal lines connected to respective gate electrodes of the plurality of pixel TFTs; and a source signal connected to the plurality of source signal lines. A semiconductor display device having a line side drive circuit and a gate signal line side drive circuit connected to the plurality of gate signal lines, wherein the gate signal line side drive circuit includes a first level shifter circuit and a second level shifter circuit And a shift register circuit, wherein the first level shifter circuit is operable with the first level shifter circuit, which is input to the first level shifter circuit from outside the gate signal line side drive circuit. A clock signal having a high voltage amplitude level to a voltage amplitude level at which the shift register circuit can operate, and input to the shift register circuit. The shift register circuit is configured to operate the pixel TFT connected to the gate signal line side driving circuit via the gate signal line based on the clock signal input to the shift register circuit. And the generated selection signal is input to the second level shifter circuit. The second level shifter circuit converts the voltage amplitude level of the timing signal input to the second level shifter circuit into the gate signal The voltage is increased to a voltage amplitude level at which all of the pixel TFTs connected to the line can be reliably operated, and a selection signal whose voltage is increased by the second level shifter circuit is supplied to the gate signal line. A semiconductor display device characterized by the above-mentioned. 8. The semiconductor display device according to claim 7, wherein said gate signal line side drive circuit is formed on the same substrate as said active matrix circuit. 9. An active matrix circuit in which a plurality of pixel TFTs are arranged in a matrix; a plurality of source signal lines connected to respective source electrodes of the plurality of pixel TFTs; A semiconductor having a plurality of gate signal lines connected to a gate electrode, a source signal line side driving circuit connected to the plurality of source signal lines, and a gate signal line side driving circuit connected to the plurality of gate signal lines In the display device, the source signal line side driving circuit has a first level shifter circuit, a second level shifter circuit, a first shift register circuit, and a first sampling circuit, and the first level shifter circuit is A voltage amplitude level input to the first level shifter circuit from outside the source signal line side driving circuit and capable of operating the first level shifter circuit. The clock signal of Le, and high voltage the first shift register circuit to possible voltage amplitude levels operation, the first
Input to a shift register circuit, wherein the first shift register circuit samples an image signal supplied from outside the source signal line side driving circuit based on the clock signal input to the first shift register circuit. The second level shifter circuit generates a timing signal for performing the above operation, and the second level shifter circuit converts the voltage amplitude level of the timing signal input to the second level shifter circuit into a liquid crystal display. The voltage is increased to a voltage amplitude level provided with a certain margin voltage at the saturation voltage of the first sampling circuit, and the voltage is input to the first sampling circuit. An image signal is sampled, supplied to the source signal line, and driven by the gate signal line. The path includes a third level shifter circuit, a fourth level shifter circuit, and a second shift register circuit. The third level shifter circuit inputs the third level shifter circuit from outside the gate signal line side drive circuit. The voltage of the clock signal having the voltage amplitude level operable by the third level shifter circuit is increased to a voltage amplitude level operable by the second shift register circuit.
The second shift register circuit is connected to the gate signal line side driving circuit via the gate signal line based on the clock signal input to the second shift register circuit. Generating a selection signal for operating the pixel TFT, and inputting the generated selection signal to the fourth level shifter circuit, wherein the fourth level shifter circuit outputs the timing signal input to the fourth level shifter circuit. Is increased to a voltage amplitude level at which all the pixel TFTs connected to the gate signal line can be reliably operated, and a high voltage is applied to the gate signal line by the fourth level shifter circuit. A semiconductor display device for supplying a simplified selection signal. 10. The semiconductor display device according to claim 9, wherein said source signal line side drive circuit and said gate signal line side drive circuit are formed on the same substrate as said active matrix circuit. 11. A first level shifter circuit, a second level shifter circuit, a third level shifter circuit, a first latch circuit, a second latch circuit, a shift register circuit, and a D / A conversion circuit. Wherein the first level shifter circuit is capable of operating the shift register circuit with an input signal input to the first level shifter circuit from outside the drive circuit. A voltage is increased to a voltage amplitude level and input to the shift register circuit. The shift register circuit converts a digital signal supplied from the outside of the drive circuit to the first signal based on the input signal. A timing signal for determining a timing of writing to the latch circuit is generated and input to the first latch circuit, and the digital signal is output to the third latch circuit. A digital signal input to the shifter circuit and output from the third level shifter circuit is input to the first latch circuit at a timing determined by a timing signal, and a digital signal input to the first latch circuit is provided. After performing a logical performance, the second latch circuit performs the performance and outputs the digital signal. The output digital signal is input to the D / A conversion circuit via the second level shifter circuit, A driving circuit for a semiconductor display device, which is converted. 12. A pixel matrix portion and a driving circuit are provided on a substrate, wherein the driving circuit has a source signal line side driving circuit and a gate signal line side driving circuit, and the source signal line side driving circuit is , A first level shifter circuit, a second level shifter circuit, a shift register circuit, and a sampling circuit. The first level shifter circuit receives the first level shifter circuit from outside the source signal line side drive circuit. The input signal input to the level shifter circuit is increased to a voltage amplitude level at which the shift register circuit can operate, and is input to the shift register circuit.The shift register circuit also receives the input signal. Generating a timing signal for sampling an image signal supplied from outside of the source signal line side driving circuit; The second level shifter circuit, the second level shifter circuit further increases the voltage amplitude level of the input timing signal to a higher voltage and inputs the voltage amplitude level to the sampling circuit, and the sampling circuit The image signal is sampled by the input timing signal and supplied to a source signal line connected to the source signal line side driving circuit. The pixel matrix portion includes at least a first thin film transistor for current control. And a second thin film transistor for switching; the first thin film transistor has an island-shaped semiconductor on the substrate; the island-shaped semiconductor has a channel formation region; One impurity region, and at least a second impurity in contact with the second impurity region. There is a region, there is at least a third impurity region in contact with the second impurity region, there is a gate insulating film on the channel forming region, the first impurity region, the second impurity region, A gate electrode is provided on the channel formation region with the gate insulating film interposed therebetween. At least one conductive sidewall is provided on the first impurity region. A third impurity of the first thin film transistor is provided. A semiconductor display device comprising: a pixel electrode electrically connected to a region; a light-emitting layer on the pixel electrode; and an electrode on the light-emitting layer. 13. A pixel matrix portion and a drive circuit are provided on a substrate, wherein the drive circuit has a source signal line side drive circuit and a gate signal line side drive circuit, and wherein the gate signal line side drive circuit is , A first level shifter circuit, a second level shifter circuit, and a shift register circuit, wherein the first level shifter circuit receives an input signal input from outside the gate signal line side driving circuit, The shift register circuit raises the voltage to a operable voltage amplitude level and inputs the voltage to the shift register circuit.The shift register circuit outputs a selection signal based on the input signal input to the shift register circuit. And the generated selection signal is input to the second level shifter circuit. The second level shifter circuit generates a voltage amplitude level of the input selection signal. To a voltage amplitude level at which all of the pixel TFTs connected to a gate signal line can be reliably operated, and the high-voltage selection signal is directly supplied to the gate signal line or a buffer circuit. The pixel matrix portion has at least a first thin film transistor for current control and a second thin film transistor for switching, and the first thin film transistor has an island-shaped semiconductor on the substrate. Wherein the island-shaped semiconductor has a channel forming region, has at least a first impurity region in contact with the channel forming region, has at least a second impurity region in contact with the second impurity region, There is at least a third impurity region in contact with the second impurity region, wherein the channel forming region, the first impurity region, A gate insulating film on the impurity region, a gate electrode on the channel forming region with the gate insulating film interposed, and at least one conductive sidewall on the first impurity region. A pixel electrode electrically connected to a third impurity region of the first thin film transistor; a light emitting layer on the pixel electrode; and an electrode on the light emitting layer. apparatus. 14. The method according to claim 12, wherein
The semiconductor display device, wherein the light emitting layer is an EL layer. 15. The method according to claim 12, wherein:
3. The semiconductor display device according to item 1, wherein a drain region of the second thin film transistor is connected to a gate electrode of the first thin film transistor. 16. The method according to claim 12, wherein:
9. The semiconductor display device according to item 1, wherein the second thin film transistor has a multi-gate structure. 17. The method according to claim 12, wherein:
2. The semiconductor display device according to claim 1, wherein at least one of the pixel electrode and the electrode is transparent.