JP2009079301A - Reactive sputtering device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device for depositing a dielectric film having a very thin thickness, high evenness of film quality and a higher dielectric constant, in a MOSFET (metal oxide semiconductor field effect transistor) on a silicon substrate. <P>SOLUTION: The reactive sputtering device is provided with a wafer holder 11 on which a wafer 22 is arranged, a target 12 obliquely arranged above the wafer holder 11 deviating from its rotary shaft, and a gas introducing part 17 and exhausting port 16 respectively provided interposing the wafer holder 11 between them below the wafer holder 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an apparatus for depositing a high dielectric constant dielectric film, and particularly deposits a high dielectric constant dielectric film such as various oxide films or nitride films having a very thin and uniform thickness on a silicon layer on a substrate. The present invention relates to a reactive sputtering apparatus.

In fabricating MOSFET devices on a silicon substrate, it is very important for future semiconductor devices to deposit very thin films of dielectric materials with a dielectric constant much higher than for example SiO ₂ . Thin, higher dielectric constant dielectric films are used, for example, as gate insulating layers in MOSFETs. Specifically, high dielectric constant dielectric materials are expected to be used in two different applications. The first application is to replace the current widespread use of SiO ₂ , SiON, and Si ₃ N ₄ dielectric materials in CMOS transistor gate dielectrics. The second application is to make a capacitor with higher capacitance, especially for liquid crystal display panels.

  Currently, there are two basic techniques for depositing high dielectric constant dielectric materials. The first method is chemical vapor deposition (CVD) and the second method is physical vapor deposition (PVD).

  Even though there are many different techniques in depositing films by CVD methods, basically only two methods are widely applied in the industry.

  In the first technique, a chemical precursor, preferably a metal-organic composite, is decomposed by plasma or thermal energy and reacts with a suitable gas to produce a dielectric material having a higher dielectric constant than desired. This technique is usually called MO-CVD technique.

  In the second method, two chemical mediators are introduced to the substrate, which are introduced with alternating time breaks between each gas introduction. During the time break, the first introduced gas is exhausted except for molecules absorbed on the surface of the substrate. When the second mediator is introduced, it reacts with the first gas molecules absorbed on the surface to form a dielectric film. Then, the remaining excess gas is exhausted during the time break until the next gas input. This technique is called atomic layer deposition (ALD) technique.

  There are two basic requirements in depositing a high dielectric constant dielectric film on a silicon substrate as a gate insulator in CMOS applications. The first requirement is that the membrane must be very thin. For example, most future CMOS devices require films with a physical thickness of less than 3 nm. The second requirement is that the thickness of the film is, for example, smaller than 1% (1σ) and is very uniform. Since these films are very thin, even a slight non-uniformity can cause significant changes in electrical properties such as capacitance and leakage current. In connection with these two basic requirements, the shortcomings of the film deposition technique are discussed.

  As one of conventional techniques, there is Patent Document 1 that discloses a method of depositing a high dielectric oxide film directly on a silicon layer by using, for example, a reactive sputtering method or CVD. This method has been proposed for forming a high dielectric oxide film directly on a silicon layer without impairing the characteristics of the high dielectric constant oxide film such as a high dielectric or insulator. According to the conventional method described above, first, a high dielectric constant nitride film is formed on a silicon layer, and then the high dielectric constant nitride film is oxidized to become a high dielectric constant oxide film. Change.

JP-A-11-168096

  The subject of the present invention is as follows. When manufacturing a very thin dielectric film used as a gate insulating layer in a MOSFET on a silicon substrate, it is necessary to form a uniform dielectric film having a higher dielectric constant.

  An object of the present invention is to provide an apparatus for depositing a dielectric film having a very thin thickness, high film quality uniformity, and higher dielectric constant in a MOSFET on a silicon substrate.

The present invention includes a wafer holder in which a wafer is disposed and rotated at a predetermined rotational speed;
A cathode provided in an inclined position at an upper position off the rotation axis of the wafer holder, a target containing hafnium is attached, and a DC power can be input;
A gas introduction part for introducing nitrogen gas as a process gas, which is provided at a position below the rotation axis of the wafer holder and where the cathode is not located above;
An exhaust port provided below the wafer holder and on the opposite side of the gas introduction unit across the wafer holder;
It is a reactive sputtering apparatus characterized by including.

In accordance with the present invention, a new technique is provided in depositing a very thin and very uniform dielectric film by PVD and thermal annealing processes, where the film is not subject to plasma-induced damage. . According to this technique, it is possible to produce a high dielectric constant dielectric film having characteristics that EOT (equivalent oxide thickness) <1 nm and a leakage current is smaller than 10 ⁻¹ A / cm ^2. Indicated.

  In order to achieve the above object, a method for depositing a high dielectric constant dielectric film according to the present invention is configured as follows.

A method for depositing a high dielectric constant dielectric film on a doped silicon layer or a doped silicon compound layer of a substrate is a method in which a specific element (A) is nitrided to form a nitride film (A _x N _y ) on the silicon layer. The first step in which the specific element (A) and nitrogen (N) in the nitride film (A _x N _y ) have a predetermined ratio between x and y, and the nitride film is oxidized It includes a second step of forming a dielectric film (AON) that is oxidized and oxidized and nitrided in an atmosphere.

  In the above method, preferably, the specific element (A) is any element belonging to Group 3, Group 4, or Group 5 of the periodic table of elements.

In the above-described method, preferably, in the nitride film (A _x N _y ), the specific element (A) and nitrogen (N) have a relationship that y is smaller than the stoichiometric value.

  In the above-described method, preferably, the specific element (A) is hafnium (Hf).

In the above-described method, preferably, hafnium (Hf) and nitrogen (N) in the nitride film (Hf _x N _y ) have a relationship that 0 <y <1.5 and x is 1.

  In the above-described method, preferably, the oxidation process in the second step is performed by a thermal annealing process having a specific temperature included in a temperature range of 400 to 1000 ° C.

  In the above method, preferably a reactive sputtering method is used for film deposition.

In the above method, preferably, either a SiO ₂ layer, a SiN layer, or a SiON layer is first provided on the silicon layer, and then a high dielectric constant dielectric film (AON) is deposited.

In the above-described method, preferably, the flow rate of nitrogen gas (N ₂ ) supplied for the nitridation process in the first step is any value within the range of 1 to 15 sccm.

  Hereinafter, preferred embodiments will be described with reference to the accompanying drawings. Details of the present invention will be clarified through the description of the embodiment.

[Embodiment 1]
A first embodiment of the present invention will be described with reference to FIGS. As an example, a schematic configuration diagram of a PVD processing chamber 10 is shown in FIG. The method of depositing a high dielectric constant dielectric film according to the present invention is carried out to make a gate insulating layer on a silicon wafer for making a gate electrode for a MOSFET in the PVD processing chamber.

  First, the structure of the PVD processing chamber 10 will be described. The processing chamber 10 includes a wafer holder 11, a so-called cathode target 12 having a flat plate shape, a side wall 13, a top plate 14, a bottom plate 15, an exhaust port 16, and a gas introduction part 17. A typical material for the target 12 is preferably hafnium (Hf). The target 12 is fixed to the wall or the plate (13, 14) of the processing chamber 10 in an inclined posture via the insulating support plate 18. Target 12 is electrically isolated from the rest of processing chamber 10 by insulating support plate 18.

  On the upper side or side of the target 12, there is a magnet array 19 fixed to a rotatable support plate 20. The support plate 20 has a drive mechanism (not shown). Reference numeral 20a indicates a rotation axis. While the device is operating, the magnet array 19 is rotated by an electric motor included in the drive mechanism. The electric motor and rotation mechanism for the magnet array 19 is not shown in FIG.

  The target 12 described above is supplied with DC power for generating plasma from the DC power source 21. It is not essential to use DC power. Instead of DC power, rf (alternating current) power can also be used to generate plasma.

  The target 12 is preferably made of hafnium (Hf) having a purity of 99.99%. The target 12 is disposed at a preferred predetermined angle with respect to the wafer or substrate 22 disposed on the wafer holder 11. Again, the axis 11a of the wafer holder 11 and the axis 12a of the target 12 are not parallel but intersect at a predetermined angle (α). The two axes 11a and 12a are in the same plane. The angle (α) between these two axes 11a and 12a is less than 90 ° and is typically about 45 °.

  The wafer holder 11 is rotated at a rotational speed of about 60 rpm during film deposition on the wafer 22. The rotational speed is not critical and can be varied over a wide range, for example, 10-500 rpm. The rotation mechanism of the wafer holder is not shown in the figure.

  Next, a method or process for depositing a high dielectric constant dielectric film on the wafer 22 performed in the PVD processing chamber described above will be described in detail with reference to FIG.

The high dielectric constant dielectric film is formed on the surface of the wafer 22 of doped silicon (p-Si, n-Si) or doped silicon compound (doped SiGe. For example, p-SiGe, n-SiGe). The high dielectric constant dielectric film is used for the gate dielectric layer of the MOSFET in the CMOS device fabricated on the wafer 22. It is a very thin dielectric film with a higher dielectric constant that is larger than that of SiO ₂ .

Ar or N ₂ is introduced as a process gas into the processing chamber 10 via the gas introduction unit 17. The internal pressure of the processing chamber 10 is preferably maintained below 0.5 Pa. Sputtering is performed by applying DC power to the Hf target 12.

When sputtering is performed using the Hf target 12, a mixed gas of nitrogen (N ₂ ) / argon (Ar) is introduced into the processing chamber 10 in advance. Since N ₂ atoms are present in the PVD processing chamber 10, the sputtered atoms Hf react with nitrogen radicals / ions to form a film or layer of HfN (hafnium nitride) on the surface of the wafer 22. . The material on which the wafer 22 is based is silicon. The HfN film is formed on a doped silicon layer or SiGe.

  The procedure for forming a high dielectric constant dielectric film based on Hf proceeds as follows.

(1): The wafer (wafer 22 described above) is cleaned with a diluted Hf solution to remove the silicon oxide originally present (step S1).
(2): The wafer is dried (step S1).
(3): An HfN film is deposited on the wafer by a reactive sputtering technique (step S2).
(4): The wafer is annealed at a high temperature exceeding 400 ° C. in an environment where the oxygen content is approximately 1% and most of the oxygen is an inert gas or N ₂ (step S3).

Initially, the wafer is cleaned with a diluted HF solution to remove the originally present oxide and other contaminants on the wafer surface and dried (step S1). Second, an HfN film is deposited on the wafer surface by a reactive sputter deposition technique (step S2). The PVD processing chamber 10 described above for the deposition of HfN is used. Thirdly, the wafer undergoes thermal annealing at a higher temperature above 400 ° C. (step S3). The pressure at the time of the annealing is not an important matter and can be changed from a pressure of several Torr to an atmospheric pressure. The annealing gas environment is almost an inert gas or N ₂ gas, and contains about 1% oxygen. The annealing process oxidizes the HfN film and changes the HfN film to a HfON film as a high dielectric constant dielectric film.

In the above process of depositing or forming a high dielectric constant dielectric film, which is very thin and used as a gate dielectric, using the Hf target 12, hafnium (Hf) and nitrogen (N) in the nitride film (Hf _x N _y ) are There is a relationship of 0 <y <1.5 with respect to x = 1.

  After the film preparation described above, a TaN film is deposited on the HfN film as a gate electrode, patterned and etched to form a metal oxide semiconductor (MOS) capacitor on the wafer 22. The CV (capacitance / voltage) characteristics and IV (current / voltage) characteristics of these MOS capacitors were inspected, and equivalent oxide thickness (EOT) and leakage current were evaluated.

  According to the apparatus configuration described above, a very uniform film is formed on a wafer having a diameter of 200 mm or 300 mm. FIG. 3 shows the uniformity of the HfN film on a 200 mm wafer. FIG. 3A is a plan view of the wafer showing the thickness of the film, and FIG. 3B is a longitudinal view of the diameter line showing the standardized resistance value of the film. The thickness of the film was measured at 49 points dispersed and set over the entire surface of a circular surface area having a diameter of 180 mm, and the standard deviation (σ) was estimated as 0.95%. Standard deviation represents the non-uniformity of the membrane. In FIG. 3, reference numeral 23 indicates a contour line of uniformity, and reference numeral 24 indicates a characteristic line formed by resistance value data.

  4 and 5 show electrical data regarding the prepared hafnium oxynitride film (HfON) obtained by the procedure described above. These HfON films are deposited with the following process parameters and film parameters.

Pressure 0.019Pa
Ar gas flow rate 20sccm
N ₂ gas flow rate 6sccm
DC power 300W
Deposition rate 2.4 nm / min Deposition time 12.5 seconds HfN film thickness 0.5 nm
HfN film resistance 516μ / Ωcm
HfN film uniformity 0.95% (1σ)

4 and 5 show the CV and IV characteristics of the prepared film, respectively. In this case, the original thickness of the HfN film before thermal annealing is 0.5 nm. Thermal annealing is performed for 30 seconds at a temperature of 600 ° C. under atmospheric pressure with a mixed gas of N ₂ and O ₂ (˜1%). The deposited HfN has a low resistance value and exhibits metallic properties. The resistance characteristic of the HfN film varies depending on the nitrogen content of the film. FIG. 6 shows the change in HfN resistance characteristic as a function of the flow rate of nitrogen introduced into the processing chamber 10.

  As shown in FIGS. 4 and 5, after thermal annealing, the resulting film (HfON) exhibits dielectric properties. The resulting film is a high dielectric constant dielectric film with a very thin thickness. Therefore, during thermal annealing, the HfN film reacts with oxygen to satisfy the above conditions and form HfON (molecular nitrogen does not react with HfN at 600 ° C.).

Again, at the Si / HfN interface, Si reacts with oxygen coming through the HfON film to form a very thin SiO layer. At higher temperatures, Hf and Si are synthesized in the vicinity of the interface to form HfSiON. Accordingly, the resulting film includes HfON, HfSiON, and SiO. For the films shown in FIGS. 4 and 5, the estimated EOT and leakage currents are 0.95 nm and 0.03 A / cm ⁻² , respectively. The leakage current is estimated at -1.2 volts (V), which is from -0.2 volts Vfb (flat band voltage) to -1 volts lower.

  The degree of oxidation of Si and the degree of mixing of Si and Hf depend on the temperature and time of the anneal. Depending on the initial HfN thickness, optimal annealing temperatures and annealing times must be found to obtain the lowest EOT and / or lowest leakage current.

  During the film deposition process, the vertical distance between the center of the Hf target 12 and the wafer holder 11 is 300 mm. The plasma generated by the DC power is basically confined in the vicinity of the Hf target 12 by a strong magnetic field. Based on these two reasons, the plasma density on the wafer surface is negligibly small. Thus, film deposition using the above-described apparatus configuration can be considered as film formation by remote plasma. Because of these facts, the film deposited on the wafer 22 is not damaged by the plasma. This is further confirmed by CV and IV measurements where no evidence of plasma induced damage to the film is found.

As a variation of the first embodiment, other metals or metal nitrides can be used as the initial film in obtaining the gate dielectric instead of the above hafnium (Hf). Other metals are specific elements belonging to Group 3, 4, or 5 of the periodic table of elements. Some examples for specific elements are Zr, La, Ti, Ta, etc. When the specific element is generally indicated by the symbol “A”, the deposited nitride material is expressed as A _x N _y . In this case, the specific element (A) and nitrogen (N) in the nitride film (A _x N _y ) have a predetermined ratio relationship between x and y. Specifically, y is smaller than the stoichiometric value of the nitride film (A _x N _y ).

  Similarly, heavily doped polysilicon can be used as the metal gate. Furthermore, different metal / metal nitride combinations can be used as metal gates instead of one type of material. Depending on the type of metal gate material, the flat band voltage shifts and the work function of the metal gate of the fabricated MOS device changes.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. A feature of the second embodiment is a film preparation procedure. The film preparation procedure in the second embodiment is as follows.

(1): The wafer is cleaned in diluted HF solution to remove the original silicon oxide.
(2): Dry the wafer.
(3): Thermal annealing is performed at over 500 ° C. in NH ₃ gas atmosphere.
(4): HfN is deposited by reactive sputtering technique.
(5): Annealing the wafer at a higher temperature above 400 ° C. in an atmosphere of mostly inert gas or N ₂ containing about 1% oxygen.

In the second embodiment, only the initial wafer preparation before the formation of the HfN film is changed as compared with the first embodiment. As explained above, the wafer is subjected to thermal annealing in an NH ₃ gas atmosphere after cleaning with diluted HF solution and before deposition of HfN. During this annealing process, a thin layer of silicon nitride (SiN _x ) is formed on the wafer surface. Typically, the annealing time and annealing temperature are controlled to have a silicon nitride film with a thickness smaller than 1 nm. However, this is not an important requirement. This silicon nitride layer suppresses the diffusion of oxygen into the Si wafer 22 during subsequent film formation annealing. Diffusion of oxygen to the Si wafer 22 is responsible for the formation of SiO _2, thereby becoming a cause of the increase in EOT. Thus, the silicon nitride layer helps to minimize the EOT of the resulting film.

  Except for the additional steps described above, all other processing steps and the configuration of the processing system in the second embodiment are the same as those described in the first embodiment.

[Embodiment 3]
Next, a third embodiment of the present invention will be described. The feature of the third embodiment is also in the film preparation procedure. The film preparation procedure in the third embodiment is as follows. In the third embodiment, only the initial wafer preparation method is changed.

(1): The wafer is cleaned with a diluted HF solution to remove originally existing silicon oxide.
(2): Dry the wafer.
(3): Deposit a very thin layer of SiO ₂ or SiON or Si ₃ N ₄ called underlayer by CVD or RTP process.
(4): HfN is deposited by a reactive sputtering technique.
(5): Annealing the wafer at a higher temperature above 400 ° C. in an atmosphere of mostly inert gas or N ₂ containing about 1% oxygen.

The SiO ₂ layer, SiON layer, or Si ₃ N ₄ layer deposited by CVD or RTP is typically kept at approximately 1 nm or less. The use of this layer is to improve the electrical properties of the final hybrid dielectric material.

  Except for the differences described above, all other film preparation methods are the same as those described in the first embodiment.

FIGS. 7 and 8 show the CV and IV curves, respectively, for the resulting film where the underlying layer is SiO ₂ having a thickness of 1.2 nm. 9 and 10 show the CV and IV curves, respectively, for the resulting film where the underlayer is SiON having a thickness of 1.2 nm. These SiO ₂ and SiON are deposited by the RTP process. HfN is deposited on these wafers by reactive sputtering under the conditions given in the first embodiment. Thereafter, the film is thermally annealed at a temperature of 900 ° C. for 30 seconds. Thereafter, CV data and IV data are measured using a TaN metal gate electrode.

  A summary of the electrical properties of these films is shown in the table depicted in FIG.

  The annealing temperature and annealing time for subsequent film formation are important in optimizing the electrical characteristics. It should be noted that the annealing time and annealing temperature described above are probably not the best conditions. Similarly, different annealing techniques other than the RTP method can be used.

  The present invention relates to high dielectric constant dielectric films, such as various metal oxide films or metal oxynitride films having very thin and uniform thickness on doped silicon or doped Si (silicon) compound wafers. And used to deposit what is used as the gate dielectric layer of MOSFET devices.

This figure is a block diagram of a DC magnetron PVD apparatus used for HfN film formation. This figure is a process diagram for forming a high dielectric constant dielectric film as a gate insulating film. These drawings ((A) and (B)) are a plan view (A) of the wafer showing the film thickness and a vertical view (B) in the diameter line showing the normalized resistance of the film. This figure is a characteristic graph showing CV data obtained for the resulting dielectric film. This figure is a characteristic graph showing IV data obtained for the resultant dielectric film. This figure is a characteristic graph showing a change in the resistance value of HfN with respect to the flow rate of nitrogen introduced into the processing chamber. This figure is a characteristic graph showing a CV curve for the final dielectric film in which the underlayer is 1.2 nm of SiO ₂ and the thickness of HfN is 0.5 nm and 1 nm. This figure is a characteristic graph showing the IV curve of the final dielectric film when the underlying layer has a thickness of 1.2 nm of SiO ₂ and HfN of 0.5 nm and 1 nm. This figure is a characteristic graph showing the CV curve of the final dielectric film when the underlayer is SiON of 1.2 nm and the thickness of HfN is 0.5 nm and 1 nm. This figure is a characteristic graph showing the IV curve of the final dielectric film when the underlayer is SiON of 1.2 nm and the thickness of HfN is 0.5 nm or 1 nm. This figure is a table that summarizes the electrical attributes of special elements.

Explanation of symbols

10 PVD processing chamber 11 Wafer holder 12 Target 19 Magnet array 22 Wafer

Claims (1)

A wafer holder in which a wafer is arranged and rotated at a predetermined rotation speed;
A cathode provided in an inclined position at an upper position off the rotation axis of the wafer holder, a target containing hafnium is attached, and a DC power can be input;
A gas introduction part for introducing nitrogen gas as a process gas, which is provided at a position below the rotation axis of the wafer holder and where the cathode is not located above;
An exhaust port provided below the wafer holder and on the opposite side of the gas introduction unit across the wafer holder;
A reactive sputtering apparatus comprising:

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