JP4523995B2 - Method for manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a method for depositing a metal gate on a high-K dielectric film in the manufacture of a metal oxide semiconductor field effect transistor (MOSFET). In particular, the present invention relates to a method for improving the interface between a high-K dielectric film and a metal gate in the manufacture of MOSFETs. The present invention also relates to a substrate processing system suitable for use in the method.

  The basic device of most composite integrated circuits (ICs) formed on a semiconductor substrate is a metal oxide semiconductor (MOS) transistor. These transistors are generally called metal oxide semiconductor field effect transistors (hereinafter referred to as MOSFETs).

  FIG. 15 shows an example of a simple diagram of a MOSFET denoted by reference numeral 100. In FIG. 15, the MOSFET 100 includes a semiconductor 101, a gate dielectric (gate oxide film) 104, a gate electrode 105, a source region 102, and a drain region 103. In operation, an electric field is applied to the channel region 107 below the gate dielectric 104 to switch the transistor on and off.

In order to improve integrated circuit (IC) performance, IC design rules or minimum feature sizes are gradually reduced. As design rules shrink, new materials and vapor deposition techniques become important. For example, the gate oxide thickness (t _ox ) decreases with decreasing gate length (G _L ) (indicated by reference numeral 106). In this _case, with the relationship of t ox = 0.018G _L. This is important for maintaining a high capacitance between the semiconductor 101 and the gate electrode 105.

In thinning the gate oxide film 104, conventional dielectric materials (SiO ₂ , SiON) can no longer be applied. This is because very thin films of these materials exhibit different electrical characteristics (eg, high leakage current).

Therefore, the gate dielectric (gate oxide) must be replaced with a new dielectric material whose dielectric constant is higher than that of SiO ₂ . This makes it easier to use thicker films without compensating capacitance.

These high dielectric constant materials are called high-K dielectrics. For example, HfO ₂ , HfSiO, HfAlO are considered high-K dielectrics.

  If high-K dielectrics are used, conventional gate electrode materials such as polysilicon must be replaced with different materials. This is due to two reasons. That is, the first reason is that polysilicon is not compatible with most high-K dielectrics. Second, when polysilicon is used, a depletion region is formed at the interface between polysilicon and high-K, thereby increasing the equivalent oxide thickness (EOT) and lowering the capacitance.

  Pure metals, metal alloys, metal nitrides, or metal alloy nitrides are typically considered in gate electrodes used with high-K dielectrics.

  Currently, high-K and metal gates are manufactured, for example, according to the procedure shown in the following chart.

1. 1. Wash the Si substrate with diluted HF solution. 2. Dry the wafer in nitrogen. Evaporate thermal SiO ₂ (~ 1nm)
4). 4. Deposit Hf (or HfO ₂ ) 5. Perform thermal annealing. 6. Deposit metal gate. Perform thermal annealing.

Step 3 described in the procedure may be omitted, instead Hf or HfO ₂ is directly deposited on the surface treated Si. Also, the procedure described above is described using HfO ₂ as a high-K dielectric. However, any other high-K material, such as HfSiO, HfSiON, HfAlO, can be selected as the dielectric.

  FIG. 14 is a schematic view showing the CVD module 40 and the wafer loading / unloading device front end module 13 attached to the central wafer processing table 3. The CVD module 40 may be a metal organic chemical vapor deposition (MOCVD) module or an atomic layer deposition (ALD) module.

An organometallic gas is used in the MOCVD process. There are two basic groups in the organometallic gas. That is, for example, when depositing a Hf-based dielectric, i) a halide-based gas such as HfCl ₄ can be used, or ii) carbon such as C ₁₆ H ₄₀ N ₄ Hf (tetrakis, diethylamino, hafnium). System gases can be used.

  In ALD deposition, two gases are alternately introduced into the CVD module 40. When a first gas, generally called a precursor gas, is introduced into the CVD module 40, the precursor molecules adhere to the substrate surface. When the second gas is introduced into the CVD module 40, the second gas reacts with the precursor molecules attached to the surface to form a dielectric film. This process continues until a film having the desired thickness is formed.

  In any CVD (ALD or MOCVD) process, impurity contamination is the biggest problem.

  For example, first, in MOCVD, halides or carbon contaminate the wafer. Also in the ALD process, carbon from the precursor gas contaminates the film. When the impurity concentration in the dielectric film is high, leakage current and threshold voltage shift increase, and the mobility of electrons in the channel region 107 (FIG. 15) in the MOSFET device increases.

  Second, in any CVD (MOCVD or ALD) process, the wafer must be heated to a high temperature, such as 400 ° C. The temperature uniformity on the substrate surface directly affects the film uniformity. If the temperature becomes non-uniform, the dielectric film becomes non-uniform, thereby causing defects in the MOSFET device, i.e., reducing the yield per wafer (reducing the number of good MOSFETs).

  Third, especially in the ALD method, the throughput is reduced and the economical feasibility is limited. In the ALD process, the film grows with the switching of the two gases, so the deposition rate is slow. The required film thickness of the High-K dielectric material is typically 10-40 angstroms. Considering these deposition rates and film thicknesses, the throughput is less than 10 wafers per hour.

  Fourthly, since the precursor is expensive and the utilization efficiency of the precursor is low, the running cost of the CVD method is high. This also limits the economic feasibility of the CVD method.

JP-A-6-29248 JP-A-4-225223 JP-A-9-148246 JP 2000-232077 A

Fermi level pinning at the polysilicon / metal oxide interface (C. Hobbs, L. Fonseca, V. Danapadani, S. Samavedam, B. Taylor, J. Grant, L. Dip, R. Triedo, R. Triedo. D. Gilmer, R. Garcia, D. Raon, L. Lovejoy, R. Rai, L. Herbert, h. Tseng, B. White, P. Tobin VLSI Technology Symposium, 2003, pages 9-10) Atomic layer deposition of lanthanum aluminum oxide nanolaminates for electrical applications, Boyong S. Lim, Anti Rahtu, Philippe de Rouffignac, Roy G. Gordon Journal of Applied Physics, Letter 84, pages 3957-59 Kappa Challenge at 45nm Node, Peter Singer Semiconductor International

  In manufacturing a high-K dielectric film and a metal gate, the quality of the lower interface between Si and the high-K dielectric film and the upper interface between the high-K dielectric film and the metal gate is important.

  In particular, the quality of the upper interface affects the mobility of electrons and the threshold voltage (Vth) shift due to the pinning effect.

In order to increase electron mobility and minimize _Vth shift, the interface trap density must be reduced.

  The interface trap density depends on the quality of the high-K dielectric and metal gate material and the manufacturing process.

  Conventionally, after thermal annealing of a high-K dielectric, typically performed in a separate annealing system, the wafer is exposed to normal atmosphere until placed in a metal gate deposition system.

  High-K dielectrics typically exhibit good thermal stability, but exhibit different chemical properties depending on the dielectric material after exposure to normal air.

For example, when HfO ₂ is selected as high-K, a SiO ₂ layer can be grown at the interface between Si and high-K. This is because oxygen diffuses across the HfO ₂ film. Since the thickness of the interface SiO ₂ changes according to the time of exposure to normal air, a problem of reliability arises.

  When LaO or an alloy thereof is used as high-K, moisture is absorbed into the film when exposed to the atmosphere. Therefore, this changes the trap density in the film and at the interface. All of these changes after exposure to air degrade the film quality, thereby reducing the performance of the final semiconductor device.

  Accordingly, it is an object of the present invention to provide a method for depositing a metal gate on a high-K dielectric film in the manufacture of a metal oxide semiconductor field effect transistor (MOSFET), thereby providing a high-K dielectric film and a metal gate. It is to improve the quality of the material, thereby improving electron mobility and minimizing the Vth shift.

Another object of the present invention is to provide a method for improving the interface between a high-K dielectric film and a metal gate in the manufacture of a MOSFET, thereby reducing the interface trap density, thereby reducing the mobility of electrons. The improvement is to minimize the _Vth shift.

  It is a further object of the present invention to provide a substrate processing system suitable for use in the method.

  In order to achieve the above object, a first aspect of the present invention is a method for depositing a metal gate on a high-K dielectric film in the manufacture of a MOSFET, in a thermal annealing module, on which high- An annealing step of annealing a substrate having a K dielectric film deposited thereon and a deposition step of depositing a metal gate material on the annealed substrate in a metal gate deposition module without breaking the vacuum. And providing a method characterized in that the deposition step is performed continuously.

  This method of the present invention is performed by the substrate processing system of the present invention. The substrate processing system includes a wafer processing table having a transfer means for transferring a substrate, and a processing module connected to the wafer processing table. The processing module includes at least a thermal annealing module and a metal gate deposition module. The transfer means transfers the substrate between the wafer processing table and the processing module without breaking the vacuum.

  A second aspect of the present invention is a method for depositing a metal gate on a high-K dielectric film in the manufacture of a MOSFET, wherein the high-K dielectric film is deposited thereon in a thermal annealing module. An annealing step for annealing the substrate; a cooling step for cooling the annealed substrate in a cooling module; and a deposition step for depositing a metal gate material on the cooled substrate in a metal gate deposition module. The method is characterized in that the annealing step, the cooling step, and the deposition step are performed continuously without breaking a vacuum.

  This method of the present invention is performed by the substrate processing system of the present invention. The substrate processing system includes a wafer processing table having a transfer means for transferring a substrate, and a processing module connected to the wafer processing table, the processing module including at least a thermal annealing module, a cooling module, A metal gate deposition module, and the transfer means transfers the substrate between the wafer processing table and the processing module without breaking a vacuum.

  A third aspect of the present invention is a method for depositing a metal gate on a high-K dielectric film in the manufacture of a MOSFET, wherein the high-K dielectric film is deposited on a substrate in a high-K deposition module. First annealing step, annealing step of annealing the substrate on which a high-K dielectric film is deposited in a thermal annealing module, and cooling step of cooling the annealed substrate in a cooling module And a second deposition step for depositing a metal gate material on the cooled substrate in a metal gate deposition module, and without breaking a vacuum, the first deposition step, the annealing step, the cooling step A method is provided wherein the step and the second deposition step are performed sequentially.

  This method of the present invention is performed by the substrate processing system of the present invention. The substrate processing system includes a wafer processing table having a transfer means for transferring a substrate, and a processing module connected to the wafer processing table, the processing module including at least a thermal annealing module, a cooling module, It has a high-K vapor deposition module and a metal gate vapor deposition module, and the transfer means transfers the substrate between the wafer processing table and the processing module without breaking the vacuum.

A fourth aspect of the present invention is a method for depositing a metal gate on a high-K dielectric film in the manufacture of a MOSFET, wherein a thin thermal SiO ₂ film is deposited on a substrate in a thermal annealing module. 1 vapor deposition step; a first cooling step for cooling the substrate in a cooling module; a second vapor deposition step for depositing a high-K dielectric film on the substrate in a high-K vapor deposition module; An annealing step for annealing the substrate in a thermal annealing module; a second cooling step for cooling the annealed substrate in a cooling module; and a metal on the cooled substrate in a metal gate deposition module. A third deposition step for depositing a gate material, and without breaking a vacuum, the first deposition step, the first cooling step The method is characterized in that the step, the second vapor deposition step, the annealing step, the second cooling step, and the third vapor deposition step are performed continuously.

  This method of the present invention is performed by the substrate processing system of the present invention. The substrate processing system includes a wafer processing table having a transfer means for transferring a substrate, and a processing module connected to the wafer processing table, the processing module including at least a thermal annealing module, a cooling module, It has a high-K vapor deposition module and a metal gate vapor deposition module, and the transfer means transfers the substrate between the wafer processing table and the processing module without breaking the vacuum.

  According to a fifth aspect of the present invention, there is provided a method for depositing a metal gate on a high-K dielectric film in the manufacture of a MOSFET according to any of the first to fourth aspects of the present invention. The metal gate formed by the vapor deposition step of depositing a gate material includes a composite film stack, and after the metal gate is formed, the substrate is further continuously annealed in the thermal annealing module without breaking a vacuum. Provide a method.

  In this vapor deposition method, the above-described composite film stack including various films, for example, a composite film stack including different films is stacked. Further, the metal laminate materials are mixed with each other by an annealing step which is continuously performed after the metal gate material made of the composite film laminate is formed.

  A sixth aspect of the present invention is a high-K dielectric in the manufacture of a MOSFET by depositing a metal gate on a high-K dielectric film according to the method of any of the first to fifth aspects of the present invention. A method is provided for improving the interface between a film and a metal gate.

  A seventh aspect of the present invention is a substrate processing system comprising a wafer processing table having a transfer means for transferring a substrate, and a processing module connected to the wafer processing table, wherein the processing module includes at least The substrate processing system includes a thermal annealing module and a metal gate deposition module, and the transfer unit transfers the substrate between the wafer processing table and the processing module without breaking a vacuum.

  An eighth aspect of the present invention is the substrate processing system according to the seventh aspect of the present invention, wherein the processing module further includes a cooling module and / or a high-K dielectric deposition module. I will provide a.

In the present invention, by providing an improved method for depositing a metal gate on a high-K dielectric film in the manufacture of MOSFETs, the quality of the high-K dielectric film and the metal gate material is improved, thereby Electron mobility is improved and _Vth shift is minimized.

Also, by providing an improved method for improving the interface between a high-K dielectric film and a metal gate in the manufacture of MOSFETs, the interface trap density can be lowered, thereby improving electron mobility. Thus, the _Vth shift can be minimized.

  Furthermore, the present invention provides a substrate processing system suitable for use with the inventive method described above.

  In the present invention, the thermal annealing system and the metal gate deposition system are integrated with one wafer processing platform to improve the interface characteristics between the high-K dielectric film and the metal gate, thereby improving the electrical characteristics and devices. Performance is improved.

Schematic of integrated system used in Example 1 The figure which shows the other structure in Example 1. FIG. The figure which shows the schematic of Example 2. Schematic diagram of another integrated system Sectional view of the beveled PVD module provided in the integrated system shown in FIG. Sectional drawing of the thermal annealing module provided in the one side system shown by FIG. (A)-(d) is a figure which shows the procedure of a vapor deposition and a thermal annealing process. Diagram showing a schematic of another integrated system Diagram showing a schematic of another integrated system (A) shows the uniform line of the Hf film deposited on the 300 mm wafer, and (b) shows the cross-sectional uniformity of the Hf film. The figure which shows the change of the HfSi film | membrane composition according to the applied DC electric power (A) shows an iso-uniform line of a TaN film deposited on a 200 mm wafer, and (b) shows a cross-sectional uniformity of the TaN film. The figure which shows the RBS data obtained in the HfSiON film Schematic of a wafer processing system in which a CVD chamber for depositing a high-K dielectric using CVD technology is connected to a central wafer processing platform. Schematic diagram of MOSFET

  In the following examples, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  In FIG. 1, a thermal annealing module 1 and a metal gate deposition module 2 are connected to a central wafer processing table 3. That is, the thermal annealing module 1 and the metal gate deposition module 2 are integrated with the central wafer processing table 3.

  A cross-sectional view of the thermal annealing module 1 is shown in FIG. The thermal annealing module 1 is preferably a rapid thermal annealing module. As shown in FIG. 6, the thermal annealing module 1 such as the RTP module shown in FIG. 6 includes a substrate holder 19, a wafer heating mechanism 20 that heats the substrate 4 disposed on the substrate holder 19, and a gas inlet. 21, a gas exhaust port 22, and a substrate loading / unloading port 33.

  In general, the heating mechanism 20 is an infrared (IR) heating process using an infrared (IR) lamp. Usually, the thermal annealing module 1 such as an RTP module can heat the substrate 4 to a temperature of about 1000 ° C. within a few seconds. During substrate heating, the substrate holder 19 may or may not be rotated. A thermal annealing module 1 such as an RTP module heats a substrate under a low pressure using an inert gas or a mixture of an inert gas and a reactive gas.

The thermal annealing module 1 may heat the substrate 4 to a high temperature using any suitable technique, for example using an IR lamp, in-furnace annealing, or RF heating. The annealing temperature may vary from 100 ° C to 1200 ° C. The actual annealing temperature may vary depending on the high-K (high dielectric constant) material. Also, the annealing pressure is not critical. The pressure may vary from 10 ⁻⁷ Pa to atmospheric pressure.

  The metal gate deposition technique performed in the metal gate deposition module 2 is also not important. This technique may be PVD, thermal CVD, plasma CVD or atomic layer deposition. The deposition pressure, precursor gas, and mixed gas depend on the type of metal gate.

  In addition to the thermal annealing module 1 and the metal gate vapor deposition module 2, a wafer loading / unloading device front end module 13 is attached to the central table 3. Therefore, the thermal annealing module 1, the metal gate deposition module 2, and the wafer loading / unloading device front end module 13 are integrated with the central wafer processing table 3. The wafer carry-in / out device front-end module 13 includes a wafer aligner 5, a wafer carry-in port 6, and a wafer carry-out port 7.

  A substrate 4 on which a high-K dielectric film is deposited is disposed in the thermal annealing module 1 of FIG. The substrate 4 is subjected to a thermal annealing process at a desired temperature in the thermal annealing module 1. Thermal annealing may be a one-step process or a two-step process using different gas atmospheres. Thereafter, the substrate 4 is transferred into the metal gate deposition module 2 via the central wafer processing table 3 by transfer means such as a robot arm 9. In the metal gate deposition module 2, a metal gate material is deposited. The metal gate material may be any suitable material such as TaN, HfSi, RuTa, Ir, or W.

  As described above, an annealing step for annealing a substrate having a high-K dielectric film deposited thereon in a thermal annealing module and a deposition step for depositing a metal gate material on the annealed substrate in a metal gate deposition module. Is performed continuously without breaking the vacuum.

  FIG. 2 shows a state in which the cooling module 8 is connected to the central wafer processing table 3 in addition to the configuration shown in FIG. That is, in FIG. 2, the thermal annealing module 1, the metal gate deposition module 2, the cooling module 8, and the wafer loading / unloading device front end module 13 are integrated with the central wafer processing table 3.

  Using the integrated system shown in FIG. 2, the substrate 4 can be cooled after the thermal annealing of the high-K dielectric described above and before the substrate 4 is placed in the metal gate module 2.

  That is, when the integrated system shown in FIG. 2 is used, an annealing step is first performed in which a substrate having a high-K dielectric film deposited thereon is annealed in a thermal annealing module, and then the annealing is performed. The substrate is cooled in a cooling module, and then a metal gate material is deposited on the cooled substrate in a metal gate deposition module. In this case, the annealing step, the cooling step, and the vapor deposition step can be performed continuously without breaking the vacuum.

  As described above, the thermal annealing module and the metal gate deposition module are integrated with one central wafer processing platform, so that the metal gate deposition module can be used immediately after the high-K annealing process without breaking the vacuum. The metal gate can be deposited by being conveyed inside.

  In addition, the thermal annealing module, cooling module, and metal gate deposition module are integrated with one central wafer processing stand, so that the wafer can be metalized without breaking the vacuum immediately after the high-K annealing process and cooling process. The metal gate can be deposited by being transferred into a gate deposition module.

  When a thermal annealing system and a metal gate deposition system are integrated into one central wafer processing table, or a thermal annealing system, a cooling system and a metal gate deposition system are integrated into one central wafer processing table, a high-K dielectric Interfacial characteristics between the film and the metal gate can be improved, thereby improving electrical characteristics and device performance.

  FIG. 3 shows an expanded example of the first embodiment in which the high-K dielectric deposition module 10 is further attached to the central wafer processing table 3 described in the first embodiment.

  In the embodiment shown in FIG. 3, in addition to the configuration shown in FIG. 2, a high-K dielectric deposition module 10 is connected to the central wafer processing table 3. That is, in FIG. 3, the thermal annealing module 1, the metal gate deposition module 2, the cooling module 8, the high-K dielectric deposition module 10, and the wafer loading / unloading device front end module 13 are integrated with the central wafer processing table 3. ing.

  The cooling module 8 may be removed from the configuration shown in FIG. The High-K dielectric deposition technique may be any desired technique, such as PVD, CVD, MOCVD or ALD. Parameters such as deposition pressure, precursor gas, temperature, etc. depend on the deposition technique and the type of high-K material.

First, a high-K material such as HfO ₂ is deposited on the substrate 4 by placing a wafer in the high-K dielectric deposition module 10. Further, a metal or metal alloy such as Hf, HfSi, HfAl, etc., which is oxidized in the thermal annealing module 1, can be deposited in the high-K dielectric deposition module 10. Thereafter, the substrate 4 is transferred into the thermal annealing module 1 and an annealing process is performed. Annealing is usually a step in an oxygen or inert gas atmosphere. However, a two-step annealing process can also be performed. In this case, in the first step, annealing is performed at a relatively low temperature in an oxygen atmosphere, and in the second step, annealing is performed at a relatively high temperature in an inert gas atmosphere.

  Thereafter, the wafer is cooled by using the cooling module 8. Thereafter, the wafer is transferred into the metal gate deposition module 2 to deposit metal.

  When the configuration shown in FIG. 3 is used, high-K vapor deposition, thermal annealing, and metal gate vapor deposition can be performed without breaking the vacuum. Thereby, the film quality is further improved, and as a result, the quality of the semiconductor device is improved.

  Using the integrated system shown in FIG. 3, the following process can be performed.

  First, a high-K dielectric film is deposited on a substrate in a high-K deposition module, and the substrate on which the high-K dielectric film is deposited is annealed in a thermal annealing module, and the annealed. The substrate is cooled in a cooling module, and then a metal gate material is deposited on the cooled substrate in a metal gate deposition module. In this case, the first vapor deposition step, the annealing step, the cooling step, and the second vapor deposition step are continuously performed without breaking the vacuum.

In addition, the following process can be performed. After a first deposition step of depositing a thin thermal SiO ₂ film on the substrate in a thermal annealing module, the substrate is cooled in a cooling module and a high-K dielectric film on the substrate in a high-K deposition module. And annealing the substrate in a thermal annealing module, cooling the annealed substrate in a cooling module, and then depositing a metal gate material on the cooled substrate in a metal gate deposition module. In this case, the first vapor deposition step, the first cooling step, the second vapor deposition step, the annealing step, the second cooling step, and the third vapor deposition step can be continuously performed without breaking the vacuum. .

  As described above, the thermal annealing module, the cooling module, the high-K deposition module, and the metal gate deposition module are integrated with one central wafer processing table, so that immediately after the high-K annealing process and the cooling process. In addition, the metal gate can be deposited by transporting the wafer into the metal gate deposition module without breaking the vacuum.

  When the thermal annealing system, the cooling module, the high-K deposition module and the metal gate deposition module are integrated with one central wafer processing platform, the interface characteristics between the high-K dielectric film and the metal gate can be improved. As a result, electrical characteristics and device performance can be improved.

  FIG. 4 shows an integrated system comprising two oblique angle PVD modules 11, 12, one thermal annealing module 1, a cooling module 8, a central wafer processing table 3, and a wafer loading / unloading device front end module 13. FIG.

  The hardware configuration of both oblique angle PVD modules 11 and 12 is the same except for the target material fixed to each cathode. A cross-sectional view of an example of an oblique PVD module that can be employed in the substrate processing system of the present invention is shown in FIG.

  The oblique PVD modules 11 and 12 include a chamber having a chamber wall 27, a vacuuming port 28, and a wafer loading / unloading port 29. As shown in FIG. 5, a substrate holder 17 is provided in the chamber.

  The beveled PVD modules 11 and 12 use off-axis sputtering techniques in which the surfaces of the substrate 4 and the target (anti-cathode) 14 are not parallel as in the case of a conventional PVD system, and as shown in FIG. These two surfaces form an angle α (indicated by reference numeral 15). However, this angle α (15) is not critical and may be in the range of 10 ° to 90 °, but is generally about 45 °. Each beveled PVD system may have one or more inclined targets. For example, although one cathode 16 is shown in FIG. 5, each PVD system shown in FIG. 4 accommodates five cathodes (16a, 16b, 16c, 16d, 16e) and thus five The target 14 is accommodated.

  In each cathode, as shown in FIG. 5, a backing plate 30 is provided by an insulator 31 in the opening of the cathode 16. The target 14 is supported by the front surface of the backing plate 30, and a magnet 32 is provided on the back surface of the backing plate 30. The magnet 32 is rotated during film deposition.

  A target 14 made of metal, metal nitride, metal oxide or semiconductor is fixed to each of the cathodes 16a to 16e. To ignite and maintain the plasma, each cathode is supplied with DC or RF power as shown in FIG. Ions in the plasma sputter the target material, and these sputtered atoms are deposited on the substrate 4 disposed on the substrate holder 17.

  The substrate holder 17 on which the substrate 4 is disposed for film deposition rotates around its central axis 18 during film deposition. Since the sputtered atoms come at a predetermined angle, the rotation of the substrate holder 17 is important for obtaining a uniform film thickness over the wafer surface.

  The PVD module can accommodate five cathodes (16a, 16b, 16c, 16d, 16e) simultaneously. These cathodes 16 a to 16 e form a predetermined angle α (15) with respect to the surface of the substrate 4 and are fixed to the ceilings of the oblique PVD modules 11 and 12. This angle α (15) is not critical and can vary from 10 ° to 90 °, but is generally about 45 °. Each cathode 16 has a metal target or dielectric target 14 as an integral part of the cathode 16. Above the target 14 is a magnet 32 that is rotated during film deposition. However, the magnet 32 is not indispensable. When the magnet 32 is used, the plasma density increases and the plasma can be confined in the lower region of the target to suppress diffusion to the wall 27 of the chamber of the PVD module. Further, the diameter of the target 14 is not important and is generally about 200 mm. The target 14 is a simple flat plate that is firmly fixed to the backing plate 30. The backing plate 30 is typically cooled using circulating water or any other suitable liquid. For clarity of illustration, the cooling mechanism of the backing plate 30 is not shown.

  In FIG. 5, reference numeral 35 denotes a shutter.

  Each cathode 16 is electrically isolated from the rest of the hardware and is connected to a DC power supply unit or an RF power supply unit. FIG. 5 shows only a DC power source. The DC or RF power applied to the target 14 is not critical, but is generally less than 500W. This is because the high-K material that must be deposited on the substrate 4 is very thin. Therefore, in order to control the film thickness with high accuracy, the film deposition rate must be reduced. Therefore, the film thickness can be accurately controlled by measuring the deposition time.

  The oblique PVD modules 11 and 12 are evacuated to a low pressure and maintained at a low pressure before and after the plasma is ignited. Although the pressure in the chambers of the oblique PVD modules 11 and 12 is not important, the deposition is usually performed at a pressure lower than 1 Pa.

  By comparing the mean free path of gas atoms in the PVD modules 11 and 12 with respect to the substrate-target distance, a very uniform deposited film can be obtained.

Sputter deposition can be performed using an inert gas plasma such as Ar plasma or using a mixed gas such as Ar + O ₂ or Ar + N ₂ . When a reaction gas mixture is used, the sputtered atoms react with the gas species to form different products such as metal nitrides or metal oxides, which are then deposited on the surface of the wafer. Film deposition is generally performed at a pressure below 1 Pa, but this is not critical and different pressures can be used for film deposition.

  Film deposition can be performed using a single target 14 and supplying DC or RF power to the appropriate target. Alternatively, film deposition can be performed by a co-sputtering process in which RF or DC power is simultaneously supplied to two or more targets 14 provided in each of the cathodes 16a to 16e. In this case, the atomic composition of the alloy material is controlled by adjusting the DC or RF power applied to each target.

  One beveled PVD system may be used for the High-K dielectric and the other beveled PVD system may be used for gate electrode deposition.

  The thermal annealing module 1 used in the configuration of FIG. 4 is the same as the thermal annealing module shown in FIG. 6 and described in the first embodiment.

When the substrate 4 on which the film is deposited in the oblique PVD module 11 is placed in the thermal annealing module 1 such as an RTP module, the substrate is generally 400 ° C. under a reaction mixed gas, preferably using an Ar + O ₂ mixed gas. It is heated to a high temperature exceeding During this heating, the metal, metal alloy or metal nitride is oxidized into a dielectric.

  Heating by the thermal annealing module 1 such as an RTP module can be performed in one or more steps in the same gas environment or in different gas environments. In the first step, for example, heating is performed only to oxidize the film deposited on the wafer surface, and in the second step or subsequent steps, the wafer is heated to a higher temperature. The oxide film and the lower Si or any other lower film are mixed.

  The cooling module 8 includes at least a wafer stage that is cooled to a low temperature.

In this case as well, an electrostatic chuck mechanism is integrally provided on the wafer stage in order to clamp the wafer on the wafer stage. This is important when wafer cooling must be performed at high speed. The pressure in the cooling module 8 is not important and may be in a range from atmospheric pressure to a low pressure of about 10 ⁻⁷ Pa.

  The central wafer processing table 3 is formed between the oblique PVD module 11 and the central wafer processing table 3, between the thermal annealing module 1 and the central wafer processing table 3, and between the oblique PVD module 12 and the center without causing vacuum breakage. A robot arm 9 for transferring the substrate 4 between the wafer processing table 3, between the cooling module 8 and the central wafer processing table 3, between the wafer loading / unloading device front-end module 13 and the central wafer processing table 3. Transport means.

  The wafer loading / unloading device front end module 13 includes at least one wafer handling arm and one or more stages for placing a wafer cassette. For simplicity, they are not shown.

  A method of forming High-K and a metal gate is as follows, and will be described with reference to FIG.

Step-1 Depositing a preliminary film for a high-K dielectric Step-2 Performing thermal annealing in an oxygen atmosphere to form a high-K dielectric Step-3 Cooling the wafer Step-4 Metal Electrode material is deposited.

Detailed description of vapor deposition method Step-1
The starting wafer may or may not have a thin SiO ₂ or SiON layer 23 deposited first. This is shown in FIG. Using one bevel PVD module, the starting material 24 for the High-K dielectric is deposited on the substrate 4 (FIG. 7 (b)). The starting material 24 may be a metal, a refractory metal such as Hf, Ta, or Zr, a metal nitride such as HfN, TaN, or TiN, a metal alloy such as HfTa or HfTi, a metal semiconductor alloy such as HfSi, TaSiN, or the like The metal alloy nitride is preferable.

  In this case as well, two or more films described above can be deposited as a laminated structure. For example, Hf / SiN / Hf, HfN / AlN /, Hf.

  Usually, Hf, Zr, Ti or Ta is used as the metal target 14. However, other metal targets can be used. When the metal semiconductor alloy is deposited, the semiconductor material is preferably Si.

  Although not critical, the film thickness of the starting material described above is typically maintained below 5 nm, and is generally maintained at about 2 nm.

Step-2
After depositing the starting film 24 as described above, the substrate 4 is transferred into the thermal annealing module 1. Under an oxygen gas atmosphere, the substrate 4 is heated to a high temperature, typically exceeding 400 ° C., which oxidizes the starting material (FIG. 7C) and forms a high-K dielectric 25. The heating process can be performed in one or more stages. Usually, in order to control the chemical reaction during the annealing process, it is appropriate to perform the heat treatment in two or more stages. For example, first, the film is heated to 400 ° C. to oxidize the metal elements in the starting material. When the film is heated at once to a very high temperature, such as 800 ° C., the metal element in the film may form its silicon compound which is stable and exhibits metallic characteristics. If the membrane is properly oxidized at a relatively low temperature, eg 400 ° C., the temperature is raised to a high value, eg 900 ° C., preferably in an inert gas environment. When a metal stack of different metals is used as the starting material, high temperature annealing is important in diffusion between each material and to form a uniform film composition.

Step-3
After the thermal annealing process is finished, the substrate 4 is transferred to the cooling module 8 and cooled to a desired temperature, preferably room temperature.

Step-4
The substrate 4 is transferred to the other oblique angle PVD module, and the gate electrode 26 is deposited (FIG. 7D).

  The gate material is a metal such as Ta, Ru or Hf, a metal nitride such as TiN, HfN or TaN, a metal alloy such as RuTa or HfTa, a metal semiconductor alloy such as HfSi or TaSi, a metal semiconductor alloy nitride such as TaSiN, Or the laminated body which consists of a film | membrane mentioned above, for example, Hf / TaN / TiN, Ru / Ta / TaN may be sufficient.

  When depositing film stacks on top of each other, it is not necessary to remove the substrate from the beveled PVD module in order to deposit the respective films. This PVD module has 5 cathodes 16a-16e and supports up to 5 different targets by fixing the appropriate target, so any desired metal within the same bevel PVD module A laminate can be deposited.

  After depositing the gate electrode, the substrate may be subjected to a thermal annealing process, particularly when a metal stack is deposited. During this thermal annealing process, the metal stack interdiffuses to form a new uniform composition. Alternatively, the wafer can be removed directly from the integrated system shown in FIG. 4 after gate electrode deposition.

  Prior to placing the wafer in the integrated system described above, it is preferable to treat the substrate as follows to improve electrical characteristics.

1. 1. Wash substrate with diluted HF solution to remove native oxide on the surface. 2. Dry the substrate. A very thin (eg 1 nm) layer of thermal SiO ₂ is deposited (eg first deposited film 23 shown in FIG. 7 (a)). This process can take place in the thermal annealing module 1.

The reason for using a thin thermal SiO ₂ layer 23 on the Si substrate 4 is that after all the film deposition forming processes described above, the first deposited SiO 2 as shown in FIGS. 7 (c) and 7 (d). _This is because part of the _two layers 23 remains at the interface between the Si substrate 4 and the high-K dielectric 25. Thereby, the leakage current is reduced, the voltage hysteresis is lowered, and the mobility of electrons in the channel region in the MOSFET is increased.

  These beveled PVD modules 11, 12 shown in FIG. 5 and used in the configuration of FIG. 4 can achieve high deposition rates. As a result of the high deposition rate, an economically realizable throughput can be obtained with the present invention.

  In FIG. 8, two oblique angle PVD modules 11 and 12, two thermal annealing modules 1 a and 1 b, one cooling module 8, and a wafer loading / unloading device front end module 13 are provided in the central wafer processing table 3. It is attached to.

  Compared to the integrated system described in the third embodiment, a further thermal annealing module is additionally provided in the fourth embodiment. Except for this addition, all other hardware is the same as that described in the third embodiment. This further thermal annealing module is used in high temperature annealing of the gate electrode material. Forming a high-K dielectric and gate electrode by annealing the starting material using a separate thermal annealing module increases throughput and minimizes secondary contamination. Except for the differences described above, all other processing steps and procedures are the same as those described in the third embodiment.

  FIG. 9 shows a schematic diagram of an integrated system for depositing a high-K dielectric. This system includes an oblique PVD module 11, a thermal annealing module 1 such as an RTP module, a central wafer processing table 3, and a wafer loading / unloading device front end module (EFEM) 13.

  The configuration and mechanism of the beveled PVD module 11 is described in Example 3 and shown in FIG. Therefore, the description is omitted in this embodiment.

  FIG. 10A shows the uniformity of the Hf film deposited on the 300 mm wafer using the oblique PVD module 11 at a pressure of 0.015 Pa. Other parameters used for the deposition are as follows: Target-substrate vertical distance = 250 mm, DC power applied to Hf target = 300 W, substrate holder rotation speed = 240 rpm, plasma gas = Ar. The standard deviation (σ) of multiple film thickness measurements is generally given as film non-uniformity. The standard deviation (σ) of the 49-point measurement value of the Hf film shown in FIG. 10 (a) is 0.16%. The line shown in FIG. 10A is the uniform line 36. The reference sign 37 shown in each iso-uniform line is normalized uniformity. FIG. 10 (b) shows the normalized uniformity across the diameter line.

  In the case of bimetal deposition or metal alloy deposition, DC or RF power is simultaneously applied to two or more targets (16a, 16b ...). By adjusting the DC or RF power applied to each cathode, the composition of the metal alloy can be varied. For example, FIG. 11 shows the controllability of the HfSi composition. The vapor deposition conditions in FIG. 11 are as follows. Process gas = Ar, pressure = 0.015 Pa, Hf target DC power = 70 W, Si target DC power = 30 W to 130 W, substrate-target distance = 250 mm. By controlling the DC power applied to the Si target, the Hf portion of the HfSi film can be controlled to 55% to 82% (or the Si portion is 45% to 18%). In FIG. 11, the change of the Hf portion of the HfSi film is indicated by reference numeral 38, and the change of the Si portion of the HfSi film is indicated by reference numeral 39.

In the case of reactive sputter deposition, a reactive gas such as oxygen or nitrogen is added to the PVD module in addition to an inert gas such as Ar. The reactive gas decomposes in the plasma and reacts with the sputtered atoms, and is then deposited on the wafer surface. For example, FIG. 12A shows the film uniformity of a TaN film deposited by a reactive sputtering method using an Ar + N ₂ mixed gas under the following conditions.

Ta target DC power = 300 W, plasma gas = Ar, pressure = 0.015 Pa, Ar flow rate = 30 sccm, N ₂ flow rate = 10 sccm, substrate-target distance = 250 mm.

  FIG. 12 (a) shows the uniform line 36, while FIG. 12 (b) shows the normalized uniformity across the diameter line. The standard deviation of the 49-thickness measurement of the TaN film shown in FIG. 12 is 0.13%.

  After the film is deposited in the PVD module 11, the substrate 4 is transferred to the thermal annealing module 1 without causing a vacuum break.

  The thermal annealing module 1 is the RTP module shown in FIG. 6 and has been described in the first embodiment.

  Heating by the thermal annealing module 1 such as an RTP module can be performed in two or more steps in the same or different gas environment. For example, in the first step, heating is performed only to oxidize the film deposited on the wafer surface, and in the second step or subsequent steps, the wafer is heated to a higher temperature and oxidized. And the lower Si or any other lower film is mixed.

  For example, an HfSiON film is formed by the following process.

Start with p-type Si wafer Remove native oxide by cleaning with HF Evaporate 1 nm thermal SiO ₂ Deposit 1 nm HfN by placing in PVD module (11) Wafer RTP module (1) Arranged in Annealing at 400 ° C. for 30 seconds in an oxygen atmosphere Annealing at 800 ° C. for 30 seconds in an inert gas atmosphere The wafer is taken out and the film is evaluated.

During the first annealing step, the HfN film is oxidized to form HfON. During the second annealing step, HfON and the lower SiO ₂ film are mixed together to form HfSiON. The RBS spectrum obtained in the film is shown in FIG. This figure clearly shows that the film is HfSiON.

  Note that after the RTP process, a Ti film is deposited as a capping layer in order to prevent further oxidation of the formed high-K film.

During the second RTP process, only a portion of the initially deposited thermal SiO ₂ film is consumed to form HfSiON. Therefore, a thin SiO ₂ layer remains just above the semiconductor and below the HfSiON film.

In order to increase the mobility of electrons in the channel region 107 (FIG. 15), it is important to leave a very thin layer made of thermal SiO ₂ below the HfSiON film. Therefore, the RTP temperature and time for consuming only part of the thermal SiO ₂ must be controlled. Thus, this method allows a very thin thermal SiO ₂ layer, for example 5 Å, to remain under the HfSiON layer. The importance of this process is that there is no reliable technique for directly depositing such a thin SiO ₂ layer.

  HfSiON is regarded as a high-K material having a relative dielectric constant of 15 to 24 depending on the film composition.

  Similar to the method described above, many other different high-K materials can be deposited using PVD and RTP modules without breaking the vacuum.

  In this process, since the vacuum is not broken, the reliability of the entire process is very high, and the entire process is reproducible. Therefore, this process can be applied to actual device manufacturing with certainty.

  As described above, the PVD (physical vapor deposition) module and the RTP (rapid thermal processing) module are integrated using a wafer transfer module and an EFEM (apparatus front end module). In this case, first, a metal, metal nitride, or metal oxide is deposited on the substrate by placing it in the PVD module, and second, the metal film becomes dielectric by exposing the wafer to an RTP process. Converted to body and / or improved dielectric properties. Since the film deposition step and the RTP process are performed without breaking the vacuum, the film deposited by this process provides reproducible and reliable properties.

  The present invention is not limited to the above-described preferred embodiments, but may be changed to various embodiments within the technical scope defined by the appended claims and the scope equivalent thereto.

DESCRIPTION OF SYMBOLS 1 Thermal annealing module 2 Metal gate vapor deposition module 3 Central wafer processing stand 4 Substrate 5 Wafer aligner 6 Wafer carry-in port 7 Wafer carry-out port 8 Cooling module 9 Robot arm 10 high-K dielectric vapor deposition module 11 Oblique PVD module 12 Oblique PVD Module 13 Wafer loading / unloading device front end module 14 Target 15 Target angle α
16 Cathode 16a, 16b, 16c, 16d, 16e Cathode 17 Substrate holder 18 Center axis of substrate holder 19 Substrate holder 20 Wafer heating mechanism 21 Gas inlet 22 Gas outlet 23 Very thin SiO ₂ or SiON layer deposited first 24 Starting material (membrane)
25 high-K dielectric 26 gate electrode 27 chamber wall 28 evacuation port 29 wafer loading / unloading port 30 backing plate 31 insulator 32 magnet 33 substrate loading / unloading port

Claims (18)

A substrate processing system having a wafer transfer module having transfer means for transferring a substrate, and a thermal annealing module, a cooling module, a first PVD module, and a second PVD module connected to the wafer transfer module was used. In a method of manufacturing a field effect transistor having a high dielectric gate insulating film and a metal gate electrode,

Formation of a first step and a second step of forming a SiO ₂ film on the substrate in the thermal annealing module, the SiO ₂ film for carrying the substrate to the thermal annealing module using said conveying means third step and, Hf / AlN / Hf claim 1 composed laminated film of a laminated body on the SiO ₂ film of the substrate to be carried into the first PVD module using the transport means of the substrate that is a fourth step of forming in a PVD module, said a fifth step of a substrate formed of a laminated film loading into the thermal annealing module, in the multilayer film the thermal annealing module substrate formed of a sixth step of forming the high dielectric gate insulating film in by heating to oxidize the laminated film, formed of the high dielectric gate insulating film A seventh step of transferring the substrate to the second PVD module by using the conveyor means that, the metal gate electrode film in the second PVD module to the high dielectric gate insulating film on the substrate eighth step of forming includes a city,

The formed SiO ₂ film, the formed laminated film and said formed high dielectric film said wafer transfer is conveyed through the module the first said substrate by said conveying means without exposure to the air A method comprising performing the steps in the order of the eighth step to the eighth step.
The method of manufacturing a field effect transistor according to claim 1, carried in the between the second step third step, the cooling module using a conveying means a substrate formed of the SiO ₂ film a ninth step of, a tenth step of cooling the substrate formed of the SiO ₂ film in the cooling module includes a city, between the seventh step and the sixth step, the An eleventh step of carrying the substrate on which the high dielectric gate insulating film is formed into the cooling module using a transfer means, and a twelfth step of cooling the substrate on which the high dielectric gate insulating film is formed by the cooling module. And a method comprising.
2. The method of manufacturing a field effect transistor according to claim 1, wherein the annealing in the sixth step is performed in an oxygen gas atmosphere.
2. The method of manufacturing a field effect transistor according to claim 1, wherein the sixth step includes a first annealing performed in an oxygen gas atmosphere and a second annealing performed in an inert gas atmosphere.
2. The method of manufacturing a field effect transistor according to claim 1, wherein a substrate holder on which the substrate is placed and a cathode including a target are provided in the first and second PVD modules, and the target. The method wherein the surface is in the range of 10 ° to 90 ° with respect to the surface of the substrate placed on the substrate holder.
2. The method of manufacturing a field effect transistor according to claim 1, wherein the metal gate electrode film in the eighth step is a metal.
The method of manufacturing a field effect transistor according to claim 6 , wherein the metal is Ta, Ru, or Hf.
2. The method of manufacturing a field effect transistor according to claim 1, wherein the metal gate electrode film in the eighth step is a metal nitride.
9. The method of manufacturing a field effect transistor according to claim 8 , wherein the metal nitride is TiN, HfN, or TaN.
2. The method of manufacturing a field effect transistor according to claim 1, wherein the metal gate electrode film in the eighth step is a metal alloy.
11. The method of manufacturing a field effect transistor according to claim 10 , wherein the metal alloy is RuTa or HfTa.
2. The method of manufacturing a field effect transistor according to claim 1, wherein the metal gate electrode film in the eighth step is a metal semiconductor alloy.
13. The method of manufacturing a field effect transistor according to claim 12 , wherein the metal semiconductor alloy is HfSi or TaSi.
2. The method of manufacturing a field effect transistor according to claim 1, wherein the metal gate electrode film in the eighth step is a metal semiconductor alloy nitride.
15. The method of manufacturing a field effect transistor according to claim 14 , wherein the metal semiconductor alloy nitride is TaSiN.
The method of manufacturing a field effect transistor according to claim 1, wherein the metal gate electrode film in the step of the eighth is a metal laminate film method.
17. The method of manufacturing a field effect transistor according to claim 16 , wherein the metal laminate film is Hf / TaN / TiN or Ru / Ta / TaN.
17. The method of manufacturing a field effect transistor according to claim 16 , wherein the formation of the metal laminate film is performed in the second PVD module.

Images