JP5998232B2 - Thin film transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to the semiconductor field, and more particularly to a thin film transistor and a method for manufacturing the same.

  Organic light emitting diodes (OLEDs) are attracting widespread attention because they have many advantages such as self-emission, immediate response, light weight, low power consumption, and flexible display. It is considered a technology. Currently, OLED technology is being applied to various electric products. Among them, the active matrix organic EL display (AMOLED: Active Matrix / Organic Light Emitting Diode) has advantages such as high image quality, short video response time, low power consumption, wide field of view and ultra-thin lightness, so OLED has been developed. It has become a major trend.

  Currently, polysilicon thin film transistors are often used in AMOLED rear panel technology. Polysilicon thin film transistors have advantages such as low power consumption and high electron mobility. Since the processing temperature of the initial polysilicon thin film transistor is as high as 1000 ° C., the selection of the substrate material is severely limited. Recently, with the development of laser, the processing temperature of polysilicon thin film transistors has dropped to 600 ° C. or lower, so that a glass substrate can be used as the substrate. A polysilicon thin film transistor formed by this process method is also referred to as a low temperature polysilicon thin film transistor (LTPS TFT).

  In traditional alkali glass, the content of metals such as aluminum, barium, and sodium is relatively high, and is easily diffused by thermal circulation of the process. In the conventional manufacturing process of a low-temperature polysilicon thin film transistor, alkali-free glass is adopted and a buffer layer is formed on the substrate as one step. By forming the buffer layer, it is possible to prevent formation of a defect center due to diffusion of metal ions into the LTPS active region in the substrate and further increase in leakage current. The appropriate thickness of the buffer layer can improve the quality of the polysilicon back interface, reduce thermal conduction, and reduce the cooling rate of the silicon heated by the laser, thus forming relatively large polysilicon crystal grains To help.

In Patent Document 1 (CN1012651311A), the buffer layer is composed of a SiN _x / SiO ₂ thin film having a double layer structure, or a SiN _x thin film or a SiO ₂ thin film having a single layer structure, and the SiN _x / SiO ₂ having a double layer structure. In the case of a thin film buffer layer, a method for producing a low-temperature polysilicon thin film in which the upper layer of the buffer layer is a SiO ₂ thin film and the lower layer is a SiN _x thin film formed on a substrate has been disclosed.

  In the manufacture of a polysilicon thin film transistor, the content of impurities is strictly required, and the buffer layer in the prior art cannot completely prevent the diffusion of metal ions on the glass substrate. In order to solve this problem, the thickness of the buffer layer is usually increased so as to improve the blocking function, but if the buffer layer becomes too thick, the residual stress increases, which affects the crystallization characteristics. .

  Therefore, there is a need for a method that can reliably and effectively improve the blocking function of the buffer layer. As a result, a buffer layer with a strong blocking function is manufactured, the stability of the polysilicon layer is improved, and the quality of the interface on the back surface of the polysilicon is improved, thereby obtaining a thin film transistor with improved reliability and yield. A display device with improved quality is obtained.

  Regarding the above problems, the inventor changed the film formation structure and the film formation quality after a long-term study, and manufactured a buffer layer having a structure in which silicon nitride and silicon oxide were stacked in multiple layers. As described above, the plurality of crystal interfaces can be increased and the diffusion of metal ions can be prevented, thereby improving the reliability of the thin film transistor having the buffer layer having the multilayer structure.

  In one aspect, the present invention provides a thin film transistor, wherein the thin film transistor includes a substrate and a buffer layer disposed on the substrate, the buffer layer including n silicon nitride layers (n ≧ 3), a first silicon oxide layer disposed on the n silicon nitride layers, and two adjacent silicon nitride layers among the n silicon nitride layers have different densities.

In one embodiment of the present invention, the n layer is 5 to 10 layers.
In another embodiment of the present invention, the thickness of each silicon nitride layer of the n silicon nitride layers is 50 to 100 mm.

  In another embodiment of the present invention, the thickness of the first silicon oxide layer is about 1500 mm.

  In another embodiment of the present invention, an interfacial oxide layer is further formed between the two adjacent silicon nitride layers.

In another embodiment of the present invention, the interfacial oxide layer is a silicon oxide layer.
In another embodiment of the present invention, the buffer layer further includes a second silicon oxide layer disposed on the first silicon oxide layer and having a density lower than that of the first silicon oxide layer.

  In another embodiment of the present invention, the second silicon oxide layer has a thickness of 500 to 1000 mm.

  In another embodiment of the present invention, the thin film transistor further includes a polysilicon layer disposed on the buffer layer.

  In another aspect, the present invention provides a method of manufacturing a thin film transistor, wherein the method of manufacturing the thin film transistor has different deposition powers of two adjacent silicon nitride layers, and the adjacent 2 layers are formed on a substrate. Depositing n (n ≧ 3) silicon nitride layers having different silicon nitride layer densities, depositing a first silicon oxide layer on the n silicon nitride layers, Forming a buffer layer formed by stacking a silicon nitride layer and the first silicon oxide layer; and forming an active layer on the buffer layer.

In one embodiment of the method of the present invention, the n layer is 5 to 10 layers.
In another embodiment of the method of the present invention, the thickness of the silicon nitride layer is 50-100 mm.

  In another embodiment of the method of the present invention, the deposition power of the silicon nitride layer is 500-1500W.

  In another embodiment of the method of the present invention, the deposition power of the two adjacent silicon nitride layers has a difference of 100W.

  In another embodiment of the method of the present invention, the thickness of the first silicon oxide layer is about 1500 mm.

  In another embodiment of the method of the present invention, the deposition power of the first silicon oxide layer is 500 W or less.

  In another embodiment of the method of the present invention, an interfacial oxide layer formed by injecting an oxidizing gas is included between the adjacent silicon nitride layers.

In another embodiment of the method of the present invention, the oxidizing gas is N ₂ O.
In another embodiment of the method of the present invention, the method further includes forming a second silicon oxide layer having a density lower than that of the first silicon oxide layer on the first silicon oxide layer.

  In another embodiment of the present invention, the second silicon oxide layer has a thickness of 500 to 1000 mm.

  In another embodiment of the method of the present invention, the deposition power of the second silicon oxide layer is 1000 W or more.

  In another embodiment of the method of the present invention, the active layer is a polysilicon layer.

  The thin film transistor having an improved buffer layer according to the present invention forms a buffer layer having a structure in which n silicon nitride layers and one silicon oxide layer are stacked by changing the film formation structure and film quality. Thus, the blocking ability of the buffer layer can be enhanced. For this reason, the upward diffusion of metal ions in the glass substrate can be effectively prevented, the formation of defect centers in the polysilicon layer can be reduced, and the leakage current can be reduced. Then, the quality of the interface on the back surface of the polysilicon can be improved, the formation of a current leak path at the interface on the back surface of the polysilicon can be prevented, and the stability of the polysilicon layer can be improved. Thus, the reliability of the thin film transistor can be improved, and the yield and quality of the display device can be improved.

It is a figure which shows typically the structure of the thin-film transistor which concerns on one embodiment of this invention. It is a figure which shows typically the structure of the buffer layer which concerns on one embodiment of this invention. It is a flowchart of the process of the manufacturing method of the thin-film transistor which concerns on Example 1 of this invention.

  Hereinafter, the technical solution of the present invention will be further described using specific examples. The scope of protection of the present invention is not limited to the following examples, which are merely illustrative and do not limit the present invention.

  The present invention provides a thin film transistor. In a preferred embodiment, as shown in FIGS. 1 and 2, the thin film transistor includes a substrate 1, a buffer layer, a polysilicon layer 3, a gate insulating layer 4, a gate 5, an interlayer dielectric layer 6, and a source / drain. 7 is provided. The buffer layer 2 includes an n-layer silicon nitride layer 21, a first silicon oxide layer 22 disposed on the n-layer silicon nitride layer 21, and a second silicon oxide disposed on the first silicon oxide layer 22. Layer 23 is provided. The density of two adjacent silicon nitride layers in the n silicon nitride layer 21 is different, and the n layer is three or more layers.

  The fact that both silicon oxide / silicon nitride layer structures prevent diffusion of impurities in the glass substrate as a buffer layer is due to the use of the blocking function of silicon nitride itself and the crystal interface between silicon nitride and silicon oxide. . In the present invention, an n-layer silicon nitride layer and a first silicon oxide layer having different densities of two adjacent silicon nitride layers are employed as buffer layers, and a crystal interface is formed between the silicon nitride layers. The number of interfaces can be increased, and the blocking function against diffusion of metal ions by the buffer layer can be enhanced.

  Compared to silicon nitride, the crystalline phase of polysilicon formed from silicon oxide is better, and silicon nitride has a better effect of blocking impurities from the substrate, so in the buffer layer, the upper layer consists of a silicon oxide layer and the lower layer It is preferable to consist of a silicon nitride layer.

  The buffer layer should have an appropriate thickness, and if it is too thin, it has a poor ability to prevent the diffusion of metal ions, and if it is too thick, it will cause considerable residual stress and affect the crystallization properties. Should be kept below 3000cm. A buffer layer with the appropriate thickness can improve the quality of the backside interface of the polysilicon, reduce the heat conduction, and reduce the cooling rate of the silicon heated by the laser, so that relatively large polysilicon crystal particles Help form.

  In order to increase the number of crystal interfaces, theoretically, as many silicon nitride layers with different densities as possible should be formed. However, in consideration of process complexity and production cost, 5 to 10 n layers are formed. It is preferable that

  Of the n silicon nitride layers, each silicon nitride layer has a substantially uniform thickness and is preferably 50 to 100 mm. Therefore, it is possible to sufficiently secure a blocking function against metal ion diffusion.

  By forming the first silicon oxide layer having a relatively high density on the n silicon nitride layers, close connection and good adhesion between the silicon nitride layer and the silicon oxide layer are ensured. The thickness of the first silicon oxide layer is preferably about 1500 mm.

  An interfacial oxide layer made of silicon oxide is further formed between two adjacent silicon nitride layers. Since the crystal interface between silicon nitride and silicon oxide has a better blocking effect on metal ions from the glass substrate than the crystal interface between silicon nitrides of different densities, the interface oxide layer is a metal layer formed by a buffer layer. The blocking function against ions can be effectively enhanced.

  Since a relatively sparse second silicon oxide layer is formed on the first silicon oxide layer, there is sufficient space for the amorphous silicon to be re-arranged in the polysilicon structure. The second silicon oxide layer is preferably formed to a thickness of 500 to 1000 mm.

  The present invention further provides a method for manufacturing the thin film transistor. In the method of manufacturing the thin film transistor, an n-layer (n ≧ 3) silicon nitride layer is deposited on a substrate, and the deposition powers of the two adjacent silicon nitride layers are made different, whereby the n-layer silicon nitride is formed. The n-type silicon nitride layer and the n-type silicon nitride layer are deposited on the n-type silicon nitride layer by differentiating the densities of two adjacent silicon nitride layers of the layers. A buffer layer formed by stacking a silicon monoxide layer is formed, and an active layer is formed on the buffer layer.

The active layer is preferably a polysilicon layer.
According to the present invention, the n silicon nitride layer and the first silicon oxide layer constituting the buffer layer of the thin film transistor are formed by a CVD method (Chemical Vapor Deposition), for example, a low pressure CVD method, a thermal CVD method, a catalytic CVD method, A plasma CVD method or the like can be used. Among them, it is preferable to use a plasma CVD method. Plasma CVD (PECVD) is a conventional low-temperature thin film manufacturing technology that combines glow discharge and CVD. The basic principle is that low-temperature plasma is used as an energy source, and the substrate is placed on a glow discharge cathode. An appropriate amount of reaction raw material gas is injected, and the gas undergoes a series of chemical reactions and plasma reactions to form a series of thin films on the surface of the substrate. PECVD has advantages such as a low basic temperature, a high deposition rate, and good film quality, and is therefore often used in the low-temperature polysilicon thin film manufacturing field.

The source gas of the silicon nitride layer can use NH ₃ , NH ₂ H ₂ N, N ₂ or the like as a nitrogen source gas, preferably NH ₃ and N _2, and SiH ₄ , Si ₂ H ₆ , SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ , SiH ₃ Cl ₃ , SiF _{4 and the} like can be used, and SiH ₄ is preferably used.

Source gas of the silicon oxide layer as an oxygen source _gas, available _{O 2, O 3, N 2} O or the like, it is preferable to use _{N 2} O, as a silicon source _{gas, SiH 4, Si 2 H 6} , SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ , SiH ₃ Cl ₃ , SiF _{4 and the} like can be used, and SiH ₄ is preferably used.

  Formation of film layers having different densities can be realized, for example, by adjusting process parameters such as the type of source gas, the flow rate ratio of source gas, deposition power, and deposition temperature. For example, the density may be controlled by adopting the same source gas type, flow rate ratio and deposition temperature, and adjusting the deposition power, or adopting the same source gas type, deposition temperature and deposition power, The density may be controlled by adjusting the gas flow rate ratio, or the density may be controlled by adjusting the deposition temperature by adopting the same source gas type, flow rate ratio and deposition power. In order to obtain further excellent effects, a plurality of parameters may be adjusted simultaneously.

  It is preferable to control the density by adjusting the deposition power in consideration of the complexity of the process and the production cost. In general, when a relatively high deposition power is employed, a relatively sparse film layer can be obtained, and when a relatively low deposition power is employed, a relatively dense film layer can be obtained.

  In one embodiment of the present invention, when depositing n silicon nitride layers, the density between the two adjacent layers of the n silicon nitride layers is different by different deposition power between the two adjacent layers. To do. The deposition power of the n silicon nitride layers is preferably 500 to 1500 W. In order to exert a certain degree of blocking effect on the crystal interface between the two adjacent silicon nitride layers, the density of the two adjacent silicon nitride layers should be made different to some extent. It is preferable that the deposition power of the silicon nitride layer is varied to some extent, and the difference is 100 W.

In another embodiment of the present invention, an oxidizing gas is injected between the deposited silicon nitride layers to form an interfacial oxide layer. As the oxidizing gas, O ₂ , O ₃ , N ₂ O, or the like can be used, and N ₂ O is preferably used. The power for injecting the oxidizing gas is 500 W or less.

  In another embodiment of the invention, the first silicon oxide layer is deposited at a first power such that the density of the first silicon oxide layer is higher than the density of the second silicon oxide layer, and the first silicon oxide layer is higher than the first power. Deposit a second silicon oxide layer with two powers. The first power is preferably 500 W or less, and the formed first silicon oxide layer is relatively tight, and can be closely connected to the silicon nitride layer and can be adhered well. The second power is preferably 1000 W or more, and since the formed second silicon oxide layer becomes relatively sparse and has good adaptability, the amorphous silicon is re-arranged in the polysilicon structure. Enough space.

  The thin film transistor of the present invention is not limited to the substrate, polysilicon layer, gate insulating layer, gate, interlayer dielectric layer, and source / drain. Can be formed. For example, a glass substrate is used as a substrate, a polysilicon layer is formed by laser annealing treatment on an amorphous silicon layer, a silicon nitride / silicon oxide two-layer laminated structure is used as a gate insulating layer, and a gate is used. Using materials such as aluminum, molybdenum, chromium, tungsten, tantalum, titanium, etc., it is possible to use a two-layer laminated structure of silicon nitride / silicon oxide as the interlayer dielectric layer, and the source / drain is doped to the polysilicon layer Formed by.

  Since the thin film transistor of the present invention employs a buffer layer having an n-layer silicon nitride layer and a first silicon oxide layer, the buffer layer has a good blocking function against the upward diffusion of metal ions in the glass substrate. In addition, the stability of the polysilicon layer can be ensured. For this reason, the thin film transistor of the present invention has good reliability.

  The present invention further provides an example in which the thin film transistor is applied to an OLED. Since the thin film transistor of the present invention has high reliability, the defect rate of the display device can be effectively lowered as a drive circuit switch element of the display device, and display quality can be improved.

  Unless otherwise limited, the terms used in the present invention have the meaning normally understood by those skilled in the art.

Hereinafter, the present invention will be described in more detail by way of examples.
Examples Comparative Example 1
In a vacuum chamber, a low-temperature plasma is generated as a gas reaction energy source by an RF source having an RF high frequency of 13.56 MHZ, and monosilane, ammonia gas, and nitrogen gas reaction gas are injected through a multi-path gas introducing device, Silicon nitride with a flow rate ratio of monosilane and ammonia gas set to 1: 1 to 3, deposition temperature set to 420 to 430 ° C., and a thickness of 1000 mm on a glass substrate with a power of 500 W by PECVD method Deposit layers.

  In the same chamber, a low-temperature plasma is generated as a gas reaction energy source by an RF source having an RF high frequency of 13.56 MHZ, and monosilane and nitrous oxide reaction gases are injected through a multi-path gas introducing device, and monosilane and sub-nitrogen are injected. The flow ratio with nitrogen oxide is set to 1: 40-50, the deposition temperature is set to 420-430 ° C., and the thickness is about 1500 mm on the above silicon nitride layer with a power of 1000 W by PECVD method. A silicon oxide layer is deposited to form a two layer buffer layer of silicon nitride / silicon oxide.

An amorphous silicon layer is formed on the buffer layer.
Laser annealing is performed on the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer.

  A gate insulating layer, a gate, an interlayer dielectric layer, and a source / drain are sequentially formed on the polysilicon layer.

  The leakage current was measured for the thin film transistor in Comparative Example 1, and the measurement results were 1E-11 to 1E-12A.

Example 1
FIG. 3 is a flowchart of the process of the method for manufacturing the thin film transistor according to the first embodiment of the invention. Detailed explanation is as follows.

  a) In a vacuum chamber, a low temperature plasma is generated as a gas reaction energy source by an RF source having an RF high frequency of 13.56 MHz, and a reactive gas of monosilane, ammonia gas, and nitrogen gas is injected through a multipath gas introduction device. Then, the flow ratio of monosilane and ammonia gas is set to 1: 1 to 3, the deposition temperature is set to 420 to 430 ° C., and the thickness is 100 mm on the glass substrate with the power of 500 W by the PECVD method. A first silicon nitride layer is deposited. See Table 1 for deposition process parameters.

  b) In the same chamber, while maintaining the above process conditions, only the deposition power is changed, and a second silicon layer having a thickness of 100 mm is formed on the first silicon nitride layer formed with the second power of 600 W. A silicon nitride layer is continuously deposited.

  c) Step b is repeated, and each time a silicon nitride layer is deposited, the deposition power is increased by 100 W to deposit a total of 10 silicon nitride layers.

  d) In the same chamber, a low temperature plasma is generated as a gas reaction energy source by an RF source having an RF high frequency of 13.56 MHZ, and a monosilane and nitrous oxide reaction gas is injected through a multi-path gas introducing device. The flow ratio of nitrous oxide is set to 1: 40-50, the deposition temperature is set to 420-430 ° C., and the thickness is formed on the silicon nitride layer by PECVD with a first power of 500 W. A first silicon oxide layer having a thickness of about 1500 Å is deposited. See Table 2 for deposition process parameters.

  e) Maintaining the above process conditions in the same chamber, changing only the deposition power, and a thickness of 500 to 1000 on the first silicon oxide layer with a second power of 1000 W by PECVD method. A second silicon oxide layer is deposited, and a buffer layer is formed by stacking n silicon nitride layers and two silicon oxide layers.

  f) Using the same material and method as in Comparative Example 1, a polysilicon layer, a gate insulating layer, a gate, an interlayer dielectric layer, and a source / drain are sequentially formed in the buffer layer.

  The leakage current was measured for the thin film transistor according to Example 1, and the measurement result was 1E-12A.

Example 2
A) In a vacuum chamber, a low-temperature plasma is generated as a gas reaction energy source by an RF source having an RF high frequency of 13.56 MHZ, and monosilane, ammonia gas, and nitrogen gas reaction gases are injected through a multipath gas introduction device. The flow ratio of monosilane and ammonia gas is set to 1: 1 to 3, the deposition temperature is set to 420 to 430 ° C., and the thickness is 100 mm on the glass substrate with a power of 500 W by PECVD method. A first silicon nitride layer is deposited. See Table 3 for deposition process parameters.

b) N ₂ O is injected into the above chamber at a temperature of 420 to 430 ° C. to form an interface oxide layer.

  c) In the same chamber, maintaining the above process conditions and changing only the deposition power, the second power having a thickness of 100 mm on the first silicon nitride layer formed with the second power of 600 W. A silicon nitride layer is continuously deposited.

  d) Repeat steps b) and c) to increase the deposition power of 100 W each time a silicon nitride layer is deposited, depositing a total of 10 silicon nitride layers.

  e) In the same chamber, a low temperature plasma is generated as a gas reaction energy source by an RF source having an RF high frequency of 13.56 MHZ, and a monosilane and nitrous oxide reaction gas is injected through a multi-path gas introducing device. The flow ratio of nitrous oxide is set to 1: 40-50, the deposition temperature is set to 420-430 ° C., and the thickness is formed on the silicon nitride layer by PECVD with a first power of 500 W. Deposit a first silicon oxide layer that is approximately 1500 Å. See Table 4 for deposition process parameters.

  f) In the same chamber, maintaining the above process conditions, changing only the deposition power, and depositing a second silicon oxide layer having a thickness of 500-1000 mm on the glass substrate with a second power of 1000 W. Then, a buffer layer is formed by stacking n silicon nitride layers including an interface oxide layer and two silicon oxide layers.

  g) Using the same material and method as in Comparative Example 1, a polysilicon layer, a gate insulating layer, a gate, an interlayer dielectric layer, and a source / drain are sequentially formed in the buffer layer.

  The leakage current is measured for the thin film transistor according to Example 2, and the measurement result is smaller than 1E-12A. The magnitudes of the leakage currents of Comparative Example 1, Example 1, and Example 2 are compared, and the result is the leakage current of Comparative Example 1> the leakage current of Example 1> the leakage current of Example 2.

  Thereby, the buffer layer employing the structure having the n-layer silicon nitride and the first silicon oxide layer can effectively reduce the leakage current as compared with the conventional technique. If an interfacial oxide layer is interposed between the silicon nitride layers, the leakage current can be further reduced.

  In summary, the thin film transistor of the present invention changes the film formation structure and film quality, and forms a buffer layer having a structure in which n silicon nitride layers and one silicon oxide layer are stacked. The blocking ability of the buffer layer can be strengthened. For this reason, the upward diffusion of metal ions in the glass substrate can be effectively prevented, the formation of defect centers in the polysilicon layer can be reduced, and the leakage current can be reduced. Then, the quality of the interface on the back surface of the polysilicon can be improved, the formation of a current leak path at the interface on the back surface of the polysilicon can be prevented, and the stability of the polysilicon layer can be improved. Thus, the reliability of the thin film transistor can be improved, and the yield and quality of the display device can be improved.

  For those skilled in the art, the embodiments described in the present invention are merely exemplary, and various substitutions, changes, and improvements may be made within the scope of the present invention. For this reason, this invention is not limited to said embodiment, It is limited only by a claim.

1 substrate 2 buffer layer 21 n silicon nitride layer 22 first silicon oxide layer 23 second silicon oxide layer 3 polysilicon layer 4 gate insulating layer 5 gate 6 interlayer dielectric layer 7 source / drain

Claims (21)

A thin film transistor having a substrate and a buffer layer disposed on the substrate,
The buffer layer is
n layers (n ≧ 3) of silicon nitride layers;
A first silicon oxide layer disposed on the n silicon nitride layers,
The thin film transistor according to claim 1, wherein two adjacent silicon nitride layers among the n silicon nitride layers have different densities. The thin film transistor according to claim 1, wherein the n layer is 5 to 10 layers. The thickness of each silicon nitride layer of the n-layer silicon nitride layer of a thin film transistor according to claim 2, characterized in that it is a 50 to 100 Å. The thin film transistor according to claim 1, wherein the thickness of the first silicon oxide layer is about 1500 mm. The thin film transistor according to claim 1, further comprising an interfacial oxide layer formed between the two adjacent silicon nitride layers. The thin film transistor according to claim 5, wherein the interface oxide layer is a silicon oxide layer. 2. The thin film transistor according to claim 1, wherein the buffer layer further includes a second silicon oxide layer disposed on the first silicon oxide layer and having a density lower than that of the first silicon oxide layer. The thin film transistor according to claim 7, wherein the second silicon oxide layer has a thickness of 500 to 1000 mm. Furthermore, it has a polysilicon layer installed on the said buffer layer. The thin-film transistor of any one of Claims 1-7 characterized by the above-mentioned. Depositing n (n ≧ 3) silicon nitride layers having different densities of the two adjacent silicon nitride layers on the substrate with different deposition powers of the two adjacent silicon nitride layers; ,
Depositing a first silicon oxide layer on the n silicon nitride layer to form a buffer layer formed by stacking the n silicon nitride layer and the first silicon oxide layer;
Forming an active layer on the buffer layer. A method of manufacturing a thin film transistor, comprising: The method for producing a thin film transistor according to claim 10, wherein the n layer is 5 to 10 layers. The method of manufacturing a thin film transistor according to claim 11, wherein each silicon nitride layer has a thickness of 50 to 100 mm. The method of manufacturing a thin film transistor according to claim 12, wherein the deposition power of the silicon nitride layer is 500 to 1500W. The method of manufacturing a thin film transistor according to claim 13, wherein the deposition power of the two adjacent silicon nitride layers has a difference of 100W. The method of manufacturing a thin film transistor according to claim 10, wherein the thickness of the first silicon oxide layer is about 1500 mm. The method of manufacturing a thin film transistor according to claim 15, wherein the deposition power of the first silicon oxide layer is 500 W or less. The method for manufacturing a thin film transistor according to claim 10, wherein an interfacial oxide layer formed by injecting an oxidizing gas is included between the adjacent silicon nitride layers. The method of manufacturing a thin film transistor according to claim 17, wherein the oxidizing gas is N ₂ O. The method of manufacturing a thin film transistor according to claim 10, further comprising forming a second silicon oxide layer having a lower density than the first silicon oxide layer on the first silicon oxide layer. The method of manufacturing a thin film transistor according to claim 19, wherein the thickness of the second silicon oxide layer is 500 to 1000 mm. The method for manufacturing a thin film transistor according to claim 19, wherein the deposition power of the second silicon oxide layer is 1000 W or more.