JPWO2019087784A1 - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a thin film transistor according to one embodiment of the present invention includes forming an active layer over a substrate. A source region and a drain region are formed so as to be electrically connected to the active layer. A first metal oxide layer made of silicon oxide is formed on the surface of the active layer by plasma CVD. A second metal oxide layer made of aluminum oxide is formed on the surface of the first metal oxide layer by ALD. A gate electrode is formed on the surface of the second metal oxide layer.

Description

  The present invention relates to a thin film transistor having a multi-layered gate insulating film and a method for manufacturing the same.

  LTPS thin film transistors (Low Temperature Poly Silicon TFTs) have high mobility and are used in organic EL display devices and liquid crystal display devices. For example, Patent Document 1 discloses a thin film transistor using LTPS as an active layer.

JP 2010-98149 A

  Usually, a thin film transistor using polysilicon is formed on a polysilicon in the order of a gate insulating film and a gate electrode. However, when the coverage of the gate insulating film is poor, the gate insulating film is not uniformly formed on the uneven polysilicon. For this reason, a leak current flows between the gate electrode and the polysilicon, causing problems on the display device such as unevenness in the image.

  In view of the circumstances as described above, an object of the present invention is to provide a thin film transistor having a high coverage and excellent transistor characteristics and a method for manufacturing the same.

In order to achieve the above object, a method for manufacturing a thin film transistor according to an embodiment of the present invention includes:
Forming an active layer on the substrate.
A source region and a drain region are formed so as to be electrically connected to the active layer.
A first metal oxide layer made of silicon oxide is formed on the surface of the active layer by plasma CVD.
A second metal oxide layer made of aluminum oxide is formed on the surface of the first metal oxide layer by ALD.
A gate electrode is formed on the surface of the second metal oxide layer.

  In the manufacturing method, the first and second metal oxide layers are sequentially formed as the gate insulating film. Since the second metal oxide layer is composed of an aluminum oxide film formed by ALD, a high coverage can be obtained as compared with a gate insulating film made of a silicon oxide single film formed by plasma CVD. As a result, a leakage current between the gate electrode and the active layer can be effectively prevented, and a thin film transistor capable of good threshold voltage control can be manufactured.

  Further, by forming the gate insulating film in multiple layers in this way, the apparent dielectric constant becomes higher than that of the gate insulating film made of a single silicon oxide film. This improves the charge mobility of the active layer.

  The method may further include a step of forming a hydrogen-rich intermediate layer between the first metal oxide layer and the second metal oxide layer, and a step of annealing the intermediate layer.

  According to this manufacturing method, a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer moves to the interface between the active layer and the first metal oxide layer by annealing. A large amount of hydrogen atoms terminates dangling bonds existing at the interface and lowers the interface state density. As a result, a leakage current between the gate electrode and the active layer can be prevented, and a thin film transistor having good switching characteristics can be manufactured.

  Further, according to this manufacturing method, the second metal oxide layer functions as a barrier layer, and hydrogen atoms contained in the first metal oxide layer and the intermediate layer are annealed to form the active layer and the first metal oxide layer. It becomes easy to move to the interface with the physical layer. Thereby, it becomes possible to improve the defect repair effect of the interface.

  The intermediate layer may be formed by performing hydrogen plasma treatment on the first metal oxide layer.

  The intermediate layer may be formed by forming a silicon nitride or silicon oxynitride layer between the first and second metal oxide layers.

  The step of forming the first metal oxide layer and the step of forming the silicon nitride or silicon oxynitride layer may be performed in the same chamber. Thus, by performing the substrate processing in the same chamber, it becomes possible to prevent the contamination of the substrate surface accompanying the replacement of the substrate. Further, it is possible to reduce the labor for replacing the board and the cost of the equipment.

The step of forming the first metal oxide layer and the step of forming the second metal oxide layer may be performed continuously in a vacuum atmosphere.
Thus, it is possible to prevent contamination of the substrate surface by gas or air by making the substrate processing consistent in vacuum.

A thin film transistor according to one embodiment of the present invention includes a gate electrode, an active layer, a source region and a drain region, and a gate insulating film.
The active layer is made of polysilicon.
The source region and the drain region are electrically connected to the active layer.
The gate insulating film includes a first metal oxide layer and a second metal oxide layer.
The first metal oxide layer is made of silicon oxide and is disposed between the gate electrode and the active layer.
The second metal oxide layer is made of aluminum oxide and is disposed between the first metal oxide layer and the gate electrode.

  The gate insulating film may further include an intermediate layer containing silicon nitride between the first metal oxide layer and the second metal oxide layer.

  The gate insulating film may further include an intermediate layer containing silicon oxynitride between the first metal oxide layer and the second metal oxide layer.

The thickness of the intermediate layer may be 3 nm or more and 10 nm or less.
Since the intermediate layer functions only as a hydrogen atom supply source, a sufficient amount of hydrogen can be supplied to the interface with a thickness of 3 nm to 10 nm.

  As described above, according to the present invention, it is possible to provide a thin film transistor having a gate insulating film with high coverage and excellent transistor characteristics, and a method for manufacturing the same.

It is a schematic sectional drawing which shows the structure of the thin-film transistor which concerns on one Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is the schematic of the plasma CVD apparatus used for manufacture of the thin-film transistor which concerns on one form of this invention. 1 is a schematic view of an ALD apparatus used for manufacturing a thin film transistor according to an embodiment of the present invention. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is process sectional drawing explaining the manufacturing method of the said thin-film transistor. It is one experimental result which shows the flat band voltage of each metal oxide thin film. It is an experimental result showing a CV curve of the al ₂ O ₃ thin film. Is an experimental result showing a thin film of CV curves of a two-layer structure of the TEOS-SiO _x and _Al 2 _{O 3.} It is a figure which shows the relationship between the film thickness of the 1st metal oxide layer of the said thin-film transistor, and a flat band voltage. It is a figure which shows the relationship between the film thickness of the 1st metal oxide layer of the said thin-film transistor, and a hysteresis characteristic. It is a figure which shows the relationship between the film thickness of the 1st metal oxide layer of the said thin-film transistor, and an interface state density. It is a schematic sectional drawing which shows the structure of the thin-film transistor which concerns on the 2nd Embodiment of this invention. It is a figure which shows the relationship between the film thickness of the intermediate | middle layer of the said thin-film transistor, and an interface state density. It is a schematic sectional drawing which shows the structure of the thin-film transistor concerning the 3rd Embodiment of this invention.

[Outline of LTPS-TFT]
Generally, TEOS-SiO _X is used for a gate insulating film used for LTPS. A gate insulating film used for TEOS-SiO _X has excellent thin film transistor characteristics as compared with a gate insulating film made of SiH ₄ —SiO. Specifically, in TEOS-SiO _X , the flat band voltage is close to the ideal value, the threshold voltage control of the thin film transistor is relatively easy, the long-term stability of the thin film transistor characteristics is excellent, the defect level density at the interface is small, etc. There is a feature.

However, the TEOS-SiO _X film has a problem that it is difficult to obtain a good coverage with respect to the device pattern. In the film structure of the top gate type LTPS-TFT, a gate insulating film and a gate electrode are sequentially formed on polysilicon as an active layer. If the coverage of the gate insulating film formed on the uneven polysilicon is poor, the gate insulating film is not uniformly formed, and a leak current flows between the gate electrode and the polysilicon. This causes problems on the display device such as unevenness.
In order to increase the aperture ratio of the pixel portion of the display device and to reduce the power consumption of peripheral circuits other than the pixel, it is necessary to reduce the operating voltage. In order to take these measures, it is necessary to increase the mobility of the thin film transistor. For this purpose, it is necessary to reduce the thickness of the gate insulating film. However, since the thinning of the gate insulating film causes an increase in leakage current, there is a limit to the thinning of the gate insulating film.

Therefore, in recent years, a gate insulating film characteristic that is excellent in transistor characteristics and excellent in coverage with respect to unevenness has attracted attention as a technique necessary for improving the characteristics of display devices.
An atomic layer deposition method (ALD) is known as a technique for forming an insulating film having an excellent coverage with respect to unevenness. In this method, two or more kinds of source gases are sequentially supplied to the substrate surface to form an atomic layer controlled thin film. ALD uses a function that self-stops the adsorption and reaction in a single molecular layer when the raw material is supplied to the substrate surface. This makes it very easy to handle irregularities on the substrate, and the coverage is almost 100%. This is a method for forming an insulating film.

However, when the CV (capacitance-voltage) characteristics of the Al ₂ O ₃ thin film formed by the ALD technique are evaluated, the flat band voltage tends to greatly shift to the plus side, as will be described later. When hysteresis occurs that causes a difference in the flat band voltage between when the starting voltage during CV curve measurement is positive and when it is negative, the threshold voltage of the transistor characteristics becomes unstable. Cannot be used.

  In order to solve the above problems, in the present embodiment, the gate insulating film structure and the manufacturing method are devised to suppress the hysteresis characteristics of the CV curve, while increasing the coverage of polysilicon, thereby providing good transistor characteristics. Trying to get.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a schematic cross-sectional view of a thin film transistor 1 according to an embodiment of the present invention.

[Configuration of thin film transistor]
The thin film transistor 1 according to the present embodiment includes an active layer 11, a source region 14 </ b> S and a drain region 14 </ b> D, a gate insulating film 12, and a gate electrode 13.

  The thin film transistor 1 includes a gate insulating film 12 formed so as to cover the active layer 11, the source region 14S and the drain region 14D formed on the substrate 10, and a gate electrode 13 formed on the gate insulating film 12. A gate type thin film transistor is used.

  Hereinafter, the configuration of each part of the thin film transistor 1 will be described.

(Active layer)
The active layer 11 is made of polysilicon formed on an insulating film (eg, silicon oxide film) 10 a on the substrate 10 and functions as a channel layer of the thin film transistor 1. The substrate 10 is typically a transparent glass substrate, but may be a semiconductor substrate such as a silicon substrate or a resin substrate such as a plastic film. As will be described later, the active layer 11 is formed by crystallizing amorphous silicon formed on the substrate 10 by annealing. The thickness of the active layer 11 is not specifically limited, For example, it is 40 nm-50 nm.

(Source region and drain region)
The source region 14S and the drain region 14D are formed so as to be separated from each other so as to sandwich the active layer 11. As will be described later, the source region 14S and the drain region 14D are formed, for example, by implanting impurity ions into a polysilicon film constituting the active layer 11.

(Gate insulation film)
The gate insulating film 12 is disposed between the active layer 11 and the gate electrode 13 and electrically insulates between them, and the charge is inverted in the active layer 11 by the voltage applied to the gate electrode 12. It has a function of forming a layer (inversion layer). The gate insulating film 12 includes a first metal oxide layer 12A and a second metal oxide layer 12B.

  The first metal oxide layer 12A is formed on the substrate 10 so as to cover the active layer 11, the source region 14S, and the drain region 14D.

The first metal oxide layer 12A is made of silicon oxide (SiO _x ). In the present embodiment, the first metal oxide layer 12A is made of silicon oxide formed using silane (SiH ₄ ) or TEOS as a film forming material. Thereby, the thin film transistor 1 can relatively easily control the threshold voltage, and can obtain excellent characteristics such as excellent long-term stability of transistor characteristics and low interface state density. The thickness of the first metal oxide layer 12A can be, for example, 10 nm to 120 nm.

As a method of forming the first metal oxide layer 12A, plasma CVD (Plasma-enhanced Chemical Vapor Deposition) is used as will be described later. As a source gas for plasma CVD, for example, a silicon compound such as silane (SiH ₄ ) or tetraethoxysilane (TEOS) can be used. In this embodiment, TEOS and oxygen (O ₂ ) are used as a source gas for plasma CVD.

The second metal oxide layer 12B is formed on the first metal oxide layer 12A. The second metal oxide layer 12B is made of aluminum oxide (Al ₂ O ₃ ). As a method of forming the second metal oxide layer 12B, ALD (Atomic Layer Deposition) is used. As an ALD source gas, various aluminum compounds can be used. In this embodiment, trimethylaluminum (TMA) is used. In addition, an oxidizing gas such as oxygen or ozone (O ₃ ) can be used as a reaction gas for ALD, and in this embodiment, water vapor (H ₂ O) is used. The purge gas for ALD is not particularly limited, and nitrogen (N ₂ ) is used in this embodiment.

ALD is excellent in step coverage and film thickness controllability, and the Al ₂ O ₃ layer produced by ALD has an excellent coverage and can effectively prevent leakage current. On the other hand, when the gate insulating film is composed of a single layer of Al ₂ O ₃ thin film, the flat band voltage tends to shift in the positive direction, thereby generating a hysteresis characteristic, and depending on the magnitude of the hysteresis characteristic, The threshold voltage of the thin film transistor may become unstable.

In the present embodiment, the gate insulating film 12 is formed by sequentially laminating a first metal oxide layer 12A composed of TEOS-SiO _x and a second metal oxide layer 12B composed of Al ₂ O ₃ . It has a two-layer structure. With this structure, it is possible to suppress the hysteresis characteristic due to the Al ₂ O ₃ layer and obtain an excellent coverage. Thereby, the thin film transistor 1 can perform good threshold voltage control while preventing leakage current.

  The thickness of the second metal oxide layer 12B can be, for example, 10 nm to 120 nm. This makes it possible to obtain an excellent coverage while suppressing the hysteresis characteristics.

  By making the thickness of the gate insulating film 12 (the sum of the thickness of the first metal oxide layer 12A and the thickness of the second metal oxide layer 12B) within a total of 130 nm, the thin film transistor 1 can be reduced in size. Each of the above effects can be obtained.

(Gate electrode)
The gate electrode 13 is made of a conductive film formed on the gate insulating film 12. The gate electrode 13 is typically composed of a metal single layer film or a metal multilayer film of Al, Mo, Cu, Ti or the like, and is formed by, for example, a sputtering method. The thickness of the gate electrode 13 is not specifically limited, For example, it is 200 nm-300 nm.

(Other)
An interlayer insulating film 15 is formed on the gate insulating film 12 and the gate electrode 13. The interlayer insulating film 15 is for maintaining insulation between the electrodes. The interlayer insulating film 15 is made of an electrically insulating material, and is typically made of silicon oxide, silicon nitride, or the like. The thickness of the interlayer insulation film 15 is not specifically limited, For example, it is 200 nm-500 nm.

  The thin film transistor 1 further includes a source electrode 16S and a drain electrode 16D. The source electrode 16S and the drain electrode 16D penetrate the interlayer insulating film 15 and the gate insulating film 12, and are electrically connected to the source region 14S and the drain region 14D, respectively. The source electrode 16S and the drain electrode 16D are configured as extraction electrodes for connecting the source region 14S and the drain region 14D to a peripheral circuit (not shown).

[Thin Film Transistor Manufacturing Method]
Next, a method for manufacturing the thin film transistor 1 of the present embodiment configured as described above will be described. 2 to 8 are cross-sectional views of each process and a schematic cross-sectional view of the film forming apparatus for explaining the method of manufacturing the thin film transistor 1.

(Formation of gate electrode)
First, as shown in FIG. 2, an insulating film 10 a and an amorphous silicon film A are formed on the substrate 10. The insulating film 10a is typically composed of a silicon oxide film, but of course may be composed of other materials and may be omitted as necessary. The raw material of the amorphous silicon film A is not particularly limited. For example, if formed by plasma CVD, a silicon compound such as silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) can be used as a raw material gas.

(Formation of gate insulating film)
Next, heat treatment is performed to crystallize the amorphous silicon film A formed on the substrate 10. Thereafter, the active layer 11 made of polysilicon is formed by patterning into a predetermined shape.

  Subsequently, as shown in FIG. 3, a gate insulating film 12 is formed on the substrate 10 so as to cover the surface of the active layer 11. The formation process of the gate insulating film 12 includes a step of forming the first metal oxide layer 12A and a step of forming the second metal oxide layer 12B.

[Step of forming first metal oxide layer]
The first metal oxide layer 12 </ b> A is formed on the substrate 10 so as to cover the surface of the active layer 11. The first metal oxide layer 12A is formed by plasma CVD. The plasma CVD apparatus is not particularly limited, and in this embodiment, a plasma CVD apparatus 100 schematically shown in FIG. 4 is used.

  The plasma CVD apparatus 100 includes a vacuum chamber 110 and a substrate support stage 111 installed in the vacuum chamber 110. The stage 111 has a heater 112 inside. Inside the vacuum chamber 110, a high frequency electrode 113 is disposed at a position facing the heater stage 111. The high-frequency electrode 113 has a shower head 114. The shower head 114 is provided with a gas diffusion plate 115 for uniformly diffusing the gas introduced from the gas introduction system and a plurality of ejection holes 116 for ejecting the gas. Yes. A vacuum exhaust system 120, a power supply system 130 having a high frequency power source, a controller 140, and a gas introduction system (not shown) are connected to the vacuum chamber 110. The controller 140 controls the heater 112, the power supply system 130, the vacuum exhaust system 120, and the gas introduction system.

In the present embodiment, TEOS and O ₂ are used as a source gas (CVD gas) for plasma CVD. The flow rate ratio between TEOS and O ₂ is not particularly limited, and can be, for example, O ₂ / TEOS = 50.

The film formation conditions are not particularly limited. For example, when the glass substrate size is 730 mm × 920 mm, the film formation is performed under the following conditions.
TEOS flow rate: 360 [sccm]
O ₂ flow rate: 16000 [sccm]
Process pressure: 175 [Pa]
RF frequency: 27.12 [MHz]
RF power: 4000 [W]
Heater temperature: 350 [° C]

[Formation of second metal oxide layer]
The second metal oxide layer 12B is formed so as to cover the first metal oxide layer 12A. The second metal oxide layer 12B is formed by ALD. The ALD apparatus is not particularly limited, and an ALD apparatus 200 schematically shown in FIG. 5 is used in this embodiment.

  The ALD apparatus 200 includes a vacuum chamber 210 and a stage 211 for supporting a substrate installed inside the vacuum chamber 210. The stage 211 has a heater 212 inside. In the vacuum chamber 210, a controller 220 and a gas introduction system and a vacuum exhaust system (not shown) are arranged. The controller 220 controls the heater 212, the gas introduction system, and the vacuum exhaust system.

The gas introduction system is configured such that the source gas, the reaction gas, and the purge gas can be introduced into the vacuum chamber 210 independently or mixed. In this embodiment, TMA gas is used as the source gas, water vapor is used as the reaction gas, and N ₂ gas is used as the purge gas.

  In forming the second metal oxide layer 12B, as a first step, TMA gas is introduced into the vacuum chamber 210 as a source gas from a gas introduction system. The TMA gas molecules introduced into the vacuum chamber 210 are adsorbed (chemically adsorbed) on the surface of the substrate 10. After the TMA gas molecules are adsorbed on the surface of the substrate 10, the introduction of the TMA gas from the gas introduction system is stopped.

  For example, when the glass substrate size is 730 mm × 920 mm, the coating conditions can be such that the temperature of the substrate 10 is 250 ° C., the pressure in the vacuum chamber 210 is 100 Pa, and the amount of TMA gas introduced is 3 cc / cycle. In the subsequent processing, the temperature of the substrate 10 is set to 250 ° C.

Next, as a second step, N ₂ gas is introduced as a purge gas from the gas introduction system. The pressure in the vacuum chamber 210 is increased by the purge gas, and the source gas is pushed out. The source gas diffused in the vacuum chamber 210 is evacuated by an exhaust pump.

The purge conditions were such that the N ₂ gas introduction time was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the N ₂ gas flow rate was 1000 sccm.

Next, as a third step, water vapor is introduced as a reaction gas from the gas introduction system. The water vapor introduced into the vacuum chamber 210 reacts with TMA gas molecules adhering to the surface of the substrate 10 to oxidize TMA, and a thin film of aluminum oxide (Al ₂ O ₃ ) is formed on the surface of the substrate 10. . After the reaction, the introduction of the reaction gas from the gas introduction system is stopped.

  The oxidation conditions were such that the pressure in the vacuum chamber 210 was 100 Pa and the amount of water vapor introduced was 3 cc / cycle.

Next, as a fourth step, N ₂ gas is introduced as a purge gas from the gas introduction system. The pressure in the vacuum chamber 210 is increased by the purge gas, and water vapor is pushed out. The water vapor diffused in the vacuum chamber 210 is evacuated by an exhaust pump.

The purge conditions were such that the N ₂ gas introduction time was 1 second, the pressure in the vacuum chamber 210 was 100 Pa, and the N ₂ gas flow rate was 1000 sccm.

By repeating the above first to fourth steps for a plurality of cycles in order until the thin film has a desired thickness, the second metal oxide layer 12B made of the Al ₂ O ₃ thin film is formed.

(Gate electrode formation process)
Next, as shown in FIG. 6, the gate electrode 13 is formed on the second metal oxide layer 12B.

  The gate electrode 13 is typically composed of a metal single layer film or a metal multilayer film such as aluminum, molybdenum, copper, or titanium, and is formed by, for example, a sputtering method. The gate electrode 13 is formed by patterning the metal film into a predetermined shape.

(Process for forming source region and drain region)
Subsequently, as shown in FIG. 7, a source region 14S and a drain region 14D are formed.

  The formation method of the source region 14S and the drain region 14D is not particularly limited. In this embodiment, the source region 14S and the drain region 14D are formed in predetermined regions of the polysilicon film constituting the active layer 11 by an ion implantation technique using the gate electrode 13 as a mask. Drain regions 14D are formed respectively. Impurity ions (dopants) to be implanted are appropriately selected according to the conductivity type (N type, P type) of the active layer 11, and typically boron (B) or phosphorus (P) is used.

(Process for forming interlayer insulating film and source / drain electrode)
Next, as shown in FIG. 8, an interlayer insulating film 15 is formed so as to cover the gate electrode 13 and the second metal oxide layer 12B.

  The interlayer insulating film 15 is made of an electrically insulating material. Typically, it is composed of an oxide film or nitride film such as a silicon oxide film or a silicon nitride film, and a laminated film thereof. The interlayer insulating film 15 is formed by, for example, a CVD method or a sputtering method.

  Subsequently, openings D1 and D2 reaching the source region 14S and the drain region 14D are formed so as to penetrate the interlayer insulating film 15 and the gate insulating film 12. The formation method of the openings D1 and D2 is not particularly limited, and for example, a laser processing technique or an etching method is used.

  Thereafter, a metal film filling the openings D1 and D2 is formed on the interlayer insulating film 15, and the metal film is patterned into a predetermined shape, thereby forming the source electrode 16S and the drain electrode 16D. As described above, the thin film transistor 1 shown in FIG. 1 is manufactured.

[Operation of this embodiment]
In the present embodiment, the gate insulating film 12 is composed of a laminated film of a first metal oxide layer 12A and a second metal oxide layer 12B. Since the second metal oxide layer 12B is composed of an aluminum oxide layer formed by ALD, a higher coverage with respect to the active layer 11 than a gate insulating film made of a silicon oxide single film formed by plasma CVD. Is obtained.

Here, as described above, when the gate insulating film is composed of a single layer of Al ₂ O ₃ thin film, the flat band voltage tends to shift in the positive direction. In addition, hysteresis characteristics are likely to occur. When a gate insulating film having hysteresis characteristics is applied to a thin film transistor, the threshold voltage of the thin film transistor may be unstable.

  The inventors produced a plurality of samples having different gate insulating film configurations on a silicon wafer, and evaluated their flat band voltage and hysteresis characteristics.

First, a sample 1 having a gate insulating film made of a single layer of Al ₂ O ₃ thin film formed by ALD and a sample having a gate insulating film made of a single layer of TEOS-SiO _x thin film formed by plasma CVD. 2 were produced. In this experimental example, the plasma CVD apparatus 100 and the ALD apparatus 200 shown in FIGS. 4 and 5 were used as the film forming apparatus, respectively.

FIG. 9 and Table 1 show the measurement results showing the relationship between the thickness of the gate insulating film and the flat band voltage (Vfb) in Samples 1 and 2. In FIG. 9, the white diamond symbol indicates an Al ₂ O ₃ thin film, and the black square indicates a TEOS-SiO _x thin film.

11 and Table 1, sample 1 in which the gate insulating film is composed of an Al ₂ O ₃ thin film has a flat band voltage of +3 V or more, as compared with sample 2 in which the gate insulating film is composed of a TEOS-SiO _x thin film. It is confirmed that there is a large shift in the positive direction.

Next, a gate insulating film (a gate insulating film according to the present embodiment) composed of a laminated film of a TEOS-SiO _x thin film having a thickness of 50 nm formed by plasma CVD and an Al ₂ O ₃ thin film having a thickness of 50 nm formed by ALD. Sample 3 having a structure equivalent to 12) was prepared, and the CV curves of Sample 1 and Sample 3 were compared. 10 and 11 show the CV curve measurement results of Samples 1 and 3. FIG.

From FIG. 10, in the sample 1 in which the gate insulating film is composed of an Al ₂ O ₃ thin film, the flat band voltage is shifted to plus as described above. Further, it is confirmed that the flat band voltage differs between when the start voltage at the time of CV curve measurement is positive and when it is negative, and hysteresis characteristics are generated. The occurrence of hysteresis characteristics in the CV curve means that the threshold voltage of the transistor characteristics is unstable, which is not preferable as a gate insulating film.

On the other hand, as shown in FIG. 11, in the sample in which the gate insulating film formed the Al ₂ O ₃ thin film on the TEOS-SiO _x thin film, the hysteresis characteristics did not occur as in the sample of the above Al ₂ O ₃ thin film alone. Is confirmed. Thus, it was confirmed that the hysteresis characteristic of the CV curve hardly occurs in the thin film having a two-layer structure in which the TEOS-SiO _x thin film and the Al ₂ O ₃ thin film are sequentially formed on the silicon substrate.

From the above experimental results, also in the thin film transistor 1 of the present embodiment, the gate insulating film 12 is composed of the first metal oxide layer 12A composed of TEOS-SiO _x on the active layer 11 and Al ₂ O ₃ . Since the structured second metal oxide layer 12B is formed in order, the occurrence of hysteresis characteristics can be suppressed. Thereby, the thin film transistor 1 can perform favorable threshold voltage control.

Subsequently, in the thin film transistor 1 according to the present embodiment, the thickness of the second metal oxide layer 12B is fixed to 50 nm, and the thickness of the first metal oxide layer 12A is 0 nm to 80 nm. Band voltage Vfb (V), hysteresis (V), and interface state density Dit (eV ⁻¹ · cm ⁻² ) were measured. Each of the above measurements was performed immediately after film formation and after annealing (500 ° C.).

  12 to 14 and Table 2 show the flat band voltage, hysteresis, and interface state density obtained by the above measurements, respectively.

From FIG. 12, when the film thickness of the first metal oxide layer 12A (TEOS-SiO _x ) is 20 nm or more and 80 nm or less, the absolute value of the flat band voltage is lower than that of the sample 2, and as the film thickness increases. It is confirmed that the flat band voltage approaches 0.
Further, FIG. 13 confirms that when the film thickness of the first metal oxide layer 12A (TEOS-SiO _x ) is 20 nm or more and 80 nm or less, almost no hysteresis characteristics are generated after annealing.
In addition, it is confirmed that the hysteresis characteristic is generated when the first metal oxide layer 12A is 0 nm. This substantially corresponds to Sample 1 described above.

Further, FIG. 14 confirms that the interface state density after the annealing treatment is greatly reduced when the thickness of the first metal oxide layer 12A (TEOS-SiO _x ) is 20 nm or more and 80 nm or less. The About this result, it thinks as follows. Since the first metal oxide layer 12A is formed by plasma CVD, hydrogen atoms are contained in the first metal oxide layer 12A. The hydrogen atoms are moved to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process, and the interface state density is reduced by terminating dangling bonds existing at the interface. it is conceivable that.

As described above, in the thin film transistor 1 of the present embodiment, the gate insulating film 12 includes the first metal oxide layer 12A including the TEOS-SiO _x thin film and the second metal oxide layer 12B including the Al ₂ O ₃ thin film. Therefore, excellent threshold voltage control is ensured without generating the hysteresis characteristics of Al ₂ O ₃ . In addition, since the gate insulating film 12 can be formed with a very high coverage with respect to the active layer 11, leakage current between the gate electrode 13 and the active layer 11 can be prevented, and good switching characteristics can be obtained. .

  Furthermore, according to the present embodiment, since a good coverage of the gate insulating film 12 with respect to the active layer 11 can be obtained, the gate insulating film can be thinned. Accordingly, since the thin film transistor can be reduced in size and thickness, the aperture ratio of the pixel portion of the display device can be increased. In addition, since the operating voltage of the thin film transistor can be reduced, power consumption of the display device can be reduced.

<Second Embodiment>
FIG. 15 is a schematic cross-sectional view of a thin film transistor 2 according to the second embodiment of the present invention. Hereinafter, configurations different from those of the first embodiment will be mainly described, and configurations similar to those of the above-described embodiment will be denoted by the same reference numerals, and description thereof will be omitted or simplified.

  The thin film transistor 2 of this embodiment is different from the first embodiment in the configuration of the gate insulating film 22. Specifically, the gate insulating film 22 further includes an intermediate layer 12C disposed between the first metal oxide layer 12A and the second metal oxide layer 12B.

The intermediate layer 12C is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is made of, for example, silicon nitride (SiN _x ) or silicon oxynitride (SiO _x N _y ) formed by a plasma CVD method.

  In the intermediate layer 12C, a large amount of hydrogen atoms contained in the intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by an annealing process described later. A large amount of hydrogen atoms terminates dangling bonds existing at the interface, and an effect of reducing the interface state density can be obtained.

  The thickness of the intermediate layer 12C is not particularly limited as long as it has a function of supplying hydrogen atoms to dangling bonds as described above, and is, for example, 3 nm or more and 30 nm or less.

  Next, a method for forming the intermediate layer 12C will be described. In this embodiment, in the step of forming the gate insulating film, the step of forming the intermediate layer is included after the step of forming the first metal oxide layer. The active layer formation step, source region and drain region formation step, gate electrode formation step, interlayer insulating film formation step, and source electrode and drain electrode formation step are the same as in the first embodiment. The description is omitted here.

The intermediate layer 12C is formed on the first metal oxide layer 12A. The method for forming the intermediate layer 12C is not particularly limited as long as it contains hydrogen atoms in the intermediate layer 12C. For example, plasma CVD is used. In the present embodiment, SiH ₄ , NH _3, and N ₂ are used as a plasma CVD source gas, and an intermediate layer 12C composed of SiN _x is formed. The intermediate layer 12C is annealed at a predetermined temperature (for example, 500 ° C.) after film formation. The annealing treatment may be performed before or after the formation of the second metal oxide layer 12B. However, in order to efficiently supply hydrogen atoms contained in the intermediate layer 12C to the interface between the active layer 11 and the first metal oxide layer 12A, an annealing process is performed after the formation of the second metal oxide layer 12B. It is desirable to implement.

  The plasma CVD apparatus for forming the intermediate layer 12C is not particularly limited, and for example, the plasma CVD apparatus 100 described with reference to FIG. 4 can be employed.

The film forming conditions for the intermediate layer 12C are not particularly limited. For example, when the glass substrate size is 730 mm × 920 mm, the film is formed under the following conditions.
SiH ₄ flow rate: 500 [sccm]
NH ₃ flow rate: 5000 [sccm]
N ₂ flow rate: 7000 [sccm]
Process pressure: 200 [Pa]
RF frequency: 27.12 [MHz]
RF power: 4000 [W]
Heater temperature: 350 [° C]

  According to the present embodiment, it is possible to obtain the same effects as those of the first embodiment described above. In the present embodiment, a large amount of hydrogen atoms contained in the hydrogen-rich intermediate layer 12C moves to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process. A large amount of hydrogen atoms terminates dangling bonds existing at the interface and lowers the interface state density. As a result, leakage current between the gate electrode 13 and the active layer 11 can be prevented, and good switching characteristics can be obtained.

  Further, according to the present embodiment, the second metal oxide layer 12B functions as a hydrogen barrier layer, and hydrogen atoms contained in the intermediate layer 12C are annealed by the active layer 11 and the first metal oxide layer 12A. It becomes easy to move to the interface. Thereby, it becomes possible to enhance the defect repair effect of the interface.

  In the present embodiment, the step of forming the first metal oxide layer 12A and the step of forming the intermediate layer 12C may be performed in the same chamber. Thereby, it becomes possible to prevent contamination of the surface of the first metal oxide layer 12A due to replacement of the substrate to be processed. Further, it is possible to reduce the labor for replacing the board and the cost of the equipment.

In order to evaluate the characteristics of the thin film transistor 2 according to the present embodiment, the interface state density Dit (eV ⁻¹ · cm ⁻² ) was measured while changing the structure of the gate insulating film as follows.
The structure of the gate insulating film of each thin film transistor used in the experiment is the structure of only the first metal oxide layer 12A (film thickness of 80 nm), the structure of the second metal oxide layer 12B (film thickness of 80 nm), The two-layer structure of the metal oxide layer 12A (film thickness 50 nm) and the second metal oxide layer 12B (film thickness 50 nm), and the first metal oxide layer 12A (film thickness 50 nm) and the second metal A three-layer structure in which an intermediate layer 12C (thickness 3 nm) is disposed between the oxide layer 12B (thickness 50 nm) is employed. The interface state density was measured immediately after film formation and after annealing (500 ° C.).

  Table 3 shows the interface state density obtained by the above measurement.

  As shown in Table 3, the two-layer structure and the three-layer structure have a lower interface state density after the annealing process than the case where the gate insulating film is a single film, and are preferable values as thin film transistor characteristics. That is confirmed. It is confirmed that the interface state density when the gate insulating film has the three-layer structure is lower than that in the two-layer structure, and is a more preferable value. This is because a large amount of hydrogen atoms contained in the intermediate layer 12C move to the interface between the active layer 11 and the first metal oxide layer 12A by the annealing process, and terminate the dangling bond, thereby further increasing the interface state. It is thought that the unit density was lowered. Thereby, the thin film transistor 2 can obtain more excellent switching characteristics.

  In addition, it is considered that the second metal oxide layer 12B was involved as a hydrogen barrier layer in this result. Specifically, the second metal oxide layer 12B acts as a hydrogen barrier layer, and hydrogen atoms contained in the intermediate layer 12C are annealed to the interface between the active layer 11 and the first metal oxide layer 12A. It becomes easy to move. Thereby, it becomes possible to enhance the defect repair effect of the interface.

Next, the film thickness of the intermediate layer 12C will be considered. In the thin film transistor 2 according to the present embodiment, the thickness of the first metal oxide layer 12A and the second metal oxide layer 12B is fixed to 50 nm, and the thickness of the intermediate layer 12C is set to 0 nm to 30 nm. The interface state density Dit (eV ⁻¹ · cm ⁻² ) was measured.

  FIG. 16 and Table 4 show the interface state density obtained by the above measurement.

  From FIG. 16, it is confirmed that the interface layer density of the intermediate layer 12C is lowered even when the thickness is 3 nm. As the film thickness of the intermediate layer 12C increases, the interface state density further decreases, and it is confirmed that the interface state density becomes the minimum value at the film thickness of 10 nm in Example 3-3. On the other hand, when the film thickness of the intermediate layer 12C exceeds 10 nm, it is confirmed that the interface state density does not decrease. Therefore, it can be seen that the intermediate layer 12C has a function of supplying hydrogen atoms sufficiently with an extremely thin film thickness of 3 nm or more and 10 nm or less.

  Subsequently, a thin film transistor characteristic (TFT characteristic) value was measured in a thin film transistor in which the structure of the gate insulating film was changed as follows. The structure of the gate insulating film of each thin film transistor includes a structure of only the first metal oxide layer 12A (film thickness of 100 nm), the first metal oxide layer 12A (film thickness of 50 nm) and the second metal oxide layer 12B ( A two-layer structure (thin film transistor 1) having a thickness of 50 nm) and an intermediate layer 12C (thickness 50 nm) between the first metal oxide layer 12A (thickness 50 nm) and the second metal oxide layer 12B (thickness 50 nm). A three-layer structure (thin film transistor 2) in which a film thickness of 10 nm) is arranged.

As TFT characteristic values, mobility (cm ² / Vs) and subthreshold swing value (S value) (V / dec) were measured. The TFT characteristics were measured after the annealing process (500 ° C.) of each thin film transistor.

  Table 5 shows the mobility and S value obtained by the above measurement.

From Table 5, it is confirmed that the mobility is improved and the S value is small in the two-layer structure or the three-layer structure as compared with the case where the gate insulating film has a single-layer structure.
Why the mobility is improved is higher than the dielectric constant of _Al 2 _{O 3} deposited by ALD (about 7.5) is the dielectric constant of the TEOS-SiO _X (approximately 4.5), TEOS-SiO _X This is presumably because the equivalent oxide thickness becomes thinner than that of a single film, and more carriers can be generated at the same voltage. Further, due to the hydrogen barrier effect of Al ₂ O _{3 formed} by ALD, hydrogen in the film terminates not only the interface but also defects in the film, thereby eliminating unnecessary charges in the TEOS-SiO _X film, Similarly, it is considered to generate more carriers at the same voltage.

Next, the reason why the S value is improved is that, as described above, the second metal oxide layer 12B functions as a hydrogen barrier layer, and the hydrogen atoms in the first metal oxide layer 12A are activated layer-gate. This is because the interface state density is reduced by effectively repairing defects at the insulating film interface.
In particular, when the gate insulating film has a three-layer structure, since it has the intermediate layer 12C, the interface state density is further reduced by a large amount of hydrogen atoms in the intermediate layer 12C, and the S value becomes a particularly preferable value. Yes.

  As described above, according to the present embodiment, since a good coverage and uniformity of the gate insulating film can be obtained, a thin film transistor having excellent TFT characteristics can be obtained.

<Third Embodiment>
FIG. 17 is a schematic cross-sectional view of a thin film transistor 3 according to the third embodiment of the present invention. Hereinafter, configurations different from those of the first embodiment will be mainly described, and configurations similar to those of the above-described embodiment will be denoted by the same reference numerals, and description thereof will be omitted or simplified.

  In the thin film transistor 3 of the present embodiment, the gate insulating film 32 includes a first intermediate oxide layer 12D disposed between the first metal oxide layer 12A and the second metal oxide layer 12B. Different from the embodiment.

  The intermediate layer 12D is a hydrogen-rich layer containing a large amount of hydrogen atoms, and is formed by performing hydrogen plasma treatment on the first metal oxide layer 12A. The intermediate layer 12D has the same effect as the intermediate layer 12C of the second embodiment. The thickness of the intermediate layer 12D is not particularly limited, and is, for example, 3 nm or more and 10 nm or less.

  Next, a method for forming the intermediate layer 12D will be described. In this embodiment, the gate insulating film forming step includes an intermediate layer forming step after the first metal oxide layer forming step. The active layer formation step, source region and drain region formation step, gate electrode formation step, interlayer insulating film formation step, and source electrode and drain electrode formation step are the same as in the first embodiment. The description is omitted here.

  The intermediate layer 12D is formed by performing hydrogen plasma treatment on the surface of the first metal oxide layer 12A. After the formation of the intermediate layer 12D, annealing is performed at a predetermined temperature (for example, 500 ° C.). The annealing treatment may be performed before or after the formation of the second metal oxide layer 12B. However, in order to efficiently supply the hydrogen atoms contained in the intermediate layer 12D to the interface between the active layer 11 and the first metal oxide layer 12A, an annealing process is performed after the formation of the second metal oxide layer 12B. It is desirable to implement. The intermediate layer 12D may disappear by diffusing into the first metal oxide layer 12A after the annealing treatment.

  The apparatus for performing the hydrogen plasma process is not particularly limited as long as the apparatus can perform the hydrogen plasma process on the surface of the first metal oxide layer 12A. The plasma apparatus may be configured to apply a bias potential to the electrode on the substrate to be processed during the hydrogen plasma process.

The film formation conditions are not particularly limited. For example, when the glass substrate size is 730 mm × 920 mm, the film formation is performed under the following conditions.
H ₂ flow rate: 1000 [sccm]
Process pressure: 200 [Pa]
RF frequency: 27.12 [MHz]
RF power: 500 [W]
Heater temperature: 350 [° C]

  Also in the present embodiment, the same operational effects as those in the first and second embodiments described above can be obtained.

  As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, a various change can be added.

  For example, the plasma CVD apparatus and the ALD apparatus used in the above embodiments are not limited to the above-described apparatuses, and other apparatuses may be used.

  In the above embodiment, the first metal oxide layer forming step and the second metal oxide layer forming step may be performed by a single wafer multi-chamber system or an in-line system.

  When each of the above steps is performed by a single wafer multi-chamber system, a plasma CVD chamber is formed after the first metal oxide layer is formed in the first chamber (plasma CVD chamber for forming the first metal oxide layer). The substrate to be processed is taken out from the substrate and transferred to the next second chamber (ALD chamber for forming the second metal oxide layer) to perform substrate processing one by one.

  Or when performing each said process by an in-line system, for example, while conveying a to-be-processed substrate by conveyance means, such as a walking beam and various conveyors, the 1st processing chamber (1st metal) divided in the conveyance direction Substrate processing is performed in each of a second processing chamber (having an ALD apparatus for forming a second metal oxide layer) and a next second processing chamber (having a plasma CVD apparatus for forming an oxide layer).

  In the single wafer multi-chamber system or the in-line system, the first metal oxide layer forming step and the second metal oxide layer forming step may be continuously performed in a vacuum atmosphere. . Thus, it is possible to prevent contamination of the substrate surface by gas or air by making the substrate processing step consistent in vacuum.

  In the above embodiment, the present invention has been described by taking a top gate type (stagger type) thin film transistor as an example. However, the gate electrode is disposed on the substrate, and the gate insulating film is sandwiched between the gate electrode and the gate electrode. The present invention can be applied even to a thin film transistor having a bottom gate type (reverse stagger type) structure in which layers are arranged.

  The thin film transistor described above can be used as a TFT for an active matrix display panel such as a liquid crystal display or an organic EL display. In addition, the transistor can be used as a transistor element in various semiconductor devices or electronic devices.

DESCRIPTION OF SYMBOLS 1, 2, 3 ... Thin-film transistor 10 ... Board | substrate 11 ... Active layer 12, 22, 32 ... Gate insulating film 12A ... 1st metal oxide layer 12B ... 2nd metal oxide layer 12C, 12D ... Intermediate | middle layer 13 ... Gate Electrode 14S ... Source region 14D ... Drain region

Claims (10)

Forming an active layer on the substrate;
Forming a source region and a drain region so as to be electrically connected to the active layer;
Forming a first metal oxide layer made of silicon oxide on the surface of the active layer by plasma CVD;
Forming a second metal oxide layer made of aluminum oxide on the surface of the first metal oxide layer by ALD;
A method for manufacturing a thin film transistor, wherein a gate electrode is formed on a surface of the second metal oxide layer. A method of manufacturing a thin film transistor according to claim 1,
Forming a hydrogen-rich intermediate layer between the first metal oxide layer and the second metal oxide layer;
And a step of annealing the intermediate layer. A method of manufacturing a thin film transistor. A method of manufacturing a thin film transistor according to claim 2,
A method of manufacturing a thin film transistor, wherein the intermediate layer is formed by performing hydrogen plasma treatment on the first metal oxide layer. A method of manufacturing a thin film transistor according to claim 2,
A method of manufacturing a thin film transistor, wherein the intermediate layer is formed by forming a silicon nitride or silicon oxynitride layer between the first and second metal oxide layers. A method of manufacturing a thin film transistor according to claim 4,
The step of forming the first metal oxide layer and the step of forming the silicon nitride or silicon oxynitride layer are performed in the same chamber. A method of manufacturing a thin film transistor according to any one of claims 1 to 5,
The method of forming a thin film transistor, wherein the step of forming the first metal oxide layer and the step of forming the second metal oxide layer are continuously performed in a vacuum atmosphere. A gate electrode;
An active layer made of polysilicon;
A source region and a drain region electrically connected to the active layer;
A first metal oxide layer made of silicon oxide and disposed between the gate electrode and the active layer; an aluminum oxide layer disposed between the first metal oxide layer and the gate electrode; A thin film transistor comprising: a second metal oxide layer comprising: a gate insulating film. The thin film transistor according to claim 7,
The gate insulating film further includes an intermediate layer including silicon nitride between the first metal oxide layer and the second metal oxide layer. The thin film transistor according to claim 7,
The gate insulating film further includes an intermediate layer including silicon oxynitride between the first metal oxide layer and the second metal oxide layer. The thin film transistor according to claim 8 or 9,
The thickness of the intermediate layer is 3 nm or more and 10 nm or less.

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