JP4023367B2

JP4023367B2 - Semiconductor film forming method and semiconductor film manufacturing method

Info

Publication number: JP4023367B2
Application number: JP2003116061A
Authority: JP
Inventors: 光敏宮坂
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 1993-09-08
Filing date: 2003-04-21
Publication date: 2007-12-19
Anticipated expiration: 2022-12-19
Also published as: JP2004006830A

Description

【０００１】
【産業上の利用分野】
本発明はアクティブマトリックス液晶ディスプレイ等に応用される薄膜トランジスタや三次元ＬＳＩデバイスなどで使用されている絶縁性物質上に形成される半導体膜の形成方法、或いは薄膜半導体装置の製造方法に関するもので有り、詳しくは製造工程の最高温度が６００℃程度以下の低温プロセスで形成する薄膜半導体装置の製造方法に関する。
【０００２】
又、本発明は非酸化性雰囲気下にて行われる基板熱処理方法及び化学気相堆積法に関する。
【０００３】
【従来の技術】
近年、液晶ディスプレイの大画面化、高解像度化に伴い、その駆動方式は単純マトリックス方式からアクティブマトリックス方式へ移行し、大容量の情報を表示出来るように成りつつ有る。アクティブマトリックス方式は数十万を越える画素を有する液晶ディスプレイが可能で有り、各画素毎にスイッチングトランジスタを形成するもので有る。各種液晶ディスプレイの基板としては、透過型ディスプレイを可能ならしめる溶融石英板やガラスなどの透明絶縁基板が使用されている。
【０００４】
しかしながら、表示画面の拡大化や低価格化を進める場合には絶縁基板として安価な通常ガラスを使用するのが必要不可欠で有る。従って、この経済性を維持して尚、アクティブマトリックス方式の液晶ディスプレイを動作させる薄膜トランジスタを安価なガラス基板上に安定した性能で容易に形成する事が可能な技術が望まれていた。
【０００５】
薄膜トランジスタのチャンネル部半導体膜としては、通常非晶質シリコンや多結晶シリコンが用いられているが、駆動回路迄一体化して薄膜トランジスタで形成しようとする場合には動作速度の速い多結晶シリコンが有利である。
【０００６】
従来この様な薄膜トランジスタやそれらに用いられる半導体膜を安価なガラスを基板として使用し得る低温プロセスで作成する場合、非晶質半導体膜形成後窒素雰囲気下にて６００℃で８時間から２４時間程度以上の時間熱処理を施していた。（Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．３０，Ｐ３７２４，１９９１やＩＥＥＥＥｌｅｃｔｒｏｎＤｅｖ．Ｌｅｔｔ．１２，Ｐ５８４，１９９１，Ｊ．Ｅｌｅｃｔｒｏｃｈｅｍ．Ｓｏｃ．１３６，Ｐ１１６９，１９８９など。）或いは半導体膜形成後レ−ザ−照射を施していた。（Ｅｘｔ．Ａｂｓ．ＳｏｌｉｄＳｔａｔｅＤｅｖｉｃｅｓａｎｄＭａｔｅｒｉａｌｓ１９９１Ｐ．６３８やＪａｐ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．３０，３７００（１９９１）など。）又、従来非酸化性雰囲気下にて基板を熱処理したり、或いは化学気相堆積する際は基板挿入の為にロードロック室を設けて炉内に混入する空気等の不純物気体量を少なくしていた。
【０００７】
【発明が解決しようとする課題】
しかしながら、先に述べた従来の方法に於いては、以下の如き問題が指摘されている。まずレ−ザ−照射による薄膜半導体装置の作成に関しては装置が窮めて高価で非実用的で有る事に加え、レーザーショット毎の変動が大きく、大面積に均一に薄膜半導体装置を作成し得ない。又基板加熱をし、一枚一枚レ−ザ−照射する等の生産性の悪さも指摘されている。一方熱処理を施す方法では次の様な問題が指摘されている。即ち、熱処理に依り結晶化された多結晶半導体膜（以後これを固相成長膜、或いはＳＰＣ膜と略記する。）はその結晶粒内部におびただしき数の欠陥が存在している為、そのままでは半導体膜品質が悪く使用し得ない。例えばＳＰＣ膜を薄膜トランジスタの能動層半導体膜として用いる場合、ゲート絶縁膜の形成を電子サイクロトロン共鳴プラズマＣＶＤ法（ＥＣＲ−ＰＥＣＶＤ）法にて作成するか、又は他の方法でゲート絶縁膜を形成して薄膜トランジスタを完成させた後に水素プラズマ照射等の水素化処理を施さねばならなかった。しかるにＥＣＲ−ＰＥＣＶＤ装置は非常に高価で有る上、定期的に分解して反応炉内の清掃を行わなければならず、薄膜トランジスタを用いた液晶ディスプレイやＬＳＩ装置の製品価格の高騰を招いたり、生産性の低下をもたらしていた。又、他の方法でゲート絶縁膜を形成し、最後に水素化処理を施す製法は工程が煩雑と化し、しかも水素化処理条件の調整が困難で、数十万個に及ぶ薄膜トランジスタの性能を均一に整えるのが非常に難しいとの問題が有る。
【０００８】
したがってＥＣＲ−ＰＥＣＶＤ装置を使用せず、しかも水素化処理も施さない簡単な製造方法で高品質な半導体膜を形成する方法、或いは薄膜半導体装置を製造する方法が求められていた。更に駆動回路まで一体化して薄膜トランジスタで形成する場合、高解像度化に伴う画素数の増加は駆動回路の高速動作を要求している。或いは液晶ディスプレイの消費電力を下げたり、液晶ディスプレイの外部回路等を廉価な汎用ＩＣで構成する為に、駆動回路の電源電圧を下げる事が求められている。これらの課題はより低い電圧でより高いオン電流を有する薄膜トランジスタに依り解決される。即ち、従来よりも少しでも優れた薄膜トランジスタが常に求められている訳である。
【０００９】
本発明は上記の事情に鑑みてなされた物でその目的とするところは、結晶性半導体膜の形成、及び良好な特性を有する薄膜半導体装置を大面積に均一にしかも簡便に製造する方法を提供する事にある。或いは本発明はオン状態の電圧が同じ場合により高いオン電流を有する薄膜半導体装置を大面積に均一に製造する方法を提供する事にある。
【００１０】
又、従来は熱処理炉や反応炉にロードロック室を設けて真空引きを行った後基板挿入していた為、熱処理炉や反応炉が大きくなったり価格高騰する上、１バッチごと真空引きするとの煩雑な工程を要していた。
【００１１】
本発明は上記の事情に鑑みてなされた物でその目的とするところは、不純物気体の混入が無く簡単な熱処理方法や化学気相堆積方法を提供する事に有る。
【００１２】
【課題を解決するための手段】
本発明の半導体膜形成方法は、少なくとも表面が絶縁性物質で有る基板上に多結晶半導体膜を形成する半導体膜形成方法であって、前記基板上に非晶質半導体膜を形成する第一の工程と、前記非晶質半導体膜が形成された基板を酸素分圧が５ｍｔｏｒｒから５０ｔｏｒｒの範囲である酸化性雰囲気下において熱処理することにより前記非晶質半導体膜を結晶化して前記多結晶半導体膜とする第二の工程と、を有することを特徴とする。
【００１３】
本発明の半導体膜形成方法は、少なくとも表面が絶縁性物質で有る基板上に多結晶半導体膜を形成する半導体膜形成方法であって、前記基板上に非晶質半導体膜を形成する第一の工程と、前記非晶質半導体膜が形成された基板を気体分圧が１ｍｔｏｒｒから１０ｔｏｒｒの範囲である笑気ガス、水、または二酸化炭素の雰囲気下において熱処理することにより、前記非晶質半導体膜を結晶化して前記多結晶半導体膜とする第二の工程と、を有することを特徴とする。
【００１４】
上記の半導体膜形成方法において、前記第二の工程の前に前記非晶質半導体膜表面から自然酸化膜を除去する工程を有する事が好ましい。
【００１５】
上記の半導体膜形成方法において、前記第二の工程の前に前記非晶質半導体膜表面から自然酸化膜を除去する工程を有する事が好ましい。
【００１６】
上記の半導体膜形成方法において、前記結晶性半導体膜を構成する元素にシリコンを含む事が好ましい。
【００２３】
［実施例］
（実施例１）
以下本発明の実施例を詳述するが、本発明が以下の実施例に限定されるものでは無い。
【００２４】
図２ａ〜ｄは本実施例１に於ける自己整合型スタガード構造のＭＩＳ型電界効果トランジスタを構成するシリコン薄膜半導体装置の製造工程を断面で示した図で有る。
【００２５】
本実施例１では、下地基板２０１として２３５ｍｍ□の溶融石英ガラスを用いたが、６００℃の工程最高温度に耐え得る基板又は下地物質で有るならば、その種類や大きさは無論問われない。例えば通常ガラス基板の他にシリコンウェハーなどの半導体基板及びそれらを加工したＬＳＩ、三次元ＬＳＩや、或いはシリコン・カーバイト、アルミナ、窒化アルミニウムなどのセラミックス基板なども下地基板として可能で有る。
【００２６】
まずアセトン又はメチル・エチル・ケトン，メチル・イソ・ブチル・ケトンやシクロヘキサノンなどの有機溶剤中に下地基板２０１を浸し、超音波洗浄を行う。洗浄後窒素中又は減圧下にて乾燥を施し、更にエタノールによる超音波洗浄を行った後窒素バブリングされている純水にて水洗を施す。次に下地基板２０１を沸騰している濃度６０％の硝酸中に５分間浸し、更に窒素バブリングされている純水中で洗浄した。基板として金属など酸に依り腐食されたり、変質して仕舞う物質を用いる場合、この硝酸に依る洗浄は必要とされない。又この強酸に依る洗浄では酸として硝酸の他に硫酸なども可能で有る。
【００２７】
こうして洗浄された石英基板上に常圧気相化学堆積法（ＡＰＣＶＤ法）で下地保護膜となる二酸化硅素膜（ＳｉＯ₂膜）２０２を２０００Å堆積した。この下地ＳｉＯ₂膜２０２は前述の如き種々多様な物質を基板として用いる際、後に堆積される半導体膜の膜質、及びそれを用いて構成される薄膜トランジスタの性能を安定化する為に必要で有る。と同時に、例えば基板２０１として通常ガラスを用いた場合、ガラス中に含まれているナトリウムなどの可動イオンが、又基板２０１として各種セラミック板を用いた際には基板中に添加されている焼結助材原料などがトランジスタ部に拡散混入するのを防ぐ役割をも演じている。又金属板を基板２０１として用いる場合は、絶縁性を確保する為に下地ＳｉＯ₂は必要不可欠で有る。又、三次元ＬＳＩ素子では、トランジスタ間や配線間の層間絶縁膜に相当している。下地ＳｉＯ₂膜２０２堆積時の基板温度は３００℃で、窒素に依り２０％に希釈されたシラン６００SCCMを８４０SCCMの酸素と共にＡＰＣＶＤ法で堆積した。この時のＳｉＯ₂膜の堆積速度は３．９Å／ｓｅｃで有った。
【００２８】
次に減圧ＣＶＤ法でいずれ能動層となる非晶質半導体膜を堆積した。本実施例１では半導体膜としてシリコンを用いたが、シリコン・ゲルマニウムやガリウム・ヒ素、シリコン・カーバイト、ダイヤモンド等他の半導体も可能で有る。
【００２９】
半導体膜堆積に用いた減圧ＣＶＤ反応炉の容積は１８４．５ｌで、基板は反応炉中央付近に水平に置かれる。原料ガス及びヘリウム・窒素・アルゴン・水素等の希釈ガスは必要に応じて反応炉下部より炉内に導入され、反応炉上部から排気される。石英ガラスで作られた反応炉の外側には３ゾーンに分かれたヒーターが設置されて居り、それらを独立に調整する事で反応炉内中央部付近に所望の温度で均熱帯を形成する。この均熱帯は約３５０ｍｍの高さで広がり、その範囲内での温度のずれは、例えば６００℃に設定した時０．２℃以内である。従って挿入基板間の間隔を１０ｍｍとすれば１バッチで３５枚の基板の処理が可能で有る。本実施例１では２０ｍｍ間隔で１７枚の基板を均熱帯内に設置した。
【００３０】
排気はロータリーポンプとメカニカル・ブースターポンプを直結して行い、反応炉内の圧力は測定値がガスの種類に依存しない隔膜式圧力計（ＭＫＳ社バラトロン・マノメーター）に依り測定した。反応炉を５５０℃に保って、ガス導入用のバルブを閉じて両ポンプにて真空引きを行った場合、反応炉内圧は０mtorrで有る為、背景真空度は悪くとも１０^-4torr程度以下で有る。
【００３１】
半導体膜を堆積すべき基板は、表側を下向きとして減圧ＣＶＤ炉内に挿入された。挿入時の反応炉内温度は３９５℃から４００℃程度で有った。基板挿入時に反応炉内には上部より純度が９９・９９９９％以上のヘリウムと水素の混合気体が３００００ SCCM導入され、これらの混合気体は反応炉下部に設けられた基板挿入口より排出されて居る。基板挿入口の直径は５４０ｍｍでその断面積は２２９０ｃｍ²で有る。混合気体が４００℃に熱せられていると、基板挿入口からの混合気体の排出速度は２９．６ｃｍ／ｍｉｎとなる。又、本実施例１の如く２３５ｍｍ□の基板を水平に設置する場合、基板面積は５５２ｃｍ²で有るから基板が基板挿入口より反応炉内に入っていく時に基板挿入口と基板の隙間から排出される混合気体の排出速度は３９．０ｃｍ／ｍｉｎで有る。本実施例１では１０ｃｍ／ｍｉｎの上昇速度で基板を反応炉に挿入したが、混合気体の排出速度の方が速い為、基板挿入に伴う空気等の反応室への混入を防ぐ事が出来る。又、混合気体の密度は空気密度よりも小さく、しかも熱せられているので重い空気がこれらの軽い気体を押し退けて下から上へ入る可能性は殆ど無い。本実施例１で反応炉上部より導入した混合気体の濃度はヘリウム９７％に水素３％で有った。水素の爆発下限界は４．０％なので、これ以下の濃度で有れば基板挿入口より室内に排出されても安全で有る。こうした基板挿入方法を用いる事に依り、ロードロック室を用いて１バッチ毎に真空引きを行うといった煩雑な過程を経る事無くして、反応炉内を清浄な非酸化性雰囲気下に保てられるので有る。基板挿入時に空気や水等の不純物気体が反応炉内に流れ込むと、これらは反応炉内壁の半導体層に吸着し、又は半導体元素と反応して反応炉内に残留し、半導体膜堆積の際脱ガスとして現れ、堆積膜の膜品質を低下させる原因となる。従って本発明の基板挿入を用いたＣＶＤ方法では容易に高品質半導体膜が堆積されるので有る。
【００３２】
基板挿入後、真空引き、漏洩検査を施した。漏洩検査では反応炉に通ずる全バルブを閉じて反応炉を完全に孤立させて、反応炉内圧力の変化を調べた。本実施例１では反応炉内温度が４００℃で２分間の完全孤立後、反応炉内圧力は１mtorr以下で有った。漏洩検査にて異常が無い事を確認した後、反応炉内温度を挿入温度の４００℃から堆積温度まで昇温する。本実施例１では５５０℃でチャンネル部となる半導体膜を堆積した為、昇温するのに一時間費やした。炉内温度が堆積温度の５５０℃に達するには３５分間程度で済むが、反応炉壁からの脱ガスを充分放出する為にも、最短一時間以上、好ましくは二時間から三時間程度の昇温期間が望ましい。この昇温期間中、二つのポンプは運転状態に有り、少なくとも純度が９９．９９５％以上の不活性又は還元性ガスを流し続ける。これらのガス種は水素・ヘリウム・窒素・ネオン・アルゴン・キセノン・クリプトン等の純ガスの他、これらのガスの混合ガスも可能で有る。本実施例１では純度９９．９９９９％以上のヘリウムを３５０SCCM流し続け、反応炉内圧力は８１±１．２mtorrで有った。
【００３３】
堆積温度到達後、原料ガスで有る所定量のシラン又はシランと希釈ガスの混合ガスを反応炉内に導入し、非晶質半導体膜を堆積する。希釈ガスとしては、先の昇温期間に流したガスと同種の組み合わせが可能で有るが、望ましくは各ガスの純度はそれぞれが９９．９９９％以上が良い。本実施例１では希釈ガスを用いず、純度９９．９９９％以上のシランを１００SCCM流して非晶質半導体膜を堆積した。堆積時に於ける反応炉内の圧力は反応炉とメカニカル・ブースターポンプの間に設置されたコンダクタンスバルヴの開閉度を調整して４００mtorrに保った。本実施例１では非晶質半導体膜は２２Å／ｍｉｎの堆積速度で２５０Åの膜厚に堆積した。
【００３４】
本実施例１では非晶質半導体膜の堆積をＬＰＣＶＤ法で行い、原料ガスもモノシランを用いたが、これ以外にもプラズマＣＶＤ法や光ＣＶＤ法、ＡＰＣＶＤ等の各種ＣＶＤ法やスパッター法、蒸着法等各種ＰＶＤ法等で堆積する事も可能で有る。又原料ガスもモノシランに限らず、ジシランやトリシランなどの高次シランやジクロールシラン或いはゲルマンやメタンなども可能で有る。又、無論上記種々のＣＶＤ法と上記種々の原料の組み合わせに依って非晶質半導体膜を堆積する事も可能で有る。
【００３５】
次にこうして得られた基板を１．６７％弗化水素酸水溶液に２０秒間浸して非晶質半導体膜表面から自然酸化膜を取り除いた。その後基板は直ちに弱酸化性雰囲気下に設置され、熱処理を施された。
【００３６】
熱処理炉は縦型炉で通常４００℃に保たれて居り、純度９９．９９９％以上の窒素を３００００ SCCMと純度９９．９９９％以上の酸素を３００SCCM流し続けて熱処理炉内部を弱酸化性雰囲気としている。従って熱処理炉内の酸素分圧はおよそ７．６ torrとなる。熱処理炉の容積は１８４．５ｌで有る。基板は縦型炉下部より熱処理炉内に挿入されるが、窒素と酸素は熱処理炉上部より炉内に導入され下部の挿入口より流出している。室温と温度平衡に達している基板は弱酸化性雰囲気で４００℃の炉に挿入された。基板挿入後熱処理炉の温度を一時間かけて６００℃まで上げ、その後６００℃にて１５時間維持した。この熱処理に依り非晶質半導体膜は結晶化して多結晶半導体膜へと固体状態を変える。非晶質膜を構成していた半導体元素が多結晶状態へと移動すると原子密度の減少及び空間移動に関する自由度の低さに起因して、出来上がった多結晶粒内部には必然的におびただしき数の欠陥や不対電子が発生する。ところが本発明が示す所に依ると、この様な欠陥及び不対電子は酸素と結合して、終端されるので有る。熱処理時の酸素分圧が高過ぎると、欠陥等を終端すべき酸素原子が半導体膜内部に迄取り込まれて半導体膜品質を劣化させてしまう。同時に非晶質から多結晶へと半導体膜が状態変化を起こす前に非晶質表面に数十Å程度の酸化膜が形成されてしまい、結晶成長が行われて欠陥や不対電子が沢山生じた後では、表面酸化膜の存在に依り欠陥終端する酸素が十分供給されないので有る。反対に熱処理時の酸素分圧が低過ぎるとやはり欠陥終端すべき酸素数が不足し、効果は十分現れない。弱酸化性雰囲気を酸素に依り作り出す場合、酸素分圧は５mtorrから５０torr程度が好ましい。最適酸素分圧は熱処理温度や時間に依っても変化するが、５００℃〜７００℃の処理温度で１００時間以内の処理時間に対しては１０mtorrから１０torr程度がより好ましく、更に好ましくは２０mtorrから５torr程度である。最適分圧は半導体膜材質に依っても決定される。シリコン・ゲルマニウムの様にシリコンに比べて酸化が速い半導体膜材料では最適酸素分圧範囲は低圧側にシフトされる。例えば純粋なゲルマニウム膜では酸素分圧は０．５mtorrから５torr程度が好ましく、より好ましくは１mtorrから1torr、更に好ましくは２mtorrから５００mtorr程度である。この最適酸素分圧はシリコン・ゲルマニウム（Ｓｉ_xＧｅ_1-x）中のシリコン原子の割合（ｘ値）比例して定まる。例えばＳｉ_0.5Ｇｅ_0.5（ｘ＝０．５）に対しては酸素分圧は２．７５mtorrから２７．５torr程度が好ましく、より好ましくは５．５mtorrから５．５torr、更に好ましくは１１mtorrから２．７５torr程度となる。又、笑気ガス（Ｎ₂Ｏ）や水（Ｈ₂Ｏ）二酸化炭素（ＣＯ₂）を用いる場合は反応が速いので、それらの気体分圧は酸素分圧の値の１／５程度となる。例えば、シリコンに対する酸素分圧が５mtorrから５０torrの範囲に相当するそれらの気体分圧はおよそ１mtorrから１０torr程度が好ましい。熱処理温度は５００℃から７００℃程度の間が使用される。結晶成長をゆっくり大きくさせるとの観点からは低温の方が好ましいが、結晶化に長時間費やす。本実施例１の様に６００℃にて熱処理を施す場合は１０時間で結晶化はほぼ完了するが、５５０℃とすると熱処理時間は１００時間以上となり、又７００℃とすると１時間程度で済む。熱処理温度はこうした長短より決められるが、好ましくは５３０℃程度から６７０℃程度、更に好ましくは５５０℃から６５０℃程度、より好ましくは５７０℃程度から６３０℃程度で有る。
【００３７】
こうして得られた半導体膜は、レジストでパターニングされた後、四弗化炭素（ＣＦ₄）と酸素（Ｏ₂）の混合プラズマに依りエッチングされ、能動層半導体膜２０３を形成した（図２ａ）。本実施例１で形成した半導体膜はＣＦ₄とＯ₂の比が５０SCCM対１００SCCMで有る１５Ｐａの真空プラズマ放電で、その出力が７００Ｗの時のエッチングでは２．０Å／ｓｅｃのエッチング速度を有していた。
【００３８】
次にこの基板を沸騰している濃度６０％の硝酸にて洗浄しＡＰＣＶＤ法にてゲート絶縁膜となるＳｉＯ₂膜２０４を１５００Å堆積した（図２ｂ）。ＡＰＣＶＤ法にてゲート絶縁膜を堆積する時の基板温度は３００℃で、窒素に依り２０％に希釈されたシラン３００SCCMと３００SCCMの酸素を流してＳｉＯ₂膜を堆積した。本実施例１ではＡＰＣＶＤ法を用いたが、これ以外にもプラズマＣＶＤ法、光ＣＶＤ法、ＬＰＣＶＤ法等の各種ＣＶＤ法やスパッタ法等のＰＶＤ法も有効で有る。又、原材料もシランに限らずＴＥＯＳ｛Ｓｉ−（ＣＨ₃−ＣＨ₂−Ｏ−）₄｝等の有機シリコン化合物も利用し得る。無論ＥＣＲ−ＰＥＣＶＤ法を用いても良い。
【００３９】
次にタンタルをスパッター法で堆積し、パターニングに依り、ゲート電極２０５を形成した。本実施例１ではゲート電極材料としてタンタルを用いたが、無論これ以外の導電性物質も可能で有るし、又その形成方法もスパッター法に限らず蒸着法やＣＶＤ法なども可能で有る。ゲート電極作成後、ゲート電極をマスクとしてドナー又はアクセプターとなる元素をイオン注入２０６し、ソース・ドレイン領域２０７及びチャンネル領域２０８を作成した（図２Ｃ）。本実施例１ではＮＭＯＳトランジスタ作成を目指し、水素希釈された５％フォスフィンを質量非分離型イオン注入装置にて打ち込んだ。加速電圧は１１０ｋｖで水素原子を含む総イオン打ち込み量は１．０×１０¹⁶ｃｍ^-2で有った。続いてＡＰＣＶＤ法で層間絶縁膜２０９となるＳｉＯ₂膜を５０００Å堆積した。この堆積は本実施例１で下地ＳｉＯ₂膜２０２を堆積した条件と全く同一で唯一堆積時間のみを変えて行った。層間絶縁膜形成後、注入イオンの活性化と層間絶縁膜の焼き締めを兼ねて、窒素中で３００℃１時間の熱処理を施した。熱処理後のソース・ドレイン領域のシート抵抗値は９５％の信頼係数で（９３±２２）ｋΩ／□で有った。本実施例１ではイオン注入を質量非分離型イオン注入装置で行い、３００℃の低温熱処理に依り注入イオンの活性化を行ったが、これに限らず例えば通常の質量分離型イオン注入装置にてイオン注入し、レーザー照射に依り活性化しても良い。その後コンタクトホールを開け、ソース・ドレイン取り出し電極２１０をスパッター法などで形成し、トランジスタが完成する（図２ｄ）。本実施例１ではソース・ドレイン取り出し電極材料としてアルミニウムを用いスパッター法で８０００Åの膜厚に堆積して、ソース・ドレイン取り出し電極を形成した。この時堆積アルミニウム膜のシート抵抗は４２．５±２．０ｍΩ／□で有った。
【００４０】
この様にして試作した薄膜トランジスタ（ＴＦＴ）の特性を温度２５℃で測定した。トランジスタサイズはチャンネル部の長さＬ＝１０μｍ、幅Ｗ＝１０μｍで有った。Ｖｄｓ＝４ｖで得られた結果を図１のＡに示す。ＳＰＣ膜中の欠陥や不対電子が終端された事実を反映して、オフ状態（Ｖｇｓ＜−５ｖ）からオン状態（Ｖｇｓ＞０ｖ）への立ち上がりが急峻となり、最小電流値（Ｖｇｓ＝−４ｖ）も小さい良好な薄膜半導体装置が得られた。又、水素化処理が一切行われていない分だけ工程は簡略化し、しかも大型基板内及び基板間で均質な薄膜半導体装置が製造された。
【００４１】
これに対して従来技術ではその様な良好な薄膜半導体装置を作成し得ない。以下本発明の優位性を明瞭と化す為に従来技術との比較を行う。従来技術と本発明の違いは非晶質半導体膜の熱処理方法で有る。従来技術では非晶質半導体膜形成後、大気圧窒素雰囲気下で熱処理を行っていた。即ち純窒素雰囲気下４００℃の熱処理炉に基板を挿入した後１時間費やして６００℃まで温度を上げ、その後６００℃にて１５時間維持した。従来技術で熱処理を施された基板は以下本実施例１の本発明と同一の工程を経て薄膜トランジスタを完成せられた。こうして従来技術で製造された薄膜半導体装置のトランジスタ特性を図１のｄに示す。この比較例が示す様に従来技術の熱処理で、ゲート絶縁膜をＥＣＲ−ＰＥＣＶＤ法以外の方法（例えばこの比較例が用いたＡＰＣＶＤ法）で形成し、水素化処理を施さないと、オフ電流が高く、スイッチング特性の優れぬ薄膜半導体装置と化してしまう。又、比較例のソース・ドレイン領域のシート抵抗は９５％の信頼係数で（１８２±６２）ｋΩ／□で有った。本発明が従来技術に比してソース・ドレイン領域のシート抵抗を下げる原因も、優良な薄膜半導体装置を製造し得る理由も、本発明に依り半導体膜中の欠陥が補修されたり、不対電子が酸素で終端された為、電子等のキャリアの欠陥及び不対電子等との非弾性散乱が減った事や、結晶粒界及び結晶粒内での捕獲準位数が減ったが故で有る。この様に本発明に依り良質な半導体膜が得られ、これらにドナー又はアクセプターとなる不純物を添加すると低抵抗の電気伝導膜が得られ、又これらを能動層半導体膜として用いると優良な薄膜半導体装置が得られるので有る。
【００４２】
（参考例１）
非晶質半導体膜の結晶化を進める熱処理方法を除いて、その他の工程は総て実施例１に記載した本発明と同一の製造方法で薄膜半導体装置を作成した。本参考例１では減圧下不活性雰囲気にて非晶質半導体膜の結晶化を進めた後、連続して酸化性雰囲気に熱処理炉内環境を変えて良質な結晶性半導体膜を得た。
【００４３】
実施例１に詳述した手法で非晶質半導体膜を堆積された基板は１．６７％弗化水素酸水溶液に２０秒間浸され、非晶質半導体膜表面から自然酸化膜を取り除いた。その後基板は直ちに不活性雰囲気下に設置され、熱処理を施された。
【００４４】
熱処理炉は縦型炉で４００℃に保たれており、純度９９．９９９％以上の窒素２００００ SCCMと純度９９．９９９９％以上のヘリウム１００００ SCCMが熱処理炉上部より熱処理炉に導入され、下部基板挿入口より排出されて居る。本参考例１の様に縦型炉で下側より基板挿入する場合、空気よりも軽い不活性気体を上方から下方に流す事に依り、空気や水等の不純物気体の混入を防ぐ事が出来、熱処理炉内を完全な不活性雰囲気に保つ事が出来る。
【００４５】
基板挿入後、真空引きを行い、熱処理炉内に純度９９．９９９％以上の窒素２００SCCMと純度９９．９９９％以上のヘリウム１００SCCMを流し続け、熱処理炉内の圧力を１０torrに保った。基板挿入時の酸素等の混入は殆ど無く、常時不活性ガスが流れ続けているので、窒素中の不純物が総て酸素で有ると厳しく仮定しても熱処理炉内の酸素分圧は０．１mtorr以下で有る。窒素の純度９９．９９９％以上とは簡易測定の測定限界を示す物で、通常は純度はもっと高い。従って熱処理炉内の酸素分圧はどんなに高くとも０．１mtorrを超える事は有り得ず、０．０５mtorr以下で有る。
【００４６】
熱処理炉内の酸素分圧を０．１mtorr以下、好ましくは０．０５mtorr以下、より好ましくは０．０１mtorr以下にした後、熱酸化炉の温度を１時間掛けて６００℃まで上げ、その後その状態で１２時間維持した。この熱処理に依り非晶質半導体膜は結晶化して多結晶状態へと固体状態を変えるが、半導体原子の移動等に伴う欠陥や不対電子が結晶粒界や膜表面に多数存在して居る。１２時間の熱処理後、６００℃の温度に維持したまま、不活性気体の供給を止め反応炉内に純度９９．９９９％以上の酸素を導入し、７６０ torrとした。この６００℃、７６０ torr純酸素雰囲気下で更に連続して３時間の熱処理を施した。この酸素雰囲気化での熱処理時間に於ける酸素分圧は７．６ torr から７６ torrが好ましい。圧力が高くなると安全上の問題が生じ、逆に低いと酸素による欠陥終端が遅くなり生産性の妨げとなる。従ってより好ましくは２２８ torrから５３２０ torrが酸素分圧として適しており、更に好ましくは５３２ torrから２２８０ torrで有る。熱処理温度は５００℃から７００℃程度の間が使用される。結晶成長をゆっくり大きくさせるとの観点からは低温の方が好ましいが、結晶化に長時間費やす。本参考例１の様に６００℃にて熱処理を施す場合は１０時間で結晶化はほぼ完了するが、５５０℃とすると熱処理時間は１００時間以上となり、又７００℃とすると１時間程度で済む。熱処理温度はこうした長短より決められるが、好ましくは５３０℃程度から６７０℃程度、更に好ましくは５５０℃から６５０℃程度、より好ましくは５７０℃程度から６３０℃程度で有る。
【００４７】
こうして得られた多結晶半導体膜を用いて以下実施例１の本発明と全く同じ工程にて薄膜半導体装置を作成した。得られたトランジスタ特性を図１−ｂに示す。従来技術と比較する迄も無く、実施例１の発明に比べても更に優良な特性となっている事が分かる。又、本参考例１で作成された薄膜半導体装置のソース・ドレイン領域のシート抵抗は９５％の信頼係数で（８５±２０）ｋΩ／□で有った。本参考例１で実施例１の発明よりも良質な半導体膜が得られたのは、実施例１が弱酸化性雰囲気下で結晶成長と酸化皮膜の形成が競争過程で有ったのに対し、本参考例１では酸素分圧を０．１mtorr以下として酸化皮膜の成長を完全に押さえ、結晶成長した後に酸素に依る欠陥等を終端した為、実施例１の発明に比べてより効果的に欠陥補修がなされたので有る。本参考例１では熱処理中の酸素分圧を低くする為に１０torrの減圧下で熱処理を施し、その後酸素分圧７６０ torrで熱処理したが、熱処理温度が６００℃程度で有れば酸素分圧は１０mtorr程度以下で有れば殆ど酸化は進まないから、大気圧不活性雰囲気下で第一の熱処理をした後、酸化性雰囲気で第二の熱処理を施しても良い。この場合、第一の熱処理時の窒素純度は９９．９９９％以上で有れば十分で有る。又、第一の不活性雰囲気下での熱処理時に流す気体も窒素・ヘリウムに限られず、ネオン・アルゴン・クリプトン・キセノン等の希ガス単体又はこれらの混合気体で有っても良い。更に第二の酸化性雰囲気下での熱処理時に流す気体も酸素に限られず、笑気ガス・水・二酸化炭素等の酸化性気体やこれらの混合気体、更には酸化性気体と不活性気体の混合気体で有っても良い。
【００４８】
（参考例２）
非晶質半導体膜の結晶化を進める熱処理方法を除いて、その他の工程は全て実施例１に記載した本発明と同一の製造方法で薄膜半導体装置を作成した。本参考例２では減圧下還元性雰囲気にて非晶質半導体膜の結晶化を進めた後、連続して酸化性雰囲気に熱処理炉内環境を変えて良質な結晶性半導体膜を得た。
【００４９】
実施例１に詳述した手法で非晶質半導体膜を堆積された基板は１．６７％弗化水素酸水溶液に２０秒間浸され、非晶質半導体膜表面から自然酸化膜を取り除いた。その後基板は直ちに還元性雰囲気下に設置され、熱処理を施された。
【００５０】
熱処理炉は縦型炉で４００℃に保たれて居り、純度９９．９９９９％以上の水素５００SCCMと純度９９．９９９９％以上のヘリウム２００００ SCCMが熱処理炉上部より熱処理炉に導入され、下部基板挿入口より排出されて居る。本参考例２の様に縦型炉で下側より基板挿入する場合、空気よりも軽い還元性気体を上方から下方に流す事に依り、空気や水等の不純物気体の混入を防ぐ事が出来、熱処理炉内を完全な還元性雰囲気に保つ事が出来る。
【００５１】
基板挿入後、真空引きを行い、熱処理炉内に純度９９．９９９９％以上の水素２００SCCMと純度９９．９９９９％以上のヘリウム１００SCCMを流し続け、熱処理炉内の圧力を１０torrに保った。従って水素分圧は６．７torrで有る。その後熱処理炉の温度を１時間掛けて６００℃に上げ、続いてその状態で１２時間維持した。次に熱処理炉の温度を６００℃に保ったまま熱処理炉内を３分間真空引きし、更に純度９９．９９９９％以上のヘリウムを３００SCCM３分間流した後、再度３分間の真空引きを行い、その後熱処理炉に純度９９．９９９％以上の酸素を導入して７６０ torrとした。この６００℃、純酸素７６０ torrの雰囲気下で更に連続して３時間の熱処理を施した。還元性雰囲気に於ける熱処理の場合、水素分圧は０．１mtorrから７６００ torr程度が好ましいが、実用的には０．１torrから７６０ torr程度が好ましく、更には１torrから７６ torrが最適で有る。連続して行われる酸化性雰囲気下での熱処理時に於ける酸素分圧は７６ torrから７６００ torrが好ましい。圧力が高くなると安全上の問題が生じ、逆に低いと酸素に依る欠陥終端が遅くなり生産性の妨げとなる。従ってより好ましくは２２８ torrから５３２０ torrが酸素分圧として適しており、更に好ましくは５３２ torrから２２８０ torrで有る。熱処理温度は５００℃から７００℃程度の間が使用される。結晶成長をゆっくり大きくさせるとの観点からは低温の方が好ましいが、結晶化に長時間費やす。本参考例２の様に６００℃にて熱処理を施す場合は１０時間で結晶化はほぼ完了するが、５５０℃とすると熱処理時間は１００時間以上となり、又７００℃とすると１時間程度で済む。熱処理温度はこうした長短より決められるが、好ましくは５３０℃程度から６７０℃程度、更に好ましくは５５０℃から６５０℃程度、より好ましくは５７０℃程度から６３０℃程度で有る。
【００５２】
こうして得られた多結晶半導体膜を用いて以下実施例１の本発明と全く同じ工程にて薄膜半導体装置を作成した。得られたトランジスタ特性を図１のＣに示す。参考例１と同様、優良な特性を有する薄膜半導体装置が得られた。本参考例２で作成された薄膜半導体装置のソース・ドレイン領域のシート抵抗値は９５％の信頼係数で（８４±１７）ｋΩ／□で有った。本参考例２でも還元性雰囲気下で結晶成長を行い、酸化皮膜の形成を完全に押さえ、結晶成長終了後酸素に依る欠陥補修を効果的に行い得た事に基づき、良質な半導体膜が得られた。尚、本参考例２での還元性雰囲気下での熱処理は減圧下で行われたが、これは常圧で有っても構わない。又還元性気体も水素に限られず、アンモニア等も可能で有る。無論酸化性気体も酸素に限られず、参考例１に述べた酸化性気体も有効で有る。
【００５３】
（参考例３）
図３ａ〜ｄは本参考例３に於ける自己整合型スタガード構造のＭＩＳ型電界効果トランジスタを構成するシリコン薄膜半導体装置の製造工程を断面で示した図で有る。
【００５４】
本参考例３では、下地基板３０１として２３５ｍｍ□の溶融石英ガラスを用いたが、６００℃の工程最高温度に耐え得る基板又は下地物質で有るならば、その種類や大きさは無論問われない。例えば通常ガラス基板の他にシリコンウェハーなどの半導体基板及びそれらを加工したＬＳＩ、三次元ＬＳＩや、或いはシリコン・カーバイト、アルミナ、窒化アルミニウムなどのセラミックス基板なども下地基板として可能で有る。
【００５５】
まずアセトン又はメチル・エチル・ケトン，メチル・イソ・ブチル・ケトンやシクロヘキサノンなどの有機溶剤中に下地基板３０１を浸し、超音波洗浄を行う。洗浄後窒素中又は減圧下にて乾燥を施し、更にエタノールによる超音波洗浄を行った後窒素バブリングされている純水にて水洗を施す。次に下地基板３０１を沸騰している濃度６０％の硝酸中に５分間浸し、更に窒素バブリングされている純水中で洗浄した。基板として金属など酸に依り腐食されたり、変質して仕舞う物質を用いる場合、この硝酸に依る洗浄は必要とされない。又この強酸に依る洗浄では酸として硝酸の他に硫酸なども可能で有る。
【００５６】
こうして洗浄された石英基板上に常圧気相化学堆積法（ＡＰＣＶＤ法）で下地保護膜となる二酸化硅素膜（ＳｉＯ₂膜）３０２を２０００Å堆積した。この下地ＳｉＯ₂膜３０２は前述の如き種々多様な物質を基板として用いる際、後に堆積される半導体膜の膜質、及びそれを用いて構成される薄膜トランジスタの性能を安定化する為に必要で有る。と同時に、例えば基板３０１として通常ガラスを用いた場合、ガラス中に含まれているナトリウムなどの可動イオンが、又基板３０１として各種セラミック板を用いた際には基板中に添加されている焼結助材原料などがトランジスタ部に拡散混入するのを防ぐ役割をも演じている。又金属板を基板３０１として用いる場合は、絶縁性を確保する為に下地ＳｉＯ₂は必要不可欠で有る。又、三次元ＬＳＩ素子では、トランジスタ間や配線間の層間絶縁膜に相当している。下地ＳｉＯ₂膜３０２堆積時の基板温度は３００℃で、窒素に依り２０％に希釈されたシラン６００SCCMを８４０SCCMの酸素と共にＡＰＣＶＤ法で堆積した。この時のＳｉＯ₂膜の堆積速度は３．９Å／ｓｅｃで有った。
【００５７】
次に減圧ＣＶＤ法でいずれ能動層となる非晶質半導体膜を堆積した。本参考例３では半導体膜としてシリコンを用いたが、シリコン・ゲルマニウムやガリウム・ヒ素等他の半導体も可能で有る。
【００５８】
半導体膜堆積に用いた減圧ＣＶＤ反応炉の容積は１８４．５ｌで、基板は反応炉中央付近に水平に置かれる。原料ガス及びヘリウム・窒素・アルゴン・水素等の希釈ガスは必要に応じて反応炉下部より炉内に導入され、反応炉上部から排気される。石英ガラスで作られた反応炉の外側には３ゾーンに分かれたヒーターが設置されて居り、それらを独立に調整する事で反応炉内中央部付近に所望の温度で均熱帯を形成する。この均熱帯は約３５０ｍｍの高さで広がり、その範囲内での温度のずれは、例えば５００℃に設定した時０．２℃以内である。従って挿入基板間の間隔を７ｍｍとすれば１バッチで５０枚の基板の処理が可能で有る。本参考例３では２０ｍｍ間隔で１７枚の基板を均熱帯内に設置した。
【００５９】
排気はロータリーポンプとメカニカル・ブースターポンプを直結して行い、反応炉内の圧力は測定値がガスの種類に依存しない隔膜式圧力計（ＭＫＳ社バラトロン・マノメーター）に依り測定した。反応炉を５５０℃に保って、ガス導入用のバルブを閉じて両ポンプにて真空引きを行った場合、反応炉内圧は０mtorrで有る為、背景真空度は悪くとも１０^-4torr程度以下で有る。
【００６０】
半導体膜を堆積すべき基板は、表側を下向きとして減圧ＣＶＤ炉内に挿入された。挿入時の反応炉内温度は３９５℃から４００℃程度で有った。基板挿入時に反応炉内には上部より純度が９９・９９９９％以上のヘリウムと水素の混合気体が３００００ SCCM導入され、これらの混合気体は反応炉下部に設けられた基板挿入口より排出されて居る。基板挿入口の直径は５４０ｍｍでその断面積は２２９０ｃｍ²で有る。混合気体が４００℃に熱せられていると、基板挿入口からの混合気体の排出速度は２９．６ｃｍ／ｍｉｎとなる。又、本参考例３の如く２３５ｍｍ□の基板を水平に設置する場合、基板面積は５５２ｃｍ²で有るから基板が基板挿入口より反応炉内に入っていく時に基板挿入口と基板の隙間から排出される混合気体の排出速度は３９．０ｃｍ／ｍｉｎで有る。本参考例３では２０ｃｍ／ｍｉｎの上昇速度で基板を反応炉に挿入したが、混合気体の排出速度の方が速い為、基板挿入に伴う空気等の反応室への混入を防ぐ事が出来る。又、混合気体の密度は空気密度よりもはるかに小さく、しかも熱せられているので重い空気がこれらの軽い気体を押し退けて下から上へ入る可能性は殆ど無い。本参考例３で反応炉上部より導入した混合気体の濃度はヘリウム９７％に水素３％で有った。水素の爆発下限界は４．０％なので、これ以下の濃度で有れば基板挿入口より室内に排出されても安全で有る。こうした基板挿入方法を用いる事に依り、ロードロック室を用いて１バッチ毎に真空引きを行うといった煩雑な過程を経る事無くして、反応炉内を清浄な非酸化性雰囲気下に保てられるので有る。基板挿入時に空気や水等の不純物気体が反応炉内に流れ込むと、これらは反応炉内壁の半導体層に吸着し、又は半導体元素と反応して反応炉内に残留し、半導体膜堆積の際、脱ガスとして現れ、堆積膜の膜品質を低下させる原因となる。従って本発明の基板挿入を用いたＣＶＤ方法では容易に高品質半導体膜が堆積されるので有る。
【００６１】
基板挿入後、真空引き、漏洩検査を施した。漏洩検査では反応炉に通ずる全バルブを閉じて反応炉を完全に孤立させて、反応炉内圧力の変化を調べた。本参考例３では反応炉内温度が４００℃で２分間の完全孤立後、反応炉内圧力は１mtorr以下で有った。漏洩検査にて異常が無い事を確認した後、反応炉内温度を挿入温度の４００℃から堆積温度まで昇温する。本参考例３では５１０℃でチャンネル部となる半導体膜を堆積した為、昇温するのに一時間費やした。炉内温度が堆積温度の５１０℃に達するには３５分間程度で済むが、反応炉壁からの脱ガスを充分放出する為にも、最短一時間以上、好ましくは数時間の昇温期間が望ましい。この昇温期間中、二つのポンプは運転状態に有り、少なくとも純度が９９．９９５％以上の不活性又は還元性ガスを流し続ける。これらのガス種は水素・ヘリウム・窒素・ネオン・アルゴン・キセノン・クリプトン等の純ガスの他、これらのガスの混合ガスも可能で有る。本参考例３では純度９９．９９９９％以上のヘリウムを３５０SCCM流し続け、反応炉内圧力は８１±１．２mtorrで有った。
【００６２】
堆積温度到達後、原料ガスで有る所定量のシラン又はシランと希釈ガスの混合ガスを反応炉内に導入し、非晶質半導体膜を堆積する。希釈ガスとしては、先の昇温期間に流したガスと同種の組み合わせが可能で有るが、望ましくは各ガスの純度はそれぞれが９９．９９９％以上が良い。本参考例３では希釈ガスを用いず、純度９９．９９９％以上のシランを２００SCCM流して非晶質半導体膜を堆積した。堆積時に於ける反応炉内の圧力は反応炉とメカニカル・ブースターポンプの間に設置されたコンダクタンスバルヴの開閉度を調整して、１．０torrに保った。本参考例３では非晶質半導体膜は２０Å／ｍｉｎの堆積速度で２５０Åの膜厚に堆積した。
【００６３】
本参考例３では非晶質半導体膜の堆積をＬＰＣＶＤ法で行い、原料ガスもモノシランを用いたが、これ以外にもプラズマＣＶＤ法や光ＣＶＤ法、ＡＰＣＶＤ等の各種ＣＶＤ法やスパッター法、蒸着法等各種ＰＶＤ法等で堆積する事も可能で有る。又原料ガスもモノシランに限らず、ジシランやトリシランなどの高次シランやジクロールシラン或いはゲルマンなども可能で有る。又、無論上記種々のＣＶＤ法と上記種々の原料の組み合わせに依って非晶質半導体膜を堆積する事も可能で有る。
【００６４】
こうして得られた非晶質半導体膜は、レジストでパターニングされた後、四弗化炭素（ＣＦ₄）と酸素（Ｏ₂）の混合プラズマに依りエッチングされ、いずれ能動層となる非晶質半導体膜３０３を形成した（図３ａ）。本参考例３で形成した非晶質半導体膜はＣＦ₄とＯ₂の比が５０SCCM対１００SCCMで有る１５Ｐａの真空プラズマ放電で、その出力が７００Ｗの時のエッチングでは２．２Å／ｓｅｃのエッチング速度を有していた。
【００６５】
次にこの基板を沸騰している濃度６０％の硝酸にて洗浄しＡＰＣＶＤ法にてゲート絶縁膜となるＳｉＯ₂膜３０４を１５００Å堆積した。ＡＰＣＶＤ法にてゲート絶縁膜を堆積する時の基板温度は３００℃で窒素に依り２０％に希釈されたシラン３００SCCMと３００SCCMの酸素を流してＳｉＯ₂膜を堆積した。本参考例３ではＡＰＣＶＤ法を用いたが、これ以外にもプラズマＣＶＤ法、光ＣＶＤ法、ＬＰＣＶＤ法等の各種ＣＶＤ法やスパッタ法等のＰＶＤ法も有効で有る。又、原材料もシランに限らずＴＥＯＳ｛Ｓｉ−（ＣＨ₃−ＣＨ₂−Ｏ−）₄｝等の有機シリコン化合物も利用し得る。無論ＥＣＲ−ＰＥＣＶＤ法を用いても良い。
【００６６】
次にこうして得られた基板を９７℃の硫酸にて洗浄し、その後基板は直ちに酸化性雰囲気下に設置され、熱処理を施された。
【００６７】
熱処理炉は縦型炉で通常４００℃に保たれて居り、純度９９．９９９％以上の酸素を３００００ SCCM流し続けて熱処理炉内部を酸化性雰囲気としている。従って熱処理炉内の酸素分圧はおよそ７６０ torrとなる。熱処理炉の容積は１８４．５ｌで有る。基板は縦型炉下部より熱処理炉内に挿入されるが、酸素は熱処理炉上部より炉内に導入され下部の挿入口より流出している。室温と温度平衡に達している基板は酸化性雰囲気で４００℃の炉に挿入された。基板挿入後熱処理炉の温度を一時間かけて６００℃まで上げ、その後６００℃にて１５時間維持した。この熱処理に依り非晶質半導体膜は結晶化して多結晶半導体膜へと固体状態を変える。非晶質膜を構成していた半導体元素が多結晶状態へと移動すると原子密度の減少及び空間移動に関する自由度の低さに起因して、出来上がった多結晶粒内部には必然的におびただしき数の欠陥や不対電子が発生する。ところが本発明が示す所に依ると、この様な欠陥及び不対電子は酸素と結合して終端されるので有る。一般に６００℃程度の温度に於ける酸素のＳｉＯ₂の拡散は非常に遅い。特にシリコンを酸化して得られるＳｉＯ₂は稠密で有る為膜厚が数十Åも有るとＳｉとＳｉＯ₂の界面（以後これをＭＯＳ界面と呼ぶ）への酸素供給量はかなり限定される。従ってもし稠密なＳｉＯ₂膜がＳｉ上に１５００Åの厚みで形成されていれば、６００℃、７６０ torr、十数時間の熱処理ではＭＯＳ界面に酸素は殆ど供給されない。ところが本参考例３に於いてはゲート絶縁膜となるＳｉＯ₂膜がＣＶＤ法により堆積された空疎な膜で有る為、Ｓｉ表面に形成された数十Å未満の稠密な自然酸化膜までは酸素は自由に供給されるので有る。稠密で酸素拡散係数の小さいＳｉＯ₂の膜厚が数十Å程度未満で有る事に依り、６００℃で７６０ torr程度で有ってもＭＯＳ界面に酸素が供給され、結晶成長に伴って発生した欠陥や不対電子は効果的に終端されるので有る。更にＣＶＤ法等で堆積されたＳｉＯ₂膜には未反応Ｓｉ原子やＳｉ−Ｈ基、Ｓｉ−ＯＨ基、及び不対電子等が沢山残っている。これらの未反応物はＳｉＯ₂中の電荷となってトランジスタのしきい値電圧（Ｖｔｈ）を大きくしたり、界面電荷（Ｑｓｓ）を増大させ、良好な特性を生じさせぬ原因となる。又、これらの未反応物は化学的に不安定で有るので、薄膜半導体装置を作成した際、半導体装置の経時安定性を損なう事となる。即ち、稠密で安定的な熱酸化膜に比べて、ＣＶＤＳｉＯ₂膜は劣っているので有る。ところが本参考例３では半導体膜の結晶化促進と同時に、酸素熱処理によるゲート酸化膜の反応促進と稠密化がなされ、酸化膜質を大きく向上させるので有る。この熱処理により酸化膜中に存在していたＳｉ−Ｈ、Ｓｉ−ＯＨ、Ｓｉ−ｅ^-等はＳｉ−Ｏ−Ｓｉと反応が進められ、同時に稠密ともなるので有る。実際１．６７％弗化水素酸水溶液によるＳｉＯ₂のエッチング速度を調べると、熱酸化膜が１．０Å／ｓｅｃでＡＰＣＶＤのＳｉＯ₂膜が２２Å／ｓｅｃで有ったのに対し、ＡＰＣＶＤ膜を酸素熱処理した本発明のエッチング速度は４．３Å／ｓｅｃと大幅に改善されていた。又、従来はＣＶＤＳｉＯ₂膜やそれらの膜を不活性雰囲気下で熱処理したＳｉＯ₂膜に弗化水素酸系の水溶液を用いてコンタクト・ホール開孔等の部分エッチングを施すと図５に示す様なＳｉ−ＳｉＯ₂界面に逆テーパーが生ずる事が頻々と生じていた。これはＳｉとＳｉＯ₂の密着性が悪い為、エッチング液がＳｉとＳｉＯ₂の界面に急速に侵入する事に基づく。これに対して酸素熱処理を施した本発明のＳｉＯ₂膜は反応が促進され、密着性が改善されたが故、逆テーパーは生じず、図６に示す様な順テーパーとなる。コンタクト・ホールを開孔した時に逆テーパーが生ずると断線となり、電気的導通が取れないから、薄膜半導体装置を安定的に沢山製造するには順テーパーは必要不可欠で有る。
【００６８】
本参考例３では酸化性雰囲気の酸素分圧は７６０ torrで有った。酸化性雰囲気を酸素に依り作り出す場合、酸素分圧は３．８ torrから３８００ torr程度が好ましい。より好ましくは７６ torrから３８００ torr、更に好ましくは３８０ torrから２２８０ torr程度で有る。最適分圧は半導体膜材質と熱処理温度に依って決定される。又、笑気ガス（Ｎ₂Ｏ）や水（Ｈ₂Ｏ）を用いる場合はこれらのガス分圧は７．６ torrから７６ torr程度が好ましく、より好ましくは１５．２ torrから７６０ torr、更に好ましくは７６ torrから４５６ torr程度で有る。又、熱処理温度は５００℃から７００℃程度の間が使用される。結晶成長をゆっくり大きくさせるとの観点からは低温の方が好ましいが、結晶化に長時間費やす。本参考例３の様に６００℃にて熱処理を施す場合は１０時間で結晶化はほぼ完了するが、５５０℃とすると熱処理時間は１００時間以上となり、又７００℃とすると１時間程度で済む。熱処理温度はこうした長短より決められるが、好ましくは５３０℃程度から６７０℃程度、更に好ましくは５５０℃から６５０℃程度、より好ましくは５７０℃程度から６３０℃程度で有る。
【００６９】
次にタンタルをスパッター法で堆積し、パターニングに依り、ゲート電極３０６を形成した。本参考例３ではゲート電極材料としてタンタルを用いたが、無論これ以外の導電性物質も可能で有るし、又その形成方法もスパッター法に限らず蒸着法やＣＶＤ法なども可能で有る。ゲート電極作成後、ゲート電極をマスクとしてドナー又はアクセプターとなる元素をイオン注入３０７し、ソース・ドレイン領域３０８及びチャンネル領域３０９を作成した（図３Ｃ）。本参考例３ではＮＭＯＳトランジスタ作成を目指し、水素希釈された５％フォスフィンを質量非分離型イオン注入装置にて打ち込んだ。加速電圧は１１０ｋｖで水素原子を含む総イオン打ち込み量は１．０×１０¹⁶ｃｍ^-2で有った。続いてＡＰＣＶＤ法で層間絶縁膜３１０となるＳｉＯ₂膜を５０００Å堆積した。この堆積は本参考例３で下地ＳｉＯ₂膜３０２を堆積した条件と全く同一で唯一堆積時間のみを変えて行った。層間絶縁膜形成後、注入イオンの活性化と層間絶縁膜の焼き締めを兼ねて、窒素中で３００℃１時間の熱処理を施した。熱処理後のソース・ドレイン領域のシート抵抗値は９５％の信頼係数で（８０±１８）ｋΩ／□で有った。本参考例３ではイオン注入を質量非分離型イオン注入装置で行い、３００℃の低温熱処理に依り注入イオンの活性化を行ったが、これに限らず例えば通常の質量分離型イオン注入装置にてイオン注入し、レーザー照射に依り活性化しても良い。その後コンタクトホールを開け、ソース・ドレイン取り出し電極３１１をスパッター法などで形成し、トランジスタが完成する（図３ｄ）。本参考例３ではソース・ドレイン取り出し電極材料としてアルミニウムを用いスパッター法で８０００Åの膜厚に堆積して、ソース・ドレイン取り出し電極を形成した。この時堆積アルミニウム膜のシート抵抗は４２．５±２．０ｍΩ／□で有った。
【００７０】
この様にして試作した薄膜トランジスタ（ＴＦＴ）の特性を温度２５℃で測定した。トランジスタサイズはチャンネル部の長さＬ＝１０μｍ、幅Ｗ＝１０μｍで有った。ＳＰＣ膜中の欠陥や不対電子が終端され、更にゲート酸化膜質が改善された事実を反映して良好なトランジスタ特性が得られた。実施例１に述べた発明（図１のＡ）及び比較例（図１のＤ）と、参考例１（図１−Ｂ）、参考例２（図１−Ｃ）のトランジスタ特性と共に本参考例３の結果を表１にまとめる。
【００７１】
【表１】

【００７２】
従来技術の比較例と比べる迄もなく、高いオン電流と低いオフ電流が実現されているのが分かる。本発明が従来技術に比してソース・ドレイン領域のシート抵抗を下げる原因も、優良な薄膜半導体装置を製造し得る理由も、本発明に依り半導体膜中の欠陥が補修されたり、不対電子が酸素で終端された為、電子等のキャリアの欠陥及び不対電子等との非弾性散乱が減った事や、結晶粒界及び結晶粒内での捕獲準位数が減ったが故で有る。加えてゲート絶縁膜の品質が上がった為、オン電流が大きくなり同時に最小電流となるゲート電圧（Ｖｇｓｍｉｎ）も０Ｖに近づき、急峻なスイッチング特性が実現したので有る。同時に経時安定性も増し、ＳｉＯ₂膜に開孔されたコンタクト・ホールの逆テーパーも解決されたので有る。
【００７３】
この様に本発明に依り良質な半導体膜が得られ、これらにドナー又はアクセプターとなる不純物を添加すると低抵抗の電気伝導膜が得られ、又これらを能動層半導体膜として用いると優良な薄膜半導体装置が得られるので有る。
【００７４】
（参考例４）
図４ａ〜ｄは本参考例４に於ける自己整合型スタガード構造のＭＩＳ型電界効果トランジスタを構成するシリコン薄膜半導体装置の製造工程を断面で示した図で有る。
【００７５】
本参考例４では、下地基板４０１として２３５ｍｍ□の溶融石英ガラスを用いたが、６００℃の工程最高温度に耐え得る基板又は下地物質で有るならば、その種類や大きさは無論問われない。例えば通常ガラス基板の他にシリコンウェハーなどの半導体基板及びそれらを加工したＬＳＩ、三次元ＬＳＩや、或いはシリコン・カーバイト、アルミナ、窒化アルミニウムなどのセラミックス基板なども下地基板として可能で有る。
【００７６】
まずアセトン又はメチル・エチル・ケトン，メチル・イソ・ブチル・ケトンやシクロヘキサノンなどの有機溶剤中に下地基板４０１を浸し、超音波洗浄を行う。洗浄後窒素中又は減圧下にて乾燥を施し、更にエタノールによる超音波洗浄を行った後窒素バブリングされている純水にて水洗を施す。次に下地基板４０１を沸騰している濃度６０％の硝酸中に５分間浸し、更に窒素バブリングされている純水中で洗浄した。基板として金属など酸に依り腐食されたり、変質して仕舞う物質を用いる場合、この硝酸に依る洗浄は必要とされない。又この強酸に依る洗浄では酸として硝酸の他に硫酸なども可能で有る。
【００７７】
こうして洗浄された石英基板上に常圧気相化学堆積法（ＡＰＣＶＤ法）で下地保護膜となる二酸化硅素膜（ＳｉＯ₂膜）４０２を２０００Å堆積した。この下地ＳｉＯ₂膜４０２は前述の如き種々多様な物質を基板として用いる際、後に堆積される半導体膜の膜質、及びそれを用いて構成される薄膜トランジスタの性能を安定化する為に必要で有る。と同時に、例えば基板４０１として通常ガラスを用いた場合、ガラス中に含まれているナトリウムなどの可動イオンが、又基板４０１として各種セラミック板を用いた際には基板中に添加されている焼結助材原料などがトランジスタ部に拡散混入するのを防ぐ役割をも演じている。又金属板を基板４０１として用いる場合は、絶縁性を確保する為に下地ＳｉＯ₂は必要不可欠で有る。又、三次元ＬＳＩ素子では、トランジスタ間や配線間の層間絶縁膜に相当している。下地ＳｉＯ₂膜４０２堆積時の基板温度は３００℃で、窒素に依り２０％に希釈されたシラン６００SCCMを８４０SCCMの酸素と共にＡＰＣＶＤ法で堆積した。この時のＳｉＯ₂膜の堆積速度は３．９Å／ｓｅｃで有った。
【００７８】
次に減圧ＣＶＤ法でいずれ能動層となる非晶質半導体膜を堆積した。本参考例４では半導体膜としてシリコンを用いたが、シリコン・ゲルマニウムやガリウム・ヒ素等他の半導体も可能で有る。
【００７９】
半導体膜堆積に用いた減圧ＣＶＤ反応炉の容積は１８４．５ｌで、基板は反応炉中央付近に水平に置かれる。原料ガス及びヘリウム・窒素・アルゴン・水素等の希釈ガスは必要に応じて反応炉下部より炉内に導入され、反応炉上部から排気される。石英ガラスで作られた反応炉の外側には３ゾーンに分かれたヒーターが設置されて居り、それらを独立に調整する事で反応炉内中央部付近に所望の温度で均熱帯を形成する。この均熱帯は約３５０ｍｍの高さで広がり、その範囲内での温度のずれは、例えば５００℃に設定した時０．２℃以内である。従って挿入基板間の間隔を５ｍｍとすれば１バッチで７０枚の基板の処理が可能で有る。本参考例４では２０ｍｍ間隔で１７枚の基板を均熱帯内に設置した。
【００８０】
排気はロータリーポンプとメカニカル・ブースターポンプを直結して行い、反応炉内の圧力は測定値がガスの種類に依存しない隔膜式圧力計（ＭＫＳ社バラトロン・マノメーター）に依り測定した。反応炉を５５０℃に保って、ガス導入用のバルブを閉じて両ポンプにて真空引きを行った場合、反応炉内圧は０mtorrで有る為、背景真空度は悪くとも１０^-4torr程度以下で有る。
【００８１】
半導体膜を堆積すべき基板は、表側を下向きとして減圧ＣＶＤ炉内に挿入された。挿入時の反応炉内温度は３９５℃から４００℃程度で有った。基板挿入時に反応炉内には上部より純度が９９・９９９９％以上の窒素と水素の混合気体が３００００ SCCM導入され、これらの混合気体は反応炉下部に設けられた基板挿入口より排出されて居る。基板挿入口の直径は５４０ｍｍでその断面積は２２９０ｃｍ²で有る。混合気体が４００℃に熱せられていると、基板挿入口からの混合気体の排出速度は２９．６ｃｍ／ｍｉｎとなる。又、本参考例４の如く２３５ｍｍ□の基板を水平に設置する場合、基板面積は５５２ｃｍ²で有るから基板が基板挿入口より反応炉内に入っていく時に基板挿入口と基板の隙間から排出される混合気体の排出速度は３９．０ｃｍ／ｍｉｎで有る。本参考例４では５ｃｍ／ｍｉｎの上昇速度で基板を反応炉に挿入したが、混合気体の排出速度の方が速い為、基板挿入に伴う空気等の反応室への混入を防ぐ事が出来る。又、混合気体の密度は空気密度よりも小さく、しかも熱せられているので重い空気がこれらの軽い気体を押し退けて下から上へ入る可能性は殆ど無い。本参考例４で反応炉上部より導入した混合気体の濃度は窒素９７％に水素３％で有った。水素の爆発下限界は４．０％なので、これ以下の濃度で有れば基板挿入口より室内に排出されても安全で有る。こうした基板挿入方法を用いる事に依り、ロードロック室を用いて１バッチ毎に真空引きを行うといった煩雑な過程を経る事無くして、反応炉内を清浄な非酸化性雰囲気下に保てられるので有る。基板挿入時に空気や水等の不純物気体が反応炉内に流れ込むと、これらは反応炉内壁の半導体層に吸着し、又は半導体元素と反応して反応炉内に残留し、半導体膜堆積の際、脱ガスとして現れ、堆積膜の膜品質を低下させる原因となる。従って本発明の基板挿入を用いたＣＶＤ方法では容易に高品質半導体膜が堆積されるので有る。
【００８２】
基板挿入後、真空引き、漏洩検査を施した。漏洩検査では反応炉に通ずる全バルブを閉じて反応炉を完全に孤立させて、反応炉内圧力の変化を調べた。本参考例４では反応炉内温度が４００℃で２分間の完全孤立後、反応炉内圧力は１mtorr以下で有った。漏洩検査にて異常が無い事を確認した後、反応炉内温度を挿入温度の４００℃から堆積温度まで昇温する。本参考例４では４９５℃でチャンネル部となる半導体膜を堆積した為、昇温するのに一時間費やした。炉内温度が堆積温度の４９５℃に達するには３５分間程度で済むが、反応炉壁からの脱ガスを充分放出する為にも、最短一時間以上、好ましくは数時間の昇温期間が望ましい。この昇温期間中、二つのポンプは運転状態に有り、少なくとも純度が９９．９９５％以上の不活性又は還元性ガスを流し続ける。これらのガス種は水素・ヘリウム・窒素・ネオン・アルゴン・キセノン・クリプトン等の純ガスの他、これらのガスの混合ガスも可能で有る。本参考例４では純度９９．９９９９％以上のヘリウムを３５０SCCM流し続け、反応炉内圧力は８１±１．２mtorrで有った。
【００８３】
堆積温度到達後、原料ガスで有る所定量のシラン又はシランと希釈ガスの混合ガスを反応炉内に導入し、非晶質半導体膜を堆積する。希釈ガスとしては、先の昇温期間に流したガスと同種の組み合わせが可能で有るが、望ましくは各ガスの純度はそれぞれが９９．９９９％以上が良い。本参考例４では希釈ガスを用いず、純度９９．９９９％以上のシランを２００SCCM流して非晶質半導体膜を堆積した。堆積時に於ける、反応炉内の圧力は反応炉とメカニカル・ブースターポンプの間に設置されたコンダクタンスバルヴの開閉度を調整して、１．３torrに保った。本参考例４では非晶質半導体膜は１６Å／ｍｉｎの堆積速度で３５０Åの膜厚に堆積した。
【００８４】
本参考例４では非晶質半導体膜の堆積をＬＰＣＶＤ法で行い、原料ガスもモノシランを用いたが、これ以外にもプラズマＣＶＤ法や光ＣＶＤ法、ＡＰＣＶＤ等の各種ＣＶＤ法やスパッター法、蒸着法等各種ＰＶＤ法等で堆積する事も可能で有る。又原料ガスもモノシランに限らず、ジシランやトリシランなどの高次シランやジクロールシラン或いはゲルマンなども可能で有る。又、無論上記種々のＣＶＤ法と上記種々の原料の組み合わせに依って非晶質半導体膜を堆積する事も可能で有る。
【００８５】
こうして得られた非晶質半導体膜は、レジストでパターニングされた後、四弗化炭素（ＣＦ₄）と酸素（Ｏ₂）の混合プラズマに依りエッチングされ、いずれ能動層となる非晶質半導体膜４０３を形成した（図４ａ）。本参考例４で形成した非晶質半導体膜はＣＦ₄とＯ₂の比が５０SCCM対１００SCCMで有る１５Ｐａの真空プラズマ放電で、その出力が７００Ｗの時のエッチングでは２．２Å／ｓｅｃのエッチング速度を有していた。
【００８６】
次にこの基板を沸騰している濃度６０％の硝酸にて洗浄しＥＣＲ−ＰＥＣＶＤ法にてゲート絶縁膜となる酸化膜４０４と窒化膜４０５及び酸化膜４０６を総計で１５００Å堆積した。本参考例４では酸化膜４０４としてはＳｉＯ₂膜を３００Å堆積し、窒化膜４０５として窒化珪素膜（ＳｉＮ_X）を１０００Å連続堆積し、更に酸化膜４０６としてＳｉＯ₂膜を２００Å堆積した。ＥＣＲ−ＰＥＣＶＤ法にてゲート絶縁膜を堆積する時の基板温度は1００℃で三層の絶縁膜を連続堆積した。本参考例４ではＥＣＲ−ＰＥＣＶＤ法に依り原料ガスとしてモノシラン（ＳｉＨ₄）及び酸素（Ｏ₂）、窒素（Ｎ₂）を用いたが、これ以外にも通常のＰＥＣＶＤ法や光ＣＶＤ法等の各種ＣＶＤ法やスパッタ法等のＰＶＤ法も有効で有る。又、原材料もモノシランに限らずジシランやトリシランなどの高次シランやジクロールシラン等の塩化シランやフッ化シラン等のハロゲン化物及びＴＥＯＳ｛Ｓｉ−（ＣＨ₃−ＣＨ₂−Ｏ−）₄｝等の有機シリコン化合物も利用し得る。又、酸化剤や窒化剤としても笑気ガス、水、二酸化炭素、ＮＯ_Xなどの窒素酸化物やアンモニアなどが利用出来る。三層の絶縁膜堆積後酸素イオン（¹⁶Ｏ⁺）を６５ｋｅＶの加速電圧で下側の酸化膜４０４中に打ち込んだ（４０７）。この加速電圧に於ける酸素イオンの飛程は１２５０Åで飛程偏差は３６０Å程度で有る。従って注入イオンの大半は下側の酸化膜４０４中に存在している。打ち込みイオン量は１×１０¹⁴ｃｍ^-2で有った。次にこうして得られた基板を洗浄し、熱処理を施した。この熱処理により非晶質半導体膜４０３は結晶化半導体膜４０８へと固相状態を変える。（図４−ｂ）。本参考例４では酸化性雰囲気下で熱処理を施した。これは上側の酸化膜４０６を参考例３で詳述した様に改善する為で有るが、上側酸化膜４０６の品質はＭＯＳ界面を形成する下側酸化膜４０４ほど重要ではないので、この熱処理雰囲気は特に酸化性に限られる事無く、製造上の都合に応じて自由に設定し得る。
【００８７】
熱処理炉は縦型炉で通常４００℃に保たれて居り、純度９９．９９９％以上の酸素を３００００ SCCM流し続けて熱処理炉内部を酸化性雰囲気としている。従って熱処理炉内の酸素分圧はおよそ７６０ torrとなる。熱処理炉の容積は１８４．５ｌで有る。基板は縦型炉下部より熱処理炉内に挿入されるが、酸素は熱処理炉上部より炉内に導入され下部の挿入口より流出している。室温と温度平衡に達している基板は酸化性雰囲気で４００℃の炉に挿入された。基板挿入後熱処理炉の温度を一時間かけて６００℃まで上げ、その後６００℃にて１５時間維持した。この熱処理に依り非晶質半導体膜は結晶化して多結晶半導体膜へと固体状態を変える。同時に下側酸化膜４０４に注入された酸素イオンは下側酸化膜の未反応物の酸化を促進し、下側酸化膜４０４の膜質及びＭＯＳ界面を改善する。更に非晶質膜を構成していた半導体元素が多結晶状態へと移動すると原子密度の減少及び空間移動に関する自由度の低さに起因して、出来上がった多結晶粒内部には必然的におびただしき数の欠陥や不対電子が発生するが、化学的に活性な注入酸素イオンがＭＯＳ界面及び結晶化半導体膜中に拡散して、この様な欠陥及び不対電子と結合し、終端させるので有る。ＭＯＳ界面近傍の半導体膜中に存在する欠陥や不対電子の濃度は１×１０¹⁷ｃｍ^-3から１×１０¹⁹ｃｍ^-3程度で有る。本参考例４では打ち込み量が１×１０¹⁴ｃｍ^-2で飛程偏差が３６０Å程度で有るから、注入イオン濃度は１．４×１０¹⁹ｃｍ^-3程度となりＳｉＯ₂中の未反応物の反応を促進したり、結晶化半導体膜中の欠陥補正するには十分で有る。酸素イオンは注入量が少なすぎると欠陥修復を十分に行えず、反対に多すぎると余分な酸化膜を形成したり、酸素原子が半導体膜内部にまで取り込まれて半導体膜品質を劣化させてしまう。従って最適注入量は注入後の濃度が１×１０¹⁷ｃｍ^-3から１×１０²⁰ｃｍ^-3、好ましくは１×１０¹⁸ｃｍ^-3から５×１０¹⁹ｃｍ^-3、更に好ましくは５×１０¹⁸ｃｍ^-3から２×１０¹⁹ｃｍ^-3となるもので有る。通常窒化膜４０５中の酸素拡散は非常に遅いので注入酸素原子は酸化膜中から半導体膜方向へのみ拡散するので効果的に酸素を供給し得る。又、供給源が酸化膜中に有って半導体膜中にないので、酸素が不必要に半導体膜中に取り込まれる事がない。酸素イオンが酸化膜中から拡散に依ってＭＯＳ界面や半導体膜に達するにはある程度の時間が必要で、この間に半導体原子の再配例、即ち結晶化が生ずるので、結晶化を妨げる事無く欠陥補修がなされるので有る。熱処理温度は５００℃から７００℃程度の間が使用される。結晶成長をゆっくり大きくさせるとの観点からは低温の方が好ましいが、結晶化に長時間費やす。本参考例４の様に６００℃にて熱処理を施す場合は１０時間で結晶化はほぼ完了するが、５５０℃とすると熱処理時間は１００時間以上となり、又７００℃とすると１時間程度で済む。熱処理温度はこうした長短より決められるが、好ましくは５３０℃程度から６７０℃程度、更に好ましくは５５０℃から６５０℃程度、より好ましくは５７０℃程度から６３０℃程度で有る。
【００８８】
次にタンタルをスパッター法で堆積し、パターニングに依り、ゲート電極４０９を形成した。本参考例４ではゲート電極材料としてタンタルを用いたが、無論これ以外の導電性物質も可能で有るし、又その形成方法もスパッター法に限らず蒸着法やＣＶＤ法なども可能で有る。ゲート電極作成後、ゲート電極をマスクとしてドナー又はアクセプターとなる元素をイオン注入４１０し、ソース・ドレイン領域４１１及びチャンネル領域４１２を作成した（図４Ｃ）。本参考例４ではＮＭＯＳトランジスタ作成を目指し、水素希釈された５％フォスフィンを質量非分離型イオン注入装置にて打ち込んだ。加速電圧は１１０ｋｖで水素原子を含む総イオン打ち込み量は１．０×１０¹⁶ｃｍ^-2で有った。続いてＡＰＣＶＤ法で層間絶縁膜４１３となるＳｉＯ₂膜を５０００Å堆積した。この堆積は本参考例４で下地ＳｉＯ₂膜４０２を堆積した条件と全く同一で唯一堆積時間のみを変えて行った。層間絶縁膜形成後、注入イオンの活性化と層間絶縁膜の焼き締めを兼ねて、窒素中で３００℃１時間の熱処理を施した。熱処理後のソース・ドレイン領域のシート抵抗値は９５％の信頼係数で（５６±１２）ｋΩ／□で有った。本参考例４ではイオン注入を質量非分離型イオン注入装置で行い、３００℃の低温熱処理に依り注入イオンの活性化を行ったが、これに限らず例えば通常の質量分離型イオン注入装置にてイオン注入し、レーザー照射に依り活性化しても良い。その後コンタクトホールを開け、ソース・ドレイン取り出し電極４１４をスパッター法などで形成し、トランジスタが完成する（図４ｄ）。本参考例４ではソース・ドレイン取り出し電極材料としてアルミニウムを用いスパッター法で８０００Åの膜厚に堆積して、ソース・ドレイン取り出し電極を形成した。この時堆積アルミニウム膜のシート抵抗は４２．５±２．０ｍΩ／□で有った。
【００８９】
この様にして試作した薄膜トランジスタ（ＴＦＴ）の特性を温度２５℃で測定した。トランジスタサイズはチャンネル部の長さＬ＝１０μｍ、幅Ｗ＝１０μｍで有った。ＳＰＣ膜中の欠陥や不対電子が酸素イオンで終端された事、下側ゲート酸化膜４０４の膜品質が酸素イオン注入とその後の熱処理で改善された事、上側ゲート酸化膜４０６が酸化性雰囲気下の熱処理で改善された事、及びゲート絶縁膜の中間層に誘電率の大きな窒化珪素膜を用いた事により、トランジスタ特性は大幅に向上した。実際オン電流（Ｖｄｓ＝４Ｖ、Ｖｇｓ＝１５Ｖ）は４．３×１０^-5Ａと従来の比較例の３倍程度にも増大し、Ｉｄｓの最小値もゲート電圧が０Ｖの時となり、その値（ＩOFF：Ｖｄｓ＝４Ｖ、Ｖｇｓ＝０Ｖ）も８．９×１０^-14と良好な値を示した。この結果ゲート電圧１５Ｖの変調に対するオン・オフ比は８．７桁にも達する優れたスイッチング特性を有する薄膜半導体装置が実現された。
【００９０】
尚、本参考例４では下側ゲート酸化膜をＣＶＤ法で堆積して形成したが、酸素イオン注入法及びその後の熱処理で形成する事もできる。この場合、まず非晶質半導体膜４０３を６００Å程度堆積し、パターニングを行う。次いで窒化珪素膜４０５を１０００Å程度と連続して上側酸化珪素膜４０６を２００Å程度堆積した後、非晶質半導体膜と窒化珪素膜の界面に酸素イオンを打ち込む。打ち込み量は下側酸化膜４０４が３００Å程度形成される量で界面よりも窒化膜側に飛程中心が来る様にする。例えば酸素イオンを５５ｋｅＶの加速電圧で打ち込むと、その飛程と飛程偏差はそれぞれ１０７５Åと３２５Å程度で有る。従って飛程中心は界面から１２５Å程窒化膜側に出来、酸素イオンは非晶質半導体膜表面２００Å程度内に分布する。打ち込み量を６．５×１０¹⁷ｃｍ^-2とし、その後熱処理する事で半導体膜表面には３００Å程度の下側酸化膜４０４が形成され、結晶化半導体膜４０８の膜厚は４００Å程度となる。この熱処理も６００℃程度で十数時間程度との前述の熱処理と同じで構わない。以下本参考例４と同じ工程で薄膜半導体装置を作成する。本参考例４では下側酸化膜４０４と窒化膜４０５、上側酸化膜４０６を連続成膜したが、これらの膜を別装置で形成しても良い。その場合、この方法を用いると下側酸化膜４０４の堆積を行わなくて良い分だけ工程は簡略化されるので有る。
【００９１】
この様に本発明に依り良質な半導体膜とＭＯＳ界面及びゲート絶縁膜が得られ、これらにドナー又はアクセプターとなる不純物を添加すると低抵抗の電気伝導膜が得られ、又これらを能動層半導体膜として用いると優良な薄膜半導体装置が得られるので有る。
【００９２】
【発明の効果】
以上述べて来た様に、本発明に依れば、良質な半導体膜をＥＣＲ−ＰＥＣＶＤ装置等の高価で面倒な装置を用いる事無く、通常の簡単な装置でしかも水素化処理を施す事無く簡単に得る事が可能になった。これに依り、優良なトランジスタ特性を有する薄膜半導体装置を大面積に均一に簡便な手法にて形成する事が可能となり、ＬＳＩの多層化や薄膜トランジスタを用いたアクティブマトリックス液晶ディスプレイの高性能化や低価格化を実現すると言う多大な効果を有する。
【００９３】
又、本発明に依り、ロードロック室を用いなくとも熱処理炉内やＣＶＤ装置を清浄に保つ事が可能となり、良質な膜作成等を極めて簡単に行える様になった。これに依りやはりＬＳＩや液晶ディスプレイ等の高性能化や低価額化を実現すると言う多大な効果を有する。
【００９４】
更に本発明により良質な半導体膜とＭＯＳ界面及びゲート絶縁膜が形成され、きわめて優良なトランジスタ特性を有する薄膜半導体装置を大面積に形成する事が可能となり、液晶ディスプレイ等の高性能化や低価額化を実現するという多大な効果を有する。
【図面の簡単な説明】
【図１】本発明の効果を示す図。
【図２】本発明の一実施例を示すシリコン薄膜半導体装置製造の各工程に於ける素子断面図。
【図３】本発明の一実施例を示すシリコン薄膜半導体装置製造の各工程に於ける素子断面図。
【図４】本発明の一実施例を示すシリコン薄膜半導体装置製造の各工程に於ける素子断面図。
【図５】エッチングの逆テーパーを説明する図。
【図６】エッチングの順テーパーを説明する図。
【符号の説明】
２０１…下地基板
２０２…下地保護膜
２０３…半導体膜
２０４…ゲート絶縁膜
２０５…ゲート電極
２０６…イオン注入
２０７…ソース・ドレイン領域
２０８…チャンネル領域
２０９…層間絶縁膜
２１０…ソース・ドレイン取り出し電極
３０１…下地基板
３０２…下地保護膜
３０３…非晶質半導体膜
３０４…ゲート絶縁膜
３０５…結晶化半導体膜
３０６…ゲート電極
３０７…イオン注入
３０８…ソース・ドレイン領域
３０９…チャンネル領域
３１０…層間絶縁膜
３１１…ソース・ドレイン取り出し電極
４０１…下地基板
４０２…下地保護膜
４０３…非晶質半導体膜
４０４…酸化膜
４０５…窒化膜
４０６…酸化膜
４０７…酸素イオン注入
４０８…結晶化半導体膜
４０９…ゲート電極
４１０…イオン注入
４１１…ソース・ドレイン領域
４１２…チャンネル領域
４１３…層間絶縁膜
４１４…ソース・ドレイン取り出し電極[0001]
[Industrial application fields]
The present invention relates to a method for forming a semiconductor film formed on an insulating material used in a thin film transistor or a three-dimensional LSI device applied to an active matrix liquid crystal display or the like, or a method for manufacturing a thin film semiconductor device, Specifically, the present invention relates to a method of manufacturing a thin film semiconductor device formed by a low temperature process in which the maximum temperature of the manufacturing process is about 600 ° C. or less.
[0002]
The present invention also relates to a substrate heat treatment method and a chemical vapor deposition method performed in a non-oxidizing atmosphere.
[0003]
[Prior art]
In recent years, with the increase in screen size and resolution of liquid crystal displays, the driving method has shifted from the simple matrix method to the active matrix method, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmissive display is used.
[0004]
However, in order to increase the display screen and reduce the price, it is essential to use inexpensive ordinary glass as the insulating substrate. Accordingly, there has been a demand for a technique capable of easily forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining this economy.
[0005]
As the channel part semiconductor film of the thin film transistor, amorphous silicon or polycrystalline silicon is usually used. However, when the thin film transistor is integrated with the drive circuit, polycrystalline silicon having a high operation speed is advantageous. is there.
[0006]
Conventionally, when such a thin film transistor and a semiconductor film used for the thin film transistor are formed by a low-temperature process using an inexpensive glass as a substrate, the amorphous semiconductor film is formed at 600 ° C. in a nitrogen atmosphere for about 8 to 24 hours. The heat treatment was performed for the above time. (Jpn. J. Appl. Phys. 30, P3724, 1991, IEEE Electron Dev. Lett. 12, P584, 1991, J. Electrochem. Soc. 136, P1169, 1989, etc.) or laser after semiconductor film formation Irradiated. (Ext. Abs. Solid State Devices and Materials 1991 P.638, Jap. J. Appl. Phys. 30, 3700 (1991), etc.) Conventionally, the substrate is heat-treated in a non-oxidizing atmosphere, or chemically. When vapor deposition is performed, a load lock chamber is provided for inserting a substrate to reduce the amount of impurity gas such as air mixed in the furnace.
[0007]
[Problems to be solved by the invention]
However, the following problems have been pointed out in the conventional method described above. First of all, regarding the production of thin film semiconductor devices by laser irradiation, in addition to the fact that the device is abundant and expensive and impractical, the fluctuation of each laser shot is large, and it is possible to produce a thin film semiconductor device uniformly over a large area. Absent. Further, it has been pointed out that the productivity is low, such as heating the substrate and irradiating the laser one by one. On the other hand, the following problems have been pointed out in the heat treatment method. That is, since a polycrystalline semiconductor film crystallized by heat treatment (hereinafter abbreviated as a solid phase growth film or SPC film) has numerous defects inside the crystal grains, Then, the quality of the semiconductor film is poor and cannot be used. For example, when an SPC film is used as an active layer semiconductor film of a thin film transistor, a gate insulating film is formed by an electron cyclotron resonance plasma CVD method (ECR-PECVD), or a gate insulating film is formed by another method. After the thin film transistor was completed, hydrogenation treatment such as hydrogen plasma irradiation had to be performed. However, the ECR-PECVD equipment is very expensive and must be periodically disassembled to clean the inside of the reactor, leading to a rise in product prices for liquid crystal displays and LSI devices using thin film transistors. It was causing a decline in sex. In addition, a method of forming a gate insulating film by another method and finally performing a hydrogenation treatment makes the process complicated, and it is difficult to adjust the hydrogenation treatment conditions, and the performance of hundreds of thousands of thin film transistors is uniform. There is a problem that it is very difficult to arrange.
[0008]
Accordingly, there has been a demand for a method for forming a high-quality semiconductor film or a method for manufacturing a thin-film semiconductor device by a simple manufacturing method that does not use an ECR-PECVD apparatus and does not perform hydrogenation. Further, in the case where the driving circuit is integrated and formed with thin film transistors, the increase in the number of pixels accompanying the increase in resolution requires high-speed operation of the driving circuit. Alternatively, in order to reduce the power consumption of the liquid crystal display or to configure the external circuit of the liquid crystal display with an inexpensive general-purpose IC, it is required to reduce the power supply voltage of the drive circuit. These problems are solved by a thin film transistor having a higher on-current at a lower voltage. That is, there is a constant demand for thin film transistors that are even better than before.
[0009]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for forming a crystalline semiconductor film and a thin film semiconductor device having good characteristics uniformly over a large area and simply. There is to do. Alternatively, it is an object of the present invention to provide a method for uniformly manufacturing a thin film semiconductor device having a higher on-state current over a large area when the on-state voltage is the same.
[0010]
In addition, since the substrate was inserted after evacuating after providing a load lock chamber in the heat treatment furnace or reaction furnace, the heat treatment furnace or reaction furnace became larger or the price increased, and the vacuum was drawn for each batch. A complicated process was required.
[0011]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a simple heat treatment method and chemical vapor deposition method in which no impurity gas is mixed.
[0012]
[Means for Solving the Problems]
The semiconductor film forming method of the present invention is a semiconductor film forming method for forming a polycrystalline semiconductor film on a substrate having at least a surface made of an insulating material, wherein the first semiconductor film is formed on the substrate. A step of crystallizing the amorphous semiconductor film by heat-treating the substrate on which the amorphous semiconductor film is formed in an oxidizing atmosphere having an oxygen partial pressure in the range of 5 mtorr to 50 torr. And a second step.
[0013]
The semiconductor film forming method of the present invention is a semiconductor film forming method for forming a polycrystalline semiconductor film on a substrate having at least a surface made of an insulating material, wherein the first semiconductor film is formed on the substrate. And heat-treating the substrate on which the amorphous semiconductor film is formed in an atmosphere of laughing gas, water, or carbon dioxide having a gas partial pressure in the range of 1 torr to 10 torr. And a second step of crystallizing the polycrystalline semiconductor film into a polycrystalline semiconductor film.
[0014]
The semiconductor film forming method preferably includes a step of removing a natural oxide film from the surface of the amorphous semiconductor film before the second step.
[0015]
The semiconductor film forming method preferably includes a step of removing a natural oxide film from the surface of the amorphous semiconductor film before the second step.
[0016]
In the above semiconductor film forming method, it is preferable that silicon is contained in the element constituting the crystalline semiconductor film.
[0023]
[Example]
Example 1
Examples of the present invention will be described in detail below, but the present invention is not limited to the following examples.
[0024]
2a to 2d are cross-sectional views showing a manufacturing process of the silicon thin film semiconductor device constituting the MIS field effect transistor having the self-aligned staggered structure in the first embodiment.
[0025]
In the first embodiment, 235 mm □ fused silica glass is used as the base substrate 201. However, as long as it is a substrate or base material that can withstand the maximum process temperature of 600 ° C., the type and size thereof are not limited. For example, in addition to a normal glass substrate, a semiconductor substrate such as a silicon wafer and an LSI obtained by processing them, a three-dimensional LSI, or a ceramic substrate such as silicon carbide, alumina, or aluminum nitride can be used as a base substrate.
[0026]
First, the base substrate 201 is immersed in an organic solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone, and ultrasonic cleaning is performed. After washing, drying is performed in nitrogen or under reduced pressure, and further ultrasonic washing with ethanol is performed, followed by washing with pure water that has been bubbled with nitrogen. Next, the base substrate 201 was immersed for 5 minutes in boiling nitric acid having a concentration of 60%, and further washed in pure water that was bubbled with nitrogen. When a substrate is used that is corroded by an acid such as a metal or is changed in quality, this cleaning with nitric acid is not required. Further, in this cleaning with strong acid, sulfuric acid can be used as an acid in addition to nitric acid.
[0027]
On the quartz substrate thus cleaned, a silicon dioxide film (SiO 2) serving as a base protective film by atmospheric pressure chemical vapor deposition (APCVD).₂2000 liters of (film) 202 was deposited. This base SiO₂The film 202 is necessary to stabilize the film quality of a semiconductor film to be deposited later and the performance of a thin film transistor formed using the film when using various kinds of materials as described above as a substrate. At the same time, for example, when normal glass is used as the substrate 201, movable ions such as sodium contained in the glass are added, and when various ceramic plates are used as the substrate 201, sintering is added to the substrate. It also plays a role in preventing auxiliary materials from diffusing and mixing into the transistor section. When a metal plate is used as the substrate 201, the underlying SiO is used to ensure insulation.₂Is indispensable. In a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors or wirings. Base SiO₂The substrate temperature during deposition of the film 202 was 300 ° C., and silane 600 SCCM diluted to 20% with nitrogen was deposited together with 840 SCCM oxygen by the APCVD method. SiO at this time₂The deposition rate of the film was 3.9 kg / sec.
[0028]
Next, an amorphous semiconductor film to be an active layer was deposited by low pressure CVD. In the first embodiment, silicon is used as the semiconductor film, but other semiconductors such as silicon / germanium, gallium / arsenic, silicon / carbite, and diamond are also possible.
[0029]
The volume of the low pressure CVD reactor used for semiconductor film deposition is 184.5 l, and the substrate is placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, and hydrogen are introduced into the furnace from the lower part of the reaction furnace as necessary, and exhausted from the upper part of the reaction furnace. A heater divided into three zones is installed outside the reaction furnace made of quartz glass, and by adjusting them independently, a soaking zone is formed at a desired temperature near the center of the reaction furnace. This soaking zone spreads at a height of about 350 mm, and the temperature deviation within that range is, for example, within 0.2 ° C. when set to 600 ° C. Therefore, if the distance between the inserted substrates is 10 mm, 35 substrates can be processed in one batch. In Example 1, 17 substrates were installed in the soaking zone at 20 mm intervals.
[0030]
Exhaust was performed by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reactor was measured using a diaphragm type pressure gauge (MKS Baratron Manometer) whose measurement value does not depend on the type of gas. When the reactor is kept at 550 ° C., the gas introduction valve is closed and evacuation is performed with both pumps, the reactor internal pressure is 0 mtorr.^-FourIt is about torr or less.
[0031]
  The substrate on which the semiconductor film was to be deposited was inserted into a low pressure CVD furnace with the front side facing down. The temperature in the reactor at the time of insertion was about 395 ° C to 400 ° C. When the substrate is inserted, a mixed gas of helium and hydrogen with a purity of 99.9999% or more is introduced into the reactor from the top.30000 SCCMThe mixed gas is introduced and discharged from the substrate insertion port provided at the lower part of the reaction furnace. The diameter of the board insertion slot is 540 mm and its cross-sectional area is 2290 cm.²It is. When the mixed gas is heated to 400 ° C., the discharge speed of the mixed gas from the substrate insertion port is 29.6 cm / min. In addition, when a 235 mm square substrate is installed horizontally as in Example 1, the substrate area is 552 cm.²Therefore, when the substrate enters the reaction furnace from the substrate insertion port, the discharge speed of the mixed gas discharged from the gap between the substrate insertion port and the substrate is 39.0 cm / min. In the first embodiment, the substrate is inserted into the reaction furnace at an ascending speed of 10 cm / min. However, since the discharge speed of the mixed gas is higher, it is possible to prevent air and the like from being mixed into the reaction chamber when the substrate is inserted. Moreover, since the density of the mixed gas is smaller than the air density and is heated, there is almost no possibility that heavy air will push these light gases away from the bottom up. The concentration of the mixed gas introduced from the upper part of the reactor in Example 1 was 97% helium and 3% hydrogen. Since the lower limit of hydrogen explosion is 4.0%, it is safe to discharge from the substrate insertion port into the room if the concentration is lower than this. By using such a substrate insertion method, the inside of the reactor can be kept in a clean non-oxidizing atmosphere without going through the complicated process of evacuating every batch using the load lock chamber. Yes. When an impurity gas such as air or water flows into the reaction furnace when the substrate is inserted, these are adsorbed on the semiconductor layer on the inner wall of the reaction furnace or react with semiconductor elements and remain in the reaction furnace, and are removed during semiconductor film deposition. It appears as gas and causes the film quality of the deposited film to deteriorate. Therefore, a high quality semiconductor film is easily deposited by the CVD method using the substrate insertion of the present invention.
[0032]
After inserting the substrate, vacuuming and leakage inspection were performed. In the leak inspection, all valves connected to the reactor were closed and the reactor was completely isolated, and changes in the reactor pressure were examined. In Example 1, the reactor pressure was 1 mtorr or less after complete isolation for 2 minutes at 400 ° C. in the reactor. After confirming that there is no abnormality in the leakage inspection, the temperature in the reactor is raised from the insertion temperature of 400 ° C. to the deposition temperature. In Example 1, since the semiconductor film to be the channel portion was deposited at 550 ° C., it took an hour to raise the temperature. It takes about 35 minutes for the furnace temperature to reach the deposition temperature of 550 ° C. However, in order to sufficiently release the degassed from the reactor wall, the temperature rises for a minimum of one hour or more, preferably about two to three hours. A warm period is desirable. During this temperature raising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995% or more. These gas species can be a pure gas such as hydrogen, helium, nitrogen, neon, argon, xenon, krypton, or a mixed gas of these gases. In Example 1, helium having a purity of 99.9999% or more was continuously supplied at 350 SCCM, and the reactor internal pressure was 81 ± 1.2 mtorr.
[0033]
After reaching the deposition temperature, a predetermined amount of silane, which is a raw material gas, or a mixed gas of silane and dilution gas is introduced into the reaction furnace to deposit an amorphous semiconductor film. As the dilution gas, the same kind of combination as the gas flowed in the previous temperature raising period is possible, but the purity of each gas is preferably 99.999% or more. In Example 1, an amorphous semiconductor film was deposited by flowing 100 SCCM of silane having a purity of 99.999% or more without using a dilution gas. The pressure in the reactor during deposition was kept at 400 mtorr by adjusting the degree of opening and closing of the conductance valve installed between the reactor and the mechanical booster pump. In Example 1, the amorphous semiconductor film was deposited to a thickness of 250 で at a deposition rate of 22 Å / min.
[0034]
In the first embodiment, the amorphous semiconductor film is deposited by LPCVD and monosilane is used as the source gas. In addition to this, various CVD methods such as plasma CVD method, photo CVD method, APCVD, sputtering method, and vapor deposition are used. It is also possible to deposit by various PVD methods. Further, the source gas is not limited to monosilane, and higher order silanes such as disilane and trisilane, dichlorosilane, germane, methane and the like are also possible. Of course, it is possible to deposit an amorphous semiconductor film by a combination of the various CVD methods and the various raw materials.
[0035]
Next, the substrate thus obtained was immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the natural oxide film from the surface of the amorphous semiconductor film. Thereafter, the substrate was immediately placed in a weakly oxidizing atmosphere and subjected to heat treatment.
[0036]
  The heat treatment furnace is a vertical furnace and is usually kept at 400 ° C. Nitrogen with a purity of 99.999% or more is used.30000 SCCMIn addition, 300 SCCM of oxygen having a purity of 99.999% or more is continuously supplied to make the inside of the heat treatment furnace a weak oxidizing atmosphere. Therefore, the oxygen partial pressure in the heat treatment furnace is approximately7.6 torrIt becomes. The volume of the heat treatment furnace is 184.5 l. The substrate is inserted into the heat treatment furnace from the lower part of the vertical furnace, but nitrogen and oxygen are introduced into the furnace from the upper part of the heat treatment furnace and flow out from the lower insertion port. The substrate reaching room temperature and temperature equilibrium was inserted into a 400 ° C. furnace in a weakly oxidizing atmosphere. After inserting the substrate, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained at 600 ° C. for 15 hours. By this heat treatment, the amorphous semiconductor film is crystallized to change the solid state into a polycrystalline semiconductor film. When the semiconductor elements that made up the amorphous film move to a polycrystalline state, the resulting polycrystalline grains will inevitably have a large amount due to a decrease in atomic density and a low degree of freedom in spatial movement. A large number of defects and unpaired electrons are generated. However, according to the present invention, such defects and unpaired electrons are bonded to oxygen and terminated. If the oxygen partial pressure during the heat treatment is too high, oxygen atoms that should terminate defects and the like are taken into the semiconductor film and deteriorate the quality of the semiconductor film. At the same time, an oxide film of several tens of millimeters is formed on the amorphous surface before the semiconductor film undergoes a state change from amorphous to polycrystalline, and crystal growth occurs, resulting in many defects and unpaired electrons. After that, oxygen that terminates the defect is not sufficiently supplied due to the presence of the surface oxide film. On the other hand, if the oxygen partial pressure during heat treatment is too low, the number of oxygen that should be terminated by defects is insufficient, and the effect is not sufficiently exhibited. When the weak oxidizing atmosphere is created by oxygen, the oxygen partial pressure is preferably about 5 to 50 torr. Although the optimum oxygen partial pressure varies depending on the heat treatment temperature and time, it is more preferably about 10 to 10 torr, more preferably 20 to 5 torr for a treatment time within 100 hours at a treatment temperature of 500 ° C. to 700 ° C. Degree. The optimum partial pressure is also determined by the semiconductor film material. In the case of a semiconductor film material that is faster oxidized than silicon, such as silicon / germanium, the optimum oxygen partial pressure range is shifted to the low pressure side. For example, in the case of a pure germanium film, the oxygen partial pressure is preferably about 0.5 to 5 torr, more preferably 1 to 1 torr, and further preferably about 2 to 500 mtorr. The optimum oxygen partial pressure is silicon germanium (Si_xGe_1-x) In proportion to the proportion of silicon atoms (x value). For example, Si_0.5Ge_0.5For (x = 0.5), the oxygen partial pressure is preferably about 2.75 mtorr to 27.5 torr, more preferably about 5.5 mtorr to 5.5 torr, and still more preferably about 11 mtorr to about 2.75 torr. Also, laughing gas (N₂O) and water (H₂O) Carbon dioxide (CO₂) Is fast, the gas partial pressure is about 1/5 of the oxygen partial pressure. For example, the gas partial pressure corresponding to the range of 5 to 50 torr of oxygen relative to silicon is preferably about 1 to 10 torr. The heat treatment temperature is between about 500 ° C and 700 ° C. Although low temperature is preferable from the viewpoint of increasing crystal growth slowly, it takes a long time for crystallization. When heat treatment is performed at 600 ° C. as in Example 1, crystallization is almost completed in 10 hours. However, if it is 550 ° C., the heat treatment time is 100 hours or more, and if it is 700 ° C., it takes about 1 hour. The heat treatment temperature is determined by such length, but is preferably about 530 ° C. to about 670 ° C., more preferably about 550 ° C. to 650 ° C., and more preferably about 570 ° C. to 630 ° C.
[0037]
The semiconductor film thus obtained is patterned with a resist and then carbon tetrafluoride (CF_Four) And oxygen (O₂The active layer semiconductor film 203 was formed by etching using the mixed plasma (FIG. 2A). The semiconductor film formed in Example 1 is CF._FourAnd O₂Etching when the output was 700 W with a vacuum plasma discharge of 15 Pa with a ratio of 50 SCCM to 100 SCCM had an etching rate of 2.0 Å / sec.
[0038]
Next, this substrate is cleaned with boiling nitric acid with a concentration of 60%, and the gate insulating film is formed by the APCVD method.₂The film 204 was deposited 1500 liters (FIG. 2b). The substrate temperature when depositing the gate insulating film by the APCVD method is 300 ° C., and oxygen of silane 300 SCCM and 300 SCCM diluted to 20% with nitrogen is flowed into SiO 2₂A film was deposited. In the first embodiment, the APCVD method is used, but besides this, various CVD methods such as a plasma CVD method, a photo CVD method, and an LPCVD method, and a PVD method such as a sputtering method are also effective. The raw material is not limited to silane, but TEOS {Si- (CH_Three-CH₂-O-)_Four} Can also be used. Of course, you may use ECR-PECVD method.
[0039]
Next, tantalum was deposited by sputtering, and the gate electrode 205 was formed by patterning. In the first embodiment, tantalum is used as the gate electrode material, but it is needless to say that other conductive materials are possible, and the formation method is not limited to the sputtering method, and the vapor deposition method, the CVD method, and the like are also possible. After forming the gate electrode, an element that becomes a donor or an acceptor is ion-implanted 206 using the gate electrode as a mask to form a source / drain region 207 and a channel region 208 (FIG. 2C). In Example 1, with the aim of producing an NMOS transistor, 5% phosphine diluted with hydrogen was implanted by a mass non-separation type ion implantation apparatus. The acceleration voltage is 110 kv and the total ion implantation amount including hydrogen atoms is 1.0 × 10¹⁶cm^-2It was in. Subsequently, SiO which becomes the interlayer insulating film 209 by the APCVD method₂A film of 5000 ５ was deposited. This deposition is performed in Example 1 with the base SiO.₂The conditions were the same as those for depositing the film 202, and only the deposition time was changed. After the formation of the interlayer insulating film, a heat treatment was performed at 300 ° C. for 1 hour in nitrogen in order to activate the implanted ions and bake the interlayer insulating film. The sheet resistance value of the source / drain region after the heat treatment was (93 ± 22) kΩ / □ with a reliability coefficient of 95%. In the first embodiment, ion implantation is performed by a mass non-separation type ion implantation apparatus, and the implanted ions are activated by low-temperature heat treatment at 300 ° C. However, the present invention is not limited to this. For example, in a normal mass separation type ion implantation apparatus It may be activated by ion implantation and laser irradiation. Thereafter, contact holes are opened, and source / drain extraction electrodes 210 are formed by sputtering or the like, thereby completing the transistor (FIG. 2d). In Example 1, aluminum was used as the source / drain extraction electrode material and deposited to a thickness of 8000 mm by sputtering to form a source / drain extraction electrode. At this time, the sheet resistance of the deposited aluminum film was 42.5 ± 2.0 mΩ / □.
[0040]
The characteristics of the prototyped thin film transistor (TFT) were measured at a temperature of 25 ° C. The transistor size was a channel portion length L = 10 μm and a width W = 10 μm. The results obtained with Vds = 4v are shown in FIG. Reflecting the fact that defects and unpaired electrons in the SPC film are terminated, the rise from the off state (Vgs <−5v) to the on state (Vgs> 0v) becomes steep, and the minimum current value (Vgs = −4v). A good thin film semiconductor device having a small size was obtained. Further, the process is simplified as long as no hydrogenation treatment is performed, and a thin film semiconductor device that is homogeneous in a large substrate and between substrates is manufactured.
[0041]
On the other hand, such a good thin film semiconductor device cannot be produced by the prior art. Hereinafter, in order to clarify the superiority of the present invention, a comparison with the prior art will be made. The difference between the prior art and the present invention is the heat treatment method of the amorphous semiconductor film. In the prior art, after the amorphous semiconductor film is formed, heat treatment is performed in an atmospheric pressure nitrogen atmosphere. That is, after inserting the substrate into a heat treatment furnace at 400 ° C. in a pure nitrogen atmosphere, the temperature was raised to 600 ° C. for 1 hour, and then maintained at 600 ° C. for 15 hours. The substrate heat-treated by the prior art was completed through the same steps as those of the present invention in Example 1 to complete the thin film transistor. The transistor characteristics of the thin film semiconductor device manufactured in this way are shown in FIG. As shown in this comparative example, when the gate insulating film is formed by a method other than the ECR-PECVD method (for example, the APCVD method used in this comparative example) by the heat treatment of the prior art and the hydrogenation treatment is not performed, It becomes a thin film semiconductor device that is high and has excellent switching characteristics. The sheet resistance of the source / drain region of the comparative example was (182 ± 62) kΩ / □ with a 95% reliability coefficient. The reason why the present invention lowers the sheet resistance of the source / drain regions as compared with the prior art, and the reason why an excellent thin film semiconductor device can be manufactured, is because defects in the semiconductor film are repaired or unpaired electrons are affected by the present invention. This is because of the termination of oxygen with oxygen, carrier defects such as electrons, inelastic scattering with unpaired electrons, etc., and the number of trap levels in the grain boundaries and grains have decreased. . As described above, a high-quality semiconductor film can be obtained according to the present invention. When an impurity serving as a donor or an acceptor is added to the semiconductor film, a low-resistance electric conductive film can be obtained. Yes, because the device is obtained.
[0042]
(Reference example 1)
  Except for the heat treatment method for promoting the crystallization of the amorphous semiconductor film, the thin film semiconductor device was manufactured by the same manufacturing method as that of the present invention described in Example 1 for all other processes. BookReference example 1Then, after crystallizing the amorphous semiconductor film in an inert atmosphere under reduced pressure, the environment in the heat treatment furnace was continuously changed to an oxidizing atmosphere to obtain a high-quality crystalline semiconductor film.
[0043]
The substrate on which the amorphous semiconductor film was deposited by the method described in detail in Example 1 was immersed in an aqueous 1.67% hydrofluoric acid solution for 20 seconds, and the natural oxide film was removed from the surface of the amorphous semiconductor film. Thereafter, the substrate was immediately placed in an inert atmosphere and subjected to heat treatment.
[0044]
  The heat treatment furnace is a vertical furnace maintained at 400 ° C. and has a purity of 99.999% or more.20000 SCCMAnd helium with a purity of 99.9999% or more10,000 SCCMIs introduced into the heat treatment furnace from the upper part of the heat treatment furnace and discharged from the lower substrate insertion opening. BookReference example 1When the substrate is inserted from the lower side in a vertical furnace like this, it is possible to prevent the introduction of impurity gases such as air and water by flowing an inert gas that is lighter than air from the top to the bottom. Can be kept in a completely inert atmosphere.
[0045]
After inserting the substrate, evacuation was performed, and 200 SCCM of nitrogen having a purity of 99.999% or more and 100 SCCM of helium having a purity of 99.999% or more were kept flowing in the heat treatment furnace, and the pressure in the heat treatment furnace was maintained at 10 torr. There is almost no contamination of oxygen or the like when the substrate is inserted, and the inert gas always flows. Therefore, even if it is strictly assumed that all the impurities in nitrogen are oxygen, the oxygen partial pressure in the heat treatment furnace is 0.1 mtorr. It is below. Nitrogen purity of 99.999% or higher indicates a measurement limit of simple measurement, and the purity is usually higher. Therefore, no matter how high the oxygen partial pressure in the heat treatment furnace cannot exceed 0.1 mtorr, it is 0.05 mtorr or less.
[0046]
  After the oxygen partial pressure in the heat treatment furnace is set to 0.1 mtorr or less, preferably 0.05 mtorr or less, more preferably 0.01 mtorr or less, the temperature of the thermal oxidation furnace is increased to 600 ° C. over 1 hour, and in that state Maintained for 12 hours. By this heat treatment, the amorphous semiconductor film is crystallized to change the solid state to a polycrystalline state. However, a large number of defects and unpaired electrons associated with the movement of semiconductor atoms exist on the crystal grain boundaries and the film surface. After the heat treatment for 12 hours, while maintaining the temperature at 600 ° C., the supply of the inert gas was stopped, and oxygen with a purity of 99.999% or more was introduced into the reactor,760 torrIt was. This 600 ℃,760 torrHeat treatment was further performed for 3 hours in a pure oxygen atmosphere. The oxygen partial pressure during the heat treatment time in this oxygen atmosphere is7.6 torr From 76 torrIs preferred. When the pressure is high, a safety problem arises. On the other hand, when the pressure is low, defect termination due to oxygen is delayed, which hinders productivity. Therefore, more preferably228 torrFrom5320 torrIs suitable as an oxygen partial pressure, more preferably532 torrFrom2280 torrIt is. The heat treatment temperature is between about 500 ° C and 700 ° C. Although low temperature is preferable from the viewpoint of increasing crystal growth slowly, it takes a long time for crystallization. BookReference example 1When the heat treatment is performed at 600 ° C., the crystallization is almost completed in 10 hours. However, if it is 550 ° C., the heat treatment time is 100 hours or more, and if it is 700 ° C., it takes about 1 hour. The heat treatment temperature is determined by such length, but is preferably about 530 ° C. to about 670 ° C., more preferably about 550 ° C. to 650 ° C., and more preferably about 570 ° C. to 630 ° C.
[0047]
  Using the polycrystalline semiconductor film thus obtained, a thin film semiconductor device was produced in the same process as that of the present invention in Example 1 below. The obtained transistor characteristics are shown in FIG. Needless to compare with the prior art, it can be seen that even better characteristics than the invention of Example 1 are obtained. BookReference example 1The sheet resistance of the source / drain region of the thin film semiconductor device fabricated in (5) was (85 ± 20) kΩ / □ with a 95% reliability coefficient. BookReference example 1Thus, a semiconductor film having a higher quality than that of the invention of Example 1 was obtained because Example 1 had a crystal growth and formation of an oxide film in a competitive process in a weakly oxidizing atmosphere.Reference example 1Then, the oxygen partial pressure was set to 0.1 mtorr or less to completely suppress the growth of the oxide film, and after the crystal growth, the defects due to oxygen were terminated, so that the defect repair was made more effective than the invention of Example 1. So it is. BookReference example 1Then, in order to lower the oxygen partial pressure during heat treatment, heat treatment is performed under a reduced pressure of 10 torr, and then the oxygen partial pressure is reduced.760 torrHowever, if the oxygen partial pressure is about 10 mtorr or less if the heat treatment temperature is about 600 ° C., the oxidation hardly proceeds. Therefore, after the first heat treatment is performed under an atmospheric pressure inert atmosphere, The second heat treatment may be performed in an atmosphere. In this case, it is sufficient that the nitrogen purity during the first heat treatment is 99.999% or more. Further, the gas flowing during the heat treatment in the first inert atmosphere is not limited to nitrogen and helium, and may be a rare gas alone such as neon, argon, krypton, xenon, or a mixed gas thereof. Furthermore, the gas flowing during the heat treatment in the second oxidizing atmosphere is not limited to oxygen, and oxidizing gases such as laughing gas, water, and carbon dioxide, and mixed gases thereof, as well as mixtures of oxidizing gases and inert gases. It may be a gas.
[0048]
(Reference example 2)
  Except for the heat treatment method for promoting the crystallization of the amorphous semiconductor film, all other steps were performed to produce a thin film semiconductor device by the same manufacturing method as the present invention described in Example 1. BookReference example 2Then, after crystallizing the amorphous semiconductor film in a reducing atmosphere under reduced pressure, the environment in the heat treatment furnace was continuously changed to an oxidizing atmosphere to obtain a high-quality crystalline semiconductor film.
[0049]
The substrate on which the amorphous semiconductor film was deposited by the method described in detail in Example 1 was immersed in an aqueous 1.67% hydrofluoric acid solution for 20 seconds, and the natural oxide film was removed from the surface of the amorphous semiconductor film. Thereafter, the substrate was immediately placed in a reducing atmosphere and subjected to heat treatment.
[0050]
  The heat treatment furnace is a vertical furnace, maintained at 400 ° C., 500 SCCM of hydrogen with a purity of 99.9999% or more, and helium with a purity of 99.9999% or more.20000 SCCMIs introduced into the heat treatment furnace from the upper part of the heat treatment furnace and discharged from the lower substrate insertion opening. BookReference example 2When a substrate is inserted from the lower side in a vertical furnace like this, it is possible to prevent the introduction of impurity gases such as air and water by flowing a reducing gas that is lighter than air from the top to the bottom. Can be kept in a completely reducing atmosphere.
[0051]
  After inserting the substrate, evacuation was performed, and 200 SCCM of hydrogen having a purity of 99.9999% or more and 100 SCCM of helium having a purity of 99.9999% or more were kept flowing in the heat treatment furnace, and the pressure in the heat treatment furnace was maintained at 10 torr. Accordingly, the hydrogen partial pressure is 6.7 torr. Thereafter, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained in that state for 12 hours. Next, the inside of the heat treatment furnace is evacuated for 3 minutes while maintaining the temperature of the heat treatment furnace at 600 ° C., and further helium having a purity of 99.9999% or more is allowed to flow for 300 SCCM for 3 minutes. Introducing oxygen with a purity of 99.999% or more into the furnace760 torrIt was. 600 ℃, pure oxygen760 torrThen, heat treatment was further continuously performed for 3 hours in the atmosphere. In the case of heat treatment in a reducing atmosphere, the hydrogen partial pressure is from 0.1 mtorr.7600 torrThe degree is preferable, but practically from 0.1 torr760 torrIs preferred, and from 1 torr76 torrIs optimal. Oxygen partial pressure during continuous heat treatment in an oxidizing atmosphere is76 torrFrom7600 torrIs preferred. When the pressure is increased, a safety problem occurs. On the other hand, when the pressure is low, the defect termination due to oxygen is delayed, which hinders productivity. Therefore, more preferably228 torrFrom5320 torrIs suitable as an oxygen partial pressure, more preferably532 torrFrom2280 torrIt is. The heat treatment temperature is between about 500 ° C and 700 ° C. Although low temperature is preferable from the viewpoint of increasing crystal growth slowly, it takes a long time for crystallization. BookReference example 2When the heat treatment is performed at 600 ° C., the crystallization is almost completed in 10 hours. However, if it is 550 ° C., the heat treatment time is 100 hours or more, and if it is 700 ° C., it takes about 1 hour. The heat treatment temperature is determined by such length, but is preferably about 530 ° C. to about 670 ° C., more preferably about 550 ° C. to 650 ° C., and more preferably about 570 ° C. to 630 ° C.
[0052]
  Using the polycrystalline semiconductor film thus obtained, a thin film semiconductor device was produced in the same process as that of the present invention in Example 1 below. The obtained transistor characteristics are shown in FIG.Reference example 1As in the above, a thin film semiconductor device having excellent characteristics was obtained. BookReference example 2The sheet resistance value of the source / drain region of the thin film semiconductor device fabricated in (1) was (84 ± 17) kΩ / □ with a 95% reliability coefficient. BookReference example 2However, based on the fact that the crystal growth was performed in a reducing atmosphere, the formation of the oxide film was completely suppressed, and the defect repair by oxygen was effectively performed after the completion of the crystal growth, a high-quality semiconductor film was obtained. BookReference example 2The heat treatment in a reducing atmosphere at was performed under reduced pressure, but this may be at normal pressure. Further, the reducing gas is not limited to hydrogen, and ammonia or the like is also possible. Of course, oxidizing gas is not limited to oxygen,Reference example 1The oxidizing gas described in (1) is also effective.
[0053]
(Reference example 3)
  Figures 3a-d are booksReference example 32 is a cross-sectional view showing a manufacturing process of a silicon thin film semiconductor device constituting a MIS field effect transistor having a self-aligned staggered structure in FIG.
[0054]
  BookReference example 3Then, although 235 mm square fused silica glass was used as the base substrate 301, the type and size of the base substrate material are not limited as long as it is a substrate or base material that can withstand the maximum process temperature of 600 ° C. For example, in addition to a normal glass substrate, a semiconductor substrate such as a silicon wafer and an LSI obtained by processing them, a three-dimensional LSI, or a ceramic substrate such as silicon carbide, alumina, or aluminum nitride can be used as a base substrate.
[0055]
First, the base substrate 301 is immersed in an organic solvent such as acetone or methyl / ethyl / ketone, methyl / iso / butyl / ketone, or cyclohexanone, and ultrasonic cleaning is performed. After washing, drying is performed in nitrogen or under reduced pressure, and further ultrasonic washing with ethanol is performed, followed by washing with pure water that has been bubbled with nitrogen. Next, the base substrate 301 was dipped in boiling nitric acid having a concentration of 60% for 5 minutes, and further washed in pure water bubbled with nitrogen. When a substrate is used that is corroded by an acid such as a metal or is changed in quality, this cleaning with nitric acid is not required. Further, in this cleaning with strong acid, sulfuric acid can be used as an acid in addition to nitric acid.
[0056]
On the quartz substrate thus cleaned, a silicon dioxide film (SiO 2) serving as a base protective film by atmospheric pressure chemical vapor deposition (APCVD).₂2000) of the film) 302 was deposited. This base SiO₂The film 302 is necessary for stabilizing the film quality of a semiconductor film to be deposited later and the performance of a thin film transistor using the film when using various kinds of materials as described above as a substrate. At the same time, for example, when normal glass is used as the substrate 301, movable ions such as sodium contained in the glass are added to the substrate 301 when various ceramic plates are used as the substrate 301. It also plays a role in preventing auxiliary materials from diffusing and mixing into the transistor section. When a metal plate is used as the substrate 301, the underlying SiO is used to ensure insulation.₂Is indispensable. In a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors or wirings. Base SiO₂The substrate temperature during deposition of the film 302 was 300 ° C., and 600 SCCM of silane diluted to 20% with nitrogen was deposited together with 840 SCCM of oxygen by the APCVD method. SiO at this time₂The deposition rate of the film was 3.9 kg / sec.
[0057]
  Next, an amorphous semiconductor film to be an active layer was deposited by low pressure CVD. BookReference example 3Although silicon is used as the semiconductor film, other semiconductors such as silicon / germanium and gallium / arsenic are possible.
[0058]
  The volume of the low pressure CVD reactor used for semiconductor film deposition is 184.5 l, and the substrate is placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, and hydrogen are introduced into the furnace from the lower part of the reaction furnace as necessary, and exhausted from the upper part of the reaction furnace. A heater divided into three zones is installed outside the reaction furnace made of quartz glass, and by adjusting them independently, a soaking zone is formed at a desired temperature near the center of the reaction furnace. This soaking zone spreads at a height of about 350 mm, and the temperature deviation within that range is within 0.2 ° C. when set to 500 ° C., for example. Therefore, if the interval between the inserted substrates is 7 mm, 50 substrates can be processed in one batch. BookReference example 3Then, 17 substrates were installed in the soaking zone at intervals of 20 mm.
[0059]
Exhaust was performed by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reactor was measured using a diaphragm type pressure gauge (MKS Baratron Manometer) whose measurement value does not depend on the type of gas. When the reactor is kept at 550 ° C., the gas introduction valve is closed and evacuation is performed with both pumps, the reactor internal pressure is 0 mtorr.^-FourIt is about torr or less.
[0060]
  The substrate on which the semiconductor film was to be deposited was inserted into a low pressure CVD furnace with the front side facing down. The temperature in the reactor at the time of insertion was about 395 ° C to 400 ° C. When the substrate is inserted, a mixed gas of helium and hydrogen with a purity of 99.9999% or more is introduced into the reactor from the top.30000 SCCMThe mixed gas is introduced and discharged from the substrate insertion port provided at the lower part of the reaction furnace. The diameter of the board insertion slot is 540 mm and its cross-sectional area is 2290 cm.²It is. When the mixed gas is heated to 400 ° C., the discharge speed of the mixed gas from the substrate insertion port is 29.6 cm / min. BookReference example 3When a 235 mm square substrate is installed horizontally as shown in the figure, the substrate area is 552 cm.²Therefore, when the substrate enters the reaction furnace from the substrate insertion port, the discharge speed of the mixed gas discharged from the gap between the substrate insertion port and the substrate is 39.0 cm / min. BookReference example 3Then, the substrate was inserted into the reaction furnace at an ascending rate of 20 cm / min. However, since the mixed gas discharge speed is faster, it is possible to prevent air and the like from being mixed into the reaction chamber when the substrate is inserted. Also, since the density of the gas mixture is much smaller than the air density and is heated, there is little possibility that heavy air will push away these light gases and enter from the bottom up. BookReference example 3The concentration of the mixed gas introduced from the upper part of the reactor was 97% helium and 3% hydrogen. Since the lower limit of hydrogen explosion is 4.0%, it is safe to discharge from the substrate insertion port into the room if the concentration is lower than this. By using such a substrate insertion method, the inside of the reactor can be kept in a clean non-oxidizing atmosphere without going through the complicated process of evacuating every batch using the load lock chamber. Yes. When impurity gases such as air and water flow into the reaction furnace when the substrate is inserted, they adsorb to the semiconductor layer on the inner wall of the reaction furnace or react with semiconductor elements and remain in the reaction furnace. Appears as degassing, and causes the quality of the deposited film to deteriorate. Therefore, a high quality semiconductor film is easily deposited by the CVD method using the substrate insertion of the present invention.
[0061]
  After inserting the substrate, vacuuming and leakage inspection were performed. In the leak inspection, all valves connected to the reactor were closed and the reactor was completely isolated, and changes in the reactor pressure were examined. BookReference example 3Then, after complete isolation for 2 minutes at 400 ° C., the reactor pressure was 1 mtorr or less. After confirming that there is no abnormality in the leakage inspection, the temperature in the reactor is raised from the insertion temperature of 400 ° C. to the deposition temperature. BookReference example 3Then, since the semiconductor film which becomes the channel portion was deposited at 510 ° C., it took one hour to raise the temperature. It takes about 35 minutes for the furnace temperature to reach the deposition temperature of 510 ° C. However, in order to sufficiently release the degassed from the reaction furnace wall, a heating period of at least one hour, preferably several hours is desirable. . During this temperature raising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995% or more. These gas species can be a pure gas such as hydrogen, helium, nitrogen, neon, argon, xenon, krypton, or a mixed gas of these gases. BookReference example 3Then, helium having a purity of 99.9999% or more was continuously supplied at 350 SCCM, and the reactor pressure was 81 ± 1.2 mtorr.
[0062]
  After reaching the deposition temperature, a predetermined amount of silane, which is a raw material gas, or a mixed gas of silane and dilution gas is introduced into the reaction furnace to deposit an amorphous semiconductor film. As the dilution gas, the same kind of combination as the gas flowed in the previous temperature raising period is possible, but the purity of each gas is preferably 99.999% or more. BookReference example 3Then, without using a diluting gas, an amorphous semiconductor film was deposited by flowing 200 SCCM of silane having a purity of 99.999% or more. The pressure in the reactor during deposition was maintained at 1.0 torr by adjusting the degree of opening and closing of a conductance valve installed between the reactor and the mechanical booster pump. BookReference example 3Then, the amorphous semiconductor film was deposited to a thickness of 250 で at a deposition rate of 20 Å / min.
[0063]
  BookReference example 3In this case, the amorphous semiconductor film is deposited by LPCVD, and monosilane is used as the source gas. In addition, various PVD methods such as plasma CVD method, photo CVD method, APCVD method, sputtering method, vapor deposition method, etc. It is also possible to deposit by the method. Further, the source gas is not limited to monosilane, and higher order silanes such as disilane and trisilane, dichlorosilane, germane, and the like are also possible. Of course, it is possible to deposit an amorphous semiconductor film by a combination of the various CVD methods and the various raw materials.
[0064]
  The amorphous semiconductor film thus obtained is patterned with a resist and then carbon tetrafluoride (CF_Four) And oxygen (O₂) To form an amorphous semiconductor film 303 that will eventually become an active layer (FIG. 3a). BookReference example 3The amorphous semiconductor film formed by CF is CF_FourAnd O₂Etching when the output was 700 W with a vacuum plasma discharge of 15 Pa with a ratio of 50 SCCM to 100 SCCM had an etching rate of 2.2 Å / sec.
[0065]
  Next, this substrate is cleaned with boiling nitric acid with a concentration of 60%, and the gate insulating film is formed by the APCVD method.₂1500 mm of film 304 was deposited. The substrate temperature when depositing the gate insulating film by the APCVD method is 300 ° C., and oxygen of silane 300 SCCM and 300 SCCM diluted to 20% with nitrogen is flowed into SiO 2₂A film was deposited. BookReference example 3In this case, the APCVD method is used, but besides this, various CVD methods such as a plasma CVD method, a photo CVD method, and an LPCVD method and a PVD method such as a sputtering method are also effective. The raw material is not limited to silane, but TEOS {Si- (CH_Three-CH₂-O-)_Four} Can also be used. Of course, you may use ECR-PECVD method.
[0066]
Next, the substrate thus obtained was washed with sulfuric acid at 97 ° C., and then the substrate was immediately placed in an oxidizing atmosphere and subjected to heat treatment.
[0067]
  The heat treatment furnace is a vertical furnace and is usually kept at 400 ° C., and oxygen with a purity of 99.999% or more is supplied.30000 SCCMThe inside of the heat treatment furnace is kept in an oxidizing atmosphere. Therefore, the oxygen partial pressure in the heat treatment furnace is approximately760 torrIt becomes. The volume of the heat treatment furnace is 184.5 l. The substrate is inserted into the heat treatment furnace from the lower part of the vertical furnace, but oxygen is introduced into the furnace from the upper part of the heat treatment furnace and flows out from the lower insertion port. The substrate that had reached temperature equilibrium with room temperature was inserted into a 400 ° C. furnace in an oxidizing atmosphere. After inserting the substrate, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained at 600 ° C. for 15 hours. By this heat treatment, the amorphous semiconductor film is crystallized to change the solid state into a polycrystalline semiconductor film. When the semiconductor elements that made up the amorphous film move to a polycrystalline state, the resulting polycrystalline grains will inevitably have a large amount due to a decrease in atomic density and a low degree of freedom in spatial movement. A large number of defects and unpaired electrons are generated. However, according to the present invention, such defects and unpaired electrons are terminated by bonding with oxygen. Generally, SiO2 of oxygen at a temperature of about 600 ° C₂The diffusion of is very slow. In particular, SiO obtained by oxidizing silicon₂Is dense, so if the film thickness is several tens of millimeters, Si and SiO₂The amount of oxygen supplied to this interface (hereinafter referred to as the MOS interface) is considerably limited. So if the dense SiO₂If the film is formed on Si with a thickness of 1500 mm,760 torrIn the heat treatment for ten hours, almost no oxygen is supplied to the MOS interface. However, the bookReference example 3In this case, SiO is used as a gate insulating film.₂Since the film is a vacant film deposited by the CVD method, oxygen is freely supplied up to a dense natural oxide film of less than several tens of kilometers formed on the Si surface. Dense and low oxygen diffusion coefficient SiO₂At a temperature of 600 ° C.760 torrEven if it is about, oxygen is supplied to the MOS interface, and defects and unpaired electrons generated during crystal growth are effectively terminated. Furthermore, SiO deposited by CVD method etc.₂Many unreacted Si atoms, Si—H groups, Si—OH groups, unpaired electrons, and the like remain in the film. These unreacted materials are SiO₂It becomes a charge in the middle and increases the threshold voltage (Vth) of the transistor or increases the interface charge (Qss), which does not cause good characteristics. Further, since these unreacted substances are chemically unstable, the stability of the semiconductor device over time is impaired when a thin film semiconductor device is produced. That is, compared to dense and stable thermal oxide film, CVDSiO₂It is because the film is inferior. However, the bookReference example 3However, simultaneously with the crystallization promotion of the semiconductor film, the reaction of the gate oxide film is promoted and densified by the oxygen heat treatment, which greatly improves the quality of the oxide film. Si-H, Si-OH, Si-e that existed in the oxide film by this heat treatment^-Etc. are present because the reaction proceeds with Si—O—Si and at the same time becomes dense. Actually SiO with 1.67% hydrofluoric acid aqueous solution₂When the etching rate of the film is examined, the thermal oxide film has a thickness of 1.0 cm / sec and the APCVD SiO₂While the film was 22 Å / sec, the etching rate of the present invention in which the APCVD film was subjected to oxygen heat treatment was greatly improved to 4.3 Å / sec. Conventionally, CVDSiO₂Films and SiO obtained by heat-treating these films in an inert atmosphere₂When partial etching such as contact hole formation is performed on the film using a hydrofluoric acid aqueous solution, Si-SiO as shown in FIG.₂Inverse taper often occurred at the interface. This is Si and SiO₂Because of poor adhesion, the etching solution is Si and SiO₂Based on rapid intrusion into the interface. In contrast, the SiO of the present invention subjected to oxygen heat treatment₂Since the reaction was promoted and the adhesion was improved, the reverse taper does not occur, and the film has a forward taper as shown in FIG. If a reverse taper is generated when a contact hole is opened, a disconnection occurs and electrical continuity cannot be obtained. Therefore, a forward taper is indispensable to stably manufacture a large number of thin film semiconductor devices.
[0068]
  BookReference example 3So the oxygen partial pressure in the oxidizing atmosphere is760 torrIt was in. When creating an oxidizing atmosphere with oxygen, the oxygen partial pressure is3.8 torrFrom3800 torrThe degree is preferred. More preferably76 torrFrom3800 torrMore preferably380 torrFrom2280 torrIt is in degree. The optimum partial pressure is determined by the semiconductor film material and the heat treatment temperature. Also, laughing gas (N₂O) and water (H₂When using O), these gas partial pressures are7.6 torrFrom76 torrDegree is preferred, more preferably15.2 torrFrom760 torrMore preferably76 torrFrom456 torrIt is in degree. The heat treatment temperature is between about 500 ° C. and 700 ° C. Although low temperature is preferable from the viewpoint of increasing crystal growth slowly, it takes a long time for crystallization. BookReference example 3When the heat treatment is performed at 600 ° C., the crystallization is almost completed in 10 hours. However, if it is 550 ° C., the heat treatment time is 100 hours or more, and if it is 700 ° C., it takes about 1 hour. The heat treatment temperature is determined by such length, but is preferably about 530 ° C. to about 670 ° C., more preferably about 550 ° C. to 650 ° C., and more preferably about 570 ° C. to 630 ° C.
[0069]
  Next, tantalum was deposited by sputtering, and a gate electrode 306 was formed by patterning. BookReference example 3In this case, tantalum is used as the gate electrode material, but it is needless to say that other conductive materials are possible, and the formation method is not limited to the sputtering method, and the vapor deposition method and the CVD method are also possible. After forming the gate electrode, an element that becomes a donor or an acceptor is ion-implanted 307 using the gate electrode as a mask to form a source / drain region 308 and a channel region 309 (FIG. 3C). BookReference example 3Then, with the aim of making an NMOS transistor, 5% phosphine diluted with hydrogen was implanted with a mass non-separation type ion implantation apparatus. The acceleration voltage is 110 kv and the total ion implantation amount including hydrogen atoms is 1.0 × 10¹⁶cm^-2It was in. Subsequently, SiO which becomes the interlayer insulating film 310 by the APCVD method.₂A film of 5000 ５ was deposited. This deposit is bookReference example 3In the base SiO₂The conditions were the same as those for depositing the film 302, and only the deposition time was changed. After the formation of the interlayer insulating film, a heat treatment was performed at 300 ° C. for 1 hour in nitrogen in order to activate the implanted ions and bake the interlayer insulating film. The sheet resistance value of the source / drain region after the heat treatment was (80 ± 18) kΩ / □ with a reliability coefficient of 95%. BookReference example 3Then, ion implantation was performed with a mass non-separation type ion implantation apparatus and activation of the implanted ions was performed by low-temperature heat treatment at 300 ° C., but not limited thereto, for example, ion implantation with a normal mass separation type ion implantation apparatus, It may be activated by laser irradiation. Thereafter, contact holes are opened, and source / drain extraction electrodes 311 are formed by sputtering or the like, thereby completing the transistor (FIG. 3d). BookReference example 3Then, aluminum was used as a source / drain extraction electrode material and deposited to a thickness of 8000 mm by sputtering to form a source / drain extraction electrode. At this time, the sheet resistance of the deposited aluminum film was 42.5 ± 2.0 mΩ / □.
[0070]
  The characteristics of the prototyped thin film transistor (TFT) were measured at a temperature of 25 ° C. The transistor size was a channel portion length L = 10 μm and a width W = 10 μm. Good transistor characteristics were obtained reflecting the fact that defects and unpaired electrons in the SPC film were terminated and the gate oxide film quality was further improved. The invention described in Example 1 (A in FIG. 1) and a comparative example (D in FIG. 1);Reference example 1(FIG. 1-B),Reference example 2(Figure 1-C) transistor characteristics and thisReference example 3The results are summarized in Table 1.
[0071]
[Table 1]

[0072]
It is obvious that a high on-current and a low off-current are realized, as compared with the comparative example of the prior art. The reason why the present invention lowers the sheet resistance of the source / drain regions as compared with the prior art, and the reason why an excellent thin film semiconductor device can be manufactured, is because defects in the semiconductor film are repaired or unpaired electrons are affected by the present invention. This is because of the termination of oxygen with oxygen, carrier defects such as electrons, inelastic scattering with unpaired electrons, etc., and the number of trap levels in the grain boundaries and grains have decreased. . In addition, since the quality of the gate insulating film has been improved, the on-current is increased, and the gate voltage (Vgs min) at which the minimum current is simultaneously approached 0 V, thereby realizing steep switching characteristics. At the same time, the stability over time increases and SiO₂The reverse taper of contact holes opened in the film has also been solved.
[0073]
As described above, a high-quality semiconductor film can be obtained according to the present invention. When an impurity serving as a donor or an acceptor is added to the semiconductor film, a low-resistance electric conductive film can be obtained. Yes, because the device is obtained.
[0074]
(Reference example 4)
  Figures 4a-d are booksReference example 42 is a cross-sectional view showing a manufacturing process of a silicon thin film semiconductor device constituting a MIS field effect transistor having a self-aligned staggered structure in FIG.
[0075]
  BookReference example 4Then, although 235 mm □ fused silica glass was used as the base substrate 401, the type and size of the base substrate material are not limited as long as it is a substrate or base material that can withstand the maximum process temperature of 600 ° C. For example, in addition to a normal glass substrate, a semiconductor substrate such as a silicon wafer and an LSI obtained by processing them, a three-dimensional LSI, or a ceramic substrate such as silicon carbide, alumina, or aluminum nitride can be used as a base substrate.
[0076]
First, the base substrate 401 is immersed in an organic solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone, and ultrasonic cleaning is performed. After washing, drying is performed in nitrogen or under reduced pressure, and further ultrasonic washing with ethanol is performed, followed by washing with pure water that has been bubbled with nitrogen. Next, the base substrate 401 was immersed for 5 minutes in boiling nitric acid having a concentration of 60%, and further washed in pure water that was bubbled with nitrogen. When a substrate is used that is corroded by an acid such as a metal or is changed in quality, this cleaning with nitric acid is not required. Further, in this cleaning with strong acid, sulfuric acid can be used as an acid in addition to nitric acid.
[0077]
On the quartz substrate thus cleaned, a silicon dioxide film (SiO 2) serving as a base protective film by atmospheric pressure chemical vapor deposition (APCVD).₂2000 liters of (film) 402 was deposited. This base SiO₂The film 402 is necessary to stabilize the film quality of a semiconductor film to be deposited later and the performance of a thin film transistor formed using the film when using various kinds of materials as described above as a substrate. At the same time, for example, when normal glass is used as the substrate 401, movable ions such as sodium contained in the glass are added, and when various ceramic plates are used as the substrate 401, sintering is added to the substrate. It also plays a role in preventing auxiliary materials from diffusing and mixing into the transistor section. When a metal plate is used as the substrate 401, the underlying SiO is used to ensure insulation.₂Is indispensable. In a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors or wirings. Base SiO₂The substrate temperature during deposition of the film 402 was 300 ° C., and silane 600 SCCM diluted to 20% with nitrogen was deposited together with 840 SCCM oxygen by the APCVD method. SiO at this time₂The deposition rate of the film was 3.9 kg / sec.
[0078]
  Next, an amorphous semiconductor film to be an active layer was deposited by low pressure CVD. BookReference example 4Although silicon is used as the semiconductor film, other semiconductors such as silicon / germanium and gallium / arsenic are possible.
[0079]
  The volume of the low pressure CVD reactor used for semiconductor film deposition is 184.5 l, and the substrate is placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, and hydrogen are introduced into the furnace from the lower part of the reaction furnace as necessary, and exhausted from the upper part of the reaction furnace. A heater divided into three zones is installed outside the reaction furnace made of quartz glass, and by adjusting them independently, a soaking zone is formed at a desired temperature near the center of the reaction furnace. This soaking zone spreads at a height of about 350 mm, and the temperature deviation within that range is within 0.2 ° C. when set to 500 ° C., for example. Therefore, if the interval between the inserted substrates is 5 mm, 70 substrates can be processed in one batch. BookReference example 4Then, 17 substrates were installed in the soaking zone at intervals of 20 mm.
[0080]
Exhaust was performed by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reactor was measured using a diaphragm type pressure gauge (MKS Baratron Manometer) whose measurement value does not depend on the type of gas. When the reactor is kept at 550 ° C., the gas introduction valve is closed and evacuation is performed with both pumps, the reactor internal pressure is 0 mtorr.^-FourIt is about torr or less.
[0081]
  The substrate on which the semiconductor film was to be deposited was inserted into a low pressure CVD furnace with the front side facing down. The temperature in the reactor at the time of insertion was about 395 ° C to 400 ° C. When the substrate is inserted, a mixed gas of nitrogen and hydrogen with a purity of 99.9999% or more is introduced into the reactor from the top.30000 SCCMThe mixed gas is introduced and discharged from the substrate insertion port provided at the lower part of the reaction furnace. The diameter of the board insertion slot is 540 mm and its cross-sectional area is 2290 cm.²It is. When the mixed gas is heated to 400 ° C., the discharge speed of the mixed gas from the substrate insertion port is 29.6 cm / min. BookReference example 4When a 235 mm square substrate is installed horizontally as shown in the figure, the substrate area is 552 cm.²Therefore, when the substrate enters the reaction furnace from the substrate insertion port, the discharge speed of the mixed gas discharged from the gap between the substrate insertion port and the substrate is 39.0 cm / min. BookReference example 4Then, the substrate was inserted into the reaction furnace at an ascending speed of 5 cm / min. However, since the mixed gas discharge speed is faster, it is possible to prevent air and the like from being mixed into the reaction chamber when the substrate is inserted. Moreover, since the density of the mixed gas is smaller than the air density and is heated, there is almost no possibility that heavy air will push these light gases away from the bottom up. BookReference example 4The concentration of the mixed gas introduced from the upper part of the reactor was 97% nitrogen and 3% hydrogen. Since the lower limit of hydrogen explosion is 4.0%, it is safe to discharge from the substrate insertion port into the room if the concentration is lower than this. By using such a substrate insertion method, the inside of the reactor can be kept in a clean non-oxidizing atmosphere without going through the complicated process of evacuating every batch using the load lock chamber. Yes. When impurity gases such as air and water flow into the reaction furnace when the substrate is inserted, they adsorb to the semiconductor layer on the inner wall of the reaction furnace or react with semiconductor elements and remain in the reaction furnace. Appears as degassing, and causes the quality of the deposited film to deteriorate. Therefore, a high quality semiconductor film is easily deposited by the CVD method using the substrate insertion of the present invention.
[0082]
  After inserting the substrate, vacuuming and leakage inspection were performed. In the leak inspection, all valves connected to the reactor were closed and the reactor was completely isolated, and changes in the reactor pressure were examined. BookReference example 4Then, after complete isolation for 2 minutes at 400 ° C., the reactor pressure was 1 mtorr or less. After confirming that there is no abnormality in the leakage inspection, the temperature in the reactor is raised from the insertion temperature of 400 ° C. to the deposition temperature. BookReference example 4Then, since the semiconductor film that becomes the channel portion was deposited at 495 ° C., it took one hour to raise the temperature. It takes about 35 minutes for the furnace temperature to reach the deposition temperature of 495 ° C. However, in order to sufficiently release the degassed from the reactor wall, a temperature rising period of at least one hour, preferably several hours is desirable. . During this temperature raising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995% or more. These gas species can be a pure gas such as hydrogen, helium, nitrogen, neon, argon, xenon, krypton, or a mixed gas of these gases. BookReference example 4Then, helium having a purity of 99.9999% or more was continuously supplied at 350 SCCM, and the reactor pressure was 81 ± 1.2 mtorr.
[0083]
  After reaching the deposition temperature, a predetermined amount of silane, which is a raw material gas, or a mixed gas of silane and dilution gas is introduced into the reaction furnace to deposit an amorphous semiconductor film. As the dilution gas, the same kind of combination as the gas flowed in the previous temperature raising period is possible, but the purity of each gas is preferably 99.999% or more. BookReference example 4Then, without using a diluting gas, an amorphous semiconductor film was deposited by flowing 200 SCCM of silane having a purity of 99.999% or more. During deposition, the pressure in the reactor was kept at 1.3 torr by adjusting the degree of opening and closing of a conductance valve installed between the reactor and the mechanical booster pump. BookReference example 4Then, the amorphous semiconductor film was deposited to a thickness of 350 で at a deposition rate of 16 Å / min.
[0084]
  BookReference example 4In this case, the amorphous semiconductor film is deposited by LPCVD, and monosilane is used as the source gas. In addition, various PVD methods such as plasma CVD method, photo CVD method, APCVD method, sputtering method, vapor deposition method, etc. It is also possible to deposit by the method. Further, the source gas is not limited to monosilane, and higher order silanes such as disilane and trisilane, dichlorosilane, germane, and the like are also possible. Of course, it is possible to deposit an amorphous semiconductor film by a combination of the various CVD methods and the various raw materials.
[0085]
  The amorphous semiconductor film thus obtained is patterned with a resist and then carbon tetrafluoride (CF_Four) And oxygen (O₂) To form an amorphous semiconductor film 403 that will eventually become an active layer (FIG. 4a). BookReference example 4The amorphous semiconductor film formed by CF is CF_FourAnd O₂Etching when the output was 700 W with a vacuum plasma discharge of 15 Pa with a ratio of 50 SCCM to 100 SCCM had an etching rate of 2.2 Å / sec.
[0086]
  Next, this substrate was washed with boiling nitric acid having a concentration of 60%, and an oxide film 404, a nitride film 405, and an oxide film 406 to be a gate insulating film were deposited by a total of 1500 にて by ECR-PECVD. BookReference example 4Then, the oxide film 404 is SiO.₂A 300-nm thick film is deposited, and a silicon nitride film (SiN) is formed as the nitride film 405._X) Is continuously deposited for 1000 mm, and further, SiO 2 is formed as an oxide film 406.₂200Å of film was deposited. The substrate temperature when depositing the gate insulating film by the ECR-PECVD method was 100 ° C., and three layers of insulating films were continuously deposited. BookReference example 4In the case of monosilane (SiH) as the source gas by the ECR-PECVD method._Four) And oxygen (O₂), Nitrogen (N₂In addition to this, various CVD methods such as a normal PECVD method and a photo-CVD method, and PVD methods such as a sputtering method are also effective. The raw material is not limited to monosilane, but higher order silanes such as disilane and trisilane, halides such as chlorosilane and fluorinated silane such as dichlorosilane, and TEOS {Si- (CH_Three-CH₂-O-)_Four} Can also be used. In addition, laughing gas, water, carbon dioxide, NO can be used as oxidants and nitriding agents._XNitrogen oxides such as ammonia and ammonia can be used. Oxygen ions after deposition of the three-layer insulating film (¹⁶O⁺) Was implanted into the lower oxide film 404 at an acceleration voltage of 65 keV (407). The range of oxygen ions at this acceleration voltage is 1250 mm and the range deviation is about 360 mm. Therefore, most of the implanted ions are present in the lower oxide film 404. Implanted ion amount is 1 × 10¹⁴cm^-2It was in. Next, the substrate thus obtained was cleaned and subjected to heat treatment. By this heat treatment, the amorphous semiconductor film 403 changes to a crystallized semiconductor film 408 in a solid phase state. (FIG. 4-b). BookReference example 4Then, heat treatment was performed in an oxidizing atmosphere. This is because the upper oxide film 406Reference example 3However, since the quality of the upper oxide film 406 is not as important as the lower oxide film 404 forming the MOS interface, the heat treatment atmosphere is not particularly limited to oxidization, and is manufactured. It can be set freely according to the above circumstances.
[0087]
  The heat treatment furnace is a vertical furnace and is usually kept at 400 ° C., and oxygen with a purity of 99.999% or more is supplied.30000 SCCMThe inside of the heat treatment furnace is kept in an oxidizing atmosphere. Therefore, the oxygen partial pressure in the heat treatment furnace is approximately760 torrIt becomes. The volume of the heat treatment furnace is 184.5 l. The substrate is inserted into the heat treatment furnace from the lower part of the vertical furnace, but oxygen is introduced into the furnace from the upper part of the heat treatment furnace and flows out from the lower insertion port. The substrate that had reached temperature equilibrium with room temperature was inserted into a 400 ° C. furnace in an oxidizing atmosphere. After inserting the substrate, the temperature of the heat treatment furnace was raised to 600 ° C. over 1 hour, and then maintained at 600 ° C. for 15 hours. By this heat treatment, the amorphous semiconductor film is crystallized to change the solid state into a polycrystalline semiconductor film. At the same time, oxygen ions implanted into the lower oxide film 404 promote oxidation of unreacted substances in the lower oxide film, and improve the film quality of the lower oxide film 404 and the MOS interface. Furthermore, when the semiconductor elements that made up the amorphous film move to the polycrystalline state, the resulting polycrystalline grains are inevitably damaged due to a decrease in atomic density and a low degree of freedom in spatial movement. However, although a number of defects and unpaired electrons are generated, chemically active implanted oxygen ions diffuse into the MOS interface and the crystallized semiconductor film, and are bonded to such defects and unpaired electrons to be terminated. So it is. The concentration of defects and unpaired electrons present in the semiconductor film near the MOS interface is 1 × 10¹⁷cm^-3To 1 × 10¹⁹cm^-3It is in degree. BookReference example 4Then the driving amount is 1 × 10¹⁴cm^-2Since the range deviation is about 360 mm, the implanted ion concentration is 1.4 × 10¹⁹cm^-3SiO2₂This is sufficient for accelerating the reaction of unreacted substances therein and correcting defects in the crystallized semiconductor film. If the amount of oxygen ions implanted is too small, the defect cannot be repaired sufficiently. On the other hand, if the amount of oxygen ions is too large, an excessive oxide film is formed, or oxygen atoms are taken into the semiconductor film to deteriorate the quality of the semiconductor film. . Therefore, the optimum injection amount is 1 × 10 after injection.¹⁷cm^-3To 1 × 10²⁰cm^-3, Preferably 1 × 10¹⁸cm^-3To 5 × 10¹⁹cm^-3More preferably 5 × 10¹⁸cm^-3To 2 × 10¹⁹cm^-3It is what becomes. Since oxygen diffusion in the nitride film 405 is usually very slow, implanted oxygen atoms diffuse only from the oxide film toward the semiconductor film, so that oxygen can be supplied effectively. Further, since the supply source is in the oxide film and not in the semiconductor film, oxygen is not unnecessarily taken into the semiconductor film. A certain amount of time is required for oxygen ions to reach the MOS interface and the semiconductor film due to diffusion from the oxide film. During this time, redistribution of the semiconductor atoms, that is, crystallization occurs, so that there is no defect without interfering with crystallization. Yes, as repairs are made. The heat treatment temperature is between about 500 ° C and 700 ° C. Although low temperature is preferable from the viewpoint of increasing crystal growth slowly, it takes a long time for crystallization. BookReference example 4When the heat treatment is performed at 600 ° C., the crystallization is almost completed in 10 hours. However, if it is 550 ° C., the heat treatment time is 100 hours or more, and if it is 700 ° C., it takes about 1 hour. The heat treatment temperature is determined by such length, but is preferably about 530 ° C. to about 670 ° C., more preferably about 550 ° C. to 650 ° C., and more preferably about 570 ° C. to 630 ° C.
[0088]
  Next, tantalum was deposited by sputtering, and a gate electrode 409 was formed by patterning. BookReference example 4In this case, tantalum is used as the gate electrode material, but it is needless to say that other conductive materials are possible, and the formation method is not limited to the sputtering method, and the vapor deposition method and the CVD method are also possible. After the gate electrode was formed, an element serving as a donor or acceptor was ion-implanted 410 using the gate electrode as a mask to form a source / drain region 411 and a channel region 412 (FIG. 4C). BookReference example 4Then, with the aim of making an NMOS transistor, 5% phosphine diluted with hydrogen was implanted with a mass non-separation type ion implantation apparatus. The acceleration voltage is 110 kv and the total ion implantation amount including hydrogen atoms is 1.0 × 10¹⁶cm^-2It was in. Subsequently, the SiOCVD layer 413 is formed by APCVD.₂A film of 5000 ５ was deposited. This deposit is bookReference example 4In the base SiO₂The conditions were the same as the conditions for depositing the film 402, and only the deposition time was changed. After the formation of the interlayer insulating film, a heat treatment was performed at 300 ° C. for 1 hour in nitrogen in order to activate the implanted ions and bake the interlayer insulating film. The sheet resistance value of the source / drain region after the heat treatment was (56 ± 12) kΩ / □ with a 95% reliability coefficient. BookReference example 4Then, ion implantation was performed with a mass non-separation type ion implantation apparatus and activation of the implanted ions was performed by low-temperature heat treatment at 300 ° C., but not limited thereto, for example, ion implantation with a normal mass separation type ion implantation apparatus, It may be activated by laser irradiation. Thereafter, contact holes are opened, and source / drain extraction electrodes 414 are formed by sputtering or the like, thereby completing the transistor (FIG. 4d). BookReference example 4Then, aluminum was used as a source / drain extraction electrode material and deposited to a thickness of 8000 mm by sputtering to form a source / drain extraction electrode. At this time, the sheet resistance of the deposited aluminum film was 42.5 ± 2.0 mΩ / □.
[0089]
The characteristics of the prototyped thin film transistor (TFT) were measured at a temperature of 25 ° C. The transistor size was a channel portion length L = 10 μm and a width W = 10 μm. Defects and unpaired electrons in the SPC film are terminated with oxygen ions, the quality of the lower gate oxide film 404 is improved by oxygen ion implantation and subsequent heat treatment, and the upper gate oxide film 406 is in an oxidizing atmosphere. The transistor characteristics were greatly improved by the improvement by the heat treatment below and the use of a silicon nitride film having a large dielectric constant as the intermediate layer of the gate insulating film. Actual on-current (Vds = 4V, Vgs = 15V) is 4.3 × 10^-FiveA increases to about three times that of the conventional comparative example, and the minimum value of Ids is also when the gate voltage is 0 V, and the values (IOFF: Vds = 4 V, Vgs = 0 V) are also 8.9 × 10^-14And showed good values. As a result, a thin film semiconductor device having excellent switching characteristics in which the on / off ratio with respect to the modulation of the gate voltage of 15 V reaches 8.7 digits was realized.
[0090]
  BookReference example 4In this case, the lower gate oxide film is deposited by the CVD method, but it can also be formed by an oxygen ion implantation method and a subsequent heat treatment. In this case, first, an amorphous semiconductor film 403 is deposited by about 600 mm and patterned. Next, after the silicon nitride film 405 is continuously deposited on the order of about 1000 mm and the upper silicon oxide film 406 is deposited on the thickness of about 200 mm, oxygen ions are implanted into the interface between the amorphous semiconductor film and the silicon nitride film. The implantation amount is such that the lower oxide film 404 is formed in an amount of about 300 mm so that the range center comes closer to the nitride film side than the interface. For example, when oxygen ions are implanted at an acceleration voltage of 55 keV, the range and range deviation are about 1075 mm and 325 mm, respectively. Accordingly, the range center can be formed on the nitride film side about 125 mm from the interface, and oxygen ions are distributed within about 200 mm on the surface of the amorphous semiconductor film. The driving amount is 6.5 × 10¹⁷cm^-2After that, by performing a heat treatment, a lower oxide film 404 of about 300 mm is formed on the surface of the semiconductor film, and the thickness of the crystallized semiconductor film 408 is about 400 mm. This heat treatment may be the same as the above-described heat treatment at about 600 ° C. for about ten hours. The followingReference example 4A thin film semiconductor device is manufactured in the same process. BookReference example 4Then, although the lower oxide film 404, the nitride film 405, and the upper oxide film 406 are continuously formed, these films may be formed by another apparatus. In that case, if this method is used, the process is simplified to the extent that the lower oxide film 404 need not be deposited.
[0091]
As described above, according to the present invention, a high-quality semiconductor film, a MOS interface and a gate insulating film can be obtained, and an impurity serving as a donor or acceptor can be added to obtain a low-resistance electric conductive film. This is because an excellent thin film semiconductor device can be obtained.
[0092]
【The invention's effect】
As described above, according to the present invention, a high-quality semiconductor film can be formed without using an expensive and troublesome apparatus such as an ECR-PECVD apparatus, and without performing a hydrogenation process with a normal simple apparatus. It became possible to get easily. This makes it possible to form a thin film semiconductor device having excellent transistor characteristics over a large area by a simple and simple technique, and to increase the performance and reduce the performance of an active matrix liquid crystal display using multilayered LSIs and thin film transistors. It has a great effect of realizing the price.
[0093]
Further, according to the present invention, it becomes possible to keep the inside of the heat treatment furnace and the CVD apparatus clean without using a load lock chamber, so that a high quality film can be formed very easily. This also has the great effect of realizing higher performance and lower cost of LSIs and liquid crystal displays.
[0094]
Further, according to the present invention, a high-quality semiconductor film, a MOS interface, and a gate insulating film are formed, and a thin-film semiconductor device having extremely excellent transistor characteristics can be formed on a large area. It has a great effect of realizing the conversion.
[Brief description of the drawings]
FIG. 1 is a diagram showing the effect of the present invention.
FIG. 2 is a cross-sectional view of an element in each process of manufacturing a silicon thin film semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an element in each process of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.
4 is a cross-sectional view of an element in each process of manufacturing a silicon thin film semiconductor device according to an embodiment of the present invention. FIG.
FIG. 5 is a diagram for explaining reverse taper of etching.
FIG. 6 is a view for explaining a forward taper of etching.
[Explanation of symbols]
201: base substrate
202 ... Underlying protective film
203 ... Semiconductor film
204 ... Gate insulating film
205 ... Gate electrode
206 ... Ion implantation
207 ... Source / drain region
208 ... Channel area
209 ... Interlayer insulating film
210 ... Source / drain extraction electrode
301 ... Substrate substrate
302. Base protective film
303 ... Amorphous semiconductor film
304 ... Gate insulating film
305 ... Crystallized semiconductor film
306 ... Gate electrode
307 ... Ion implantation
308 ... Source / drain region
309 ... Channel area
310 ... Interlayer insulating film
311 ... Source / drain extraction electrode
401: base substrate
402: Base protective film
403: Amorphous semiconductor film
404 ... Oxide film
405 ... Nitride film
406 ... Oxide film
407 ... oxygen ion implantation
408 ... Crystallized semiconductor film
409 ... Gate electrode
410 ... Ion implantation
411 ... Source / drain region
412 ... Channel area
413 ... Interlayer insulating film
414 ... Source / drain extraction electrode

Claims

A semiconductor film forming method for forming a polycrystalline semiconductor film on a substrate having at least a surface made of an insulating material,
A first step of forming an amorphous semiconductor film on the substrate;
The substrate on which the amorphous semiconductor film is formed is heat-treated in an oxidizing atmosphere having an oxygen partial pressure in the range of 5 mtorr to 50 torr to crystallize the amorphous semiconductor film to form the polycrystalline semiconductor film. A method for forming a semiconductor film, comprising:

A semiconductor film forming method for forming a polycrystalline semiconductor film on a substrate having at least a surface made of an insulating material,
A first step of forming an amorphous semiconductor film on the substrate;
The substrate on which the amorphous semiconductor film is formed is heat-treated in an atmosphere of laughing gas, water, or carbon dioxide whose gas partial pressure is in the range of 1 mtorr to 10 torr, thereby crystallizing the amorphous semiconductor film. And a second step of forming the polycrystalline semiconductor film.

In the semiconductor formation method of Claim 1 or 2,
A method of forming a semiconductor film, comprising a step of removing a natural oxide film from the surface of the amorphous semiconductor film before the second step.

In the semiconductor film formation method of Claims 1 thru | or 3,
A method of forming a semiconductor film, characterized in that silicon is contained in an element constituting the crystalline semiconductor film.

A semiconductor device manufacturing method using the semiconductor forming method according to claim 1.