JPS63250863A - Field-effect semiconductor device - Google Patents
Field-effect semiconductor deviceInfo
- Publication number
- JPS63250863A JPS63250863A JP8630887A JP8630887A JPS63250863A JP S63250863 A JPS63250863 A JP S63250863A JP 8630887 A JP8630887 A JP 8630887A JP 8630887 A JP8630887 A JP 8630887A JP S63250863 A JPS63250863 A JP S63250863A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- doped
- gaas
- electron
- ingaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000005669 field effect Effects 0.000 title claims abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 38
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 150000001875 compounds Chemical class 0.000 claims abstract description 5
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 19
- 230000008859 change Effects 0.000 abstract description 3
- 230000002085 persistent effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 50
- 230000006872 improvement Effects 0.000 description 8
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 240000002329 Inga feuillei Species 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- FVJPPEWHZCSTAC-UHFFFAOYSA-N meta-O-Dealkylated flecainide Chemical compound OC1=CC=C(OCC(F)(F)F)C(C(=O)NCC2NCCCC2)=C1 FVJPPEWHZCSTAC-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は電界効果型半導体装置に関し、特にInGaA
s系変調ドープPET (MODFET)における素子
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to field effect semiconductor devices, particularly InGaA semiconductor devices.
The present invention relates to an element structure in an s-based modulation doped PET (MODFET).
(ロ)従来の技術
一般に、化合物半導体は、キャリアの易動度が大きいこ
とや、その多くが直接遷移型半導体であること等の長所
により、超高速半導体素子や発光素子等、他方面にわた
ってその用途が拡大している。また、分子線エピタキシ
ャル成長は、他の結晶成長では作製できない急峻なヘテ
ロ界面の成長が可能である等の元来の長所に加え、近年
、基板直接加熱法や、各ソースるつぼの大口径化や成長
時の基板回転の高速化による成長層の均一性向上等の改
良により、化合物半導体装置製作の基盤技術として、急
速に進歩している。また、上記超高速半導体素子におい
ては、低雑音化、高利得化のため、相互コンダクタンス
g1の向上、ソース抵抗Rsおよびゲート人力容@Cg
sの低減化が進められており、これにより、例えば、ゲ
ート長の短縮化や活性層最下部のキャリア濃度を高くす
るベリラドチャンネルプロファイルの採用や、表面n゛
層導入とそれに伴う深いリセス構造の採用およびドリフ
ト速度の高い電子を得るべくAlGaAs/GaAs、
GaAs/InGaAs、AlGaAs/InGaAs
等のへテロ接合を利用したM OD F ETの採用等
が行われている。(b) Conventional technology In general, compound semiconductors have advantages such as high carrier mobility and the fact that most of them are direct transition type semiconductors, so they are used in ultrahigh-speed semiconductor devices, light-emitting devices, etc. Its uses are expanding. In addition to the original advantages of molecular beam epitaxial growth, such as the ability to grow steep hetero-interfaces that cannot be produced with other crystal growth methods, in recent years, direct heating of the substrate, larger diameters of each source crucible, and growth Due to improvements such as improved uniformity of the grown layer due to faster substrate rotation, it is rapidly progressing as a basic technology for manufacturing compound semiconductor devices. In addition, in the above-mentioned ultra-high-speed semiconductor device, in order to reduce noise and increase gain, the mutual conductance g1 is improved, the source resistance Rs and the gate force capacity @Cg
Progress is being made to reduce s, and this has resulted in, for example, shortening the gate length, adopting a Verirad channel profile that increases the carrier concentration at the bottom of the active layer, and introducing an n layer on the surface and the accompanying deep recess structure. In order to obtain electrons with high drift speed, AlGaAs/GaAs,
GaAs/InGaAs, AlGaAs/InGaAs
MOD FETs using heterojunctions such as these have been adopted.
上記M OD F E Tにおいては、従来、第3図に
示すような、AlGaAs/GaAsMMODFETが
最も一般的であり、これはGaAs基板l上にノンドー
プGaAsバッファ一層2およびSiドープn”−AI
GaAs層4を成長させ、電子供給層であるSiドープ
n”−AIGaAs層4と電子走行層であるノンドープ
GaAsバッファ一層2との間にノンドープAlGaA
sスペーサ一層3を設けることにより、2次元電子ガス
を電子供帖層4中のイオン化ドナーによるクローン場か
ら遠ざけて電子の易動度を高める等の改良が行われてい
る。Conventionally, the most common type of MOD FET is an AlGaAs/GaAs MMODFET as shown in FIG.
A GaAs layer 4 is grown, and non-doped AlGaA is grown between the Si-doped n''-AIGaAs layer 4 which is an electron supply layer and the non-doped GaAs buffer layer 2 which is an electron transport layer.
By providing the s-spacer layer 3, improvements such as increasing the mobility of electrons by moving the two-dimensional electron gas away from the clone field caused by the ionized donors in the electron book layer 4 have been made.
また、近年、第4図に示すように、電子走行層2および
スペーサ一層3間にGaAsよりも電子の飽和速度の高
いInGaAs層7を有するAlGaAs/InGaA
s系MODFETや、第5図に示すように、InGaA
s層7上にノンドープGaAsスペーサ一層8を介して
Siドープn”−GaAs層9が成長されたGtIA5
/ I nGaAs系MODFET等が提案されており
、電子のドリフト速度を高くする改良が行われている。In addition, in recent years, as shown in FIG.
s-based MODFET, and as shown in Figure 5, InGaA
GtIA 5 in which a Si-doped n''-GaAs layer 9 is grown on the s-layer 7 with a non-doped GaAs spacer layer 8 interposed therebetween.
/InGaAs-based MODFETs and the like have been proposed, and improvements have been made to increase the electron drift speed.
なお、第3〜5図において、5.6はそれぞれオーミッ
ク、ゲート各電極である。In addition, in FIGS. 3 to 5, 5.6 is an ohmic electrode and a gate electrode, respectively.
(ハ)発明が解渓しようとする問題点
しかしながら、上記MODFET、例えば第3図のごと
きAlGaAs/GaAs系MODFET。(c) Problems to be solved by the invention However, the above-mentioned MODFET, for example, the AlGaAs/GaAs-based MODFET as shown in FIG.
第4図のごときAlGaAs/InGaAs系M OD
FETにおいては電子供給層4としてAlxGa+−
xAsからなる混晶を用いているため、M OD F
ETとして通常用いられているX=0.3程度の混晶比
では、n″AlxGa1.□xAS中によく知られてい
るD−Xセンターが存在し、それが原因となり、FET
のしきい値電圧vthが温度によって変化することや、
Persistent Photoconductiv
ity (P 、 P 。AlGaAs/InGaAs-based MOD as shown in Figure 4
In the FET, AlxGa+- is used as the electron supply layer 4.
Since a mixed crystal consisting of xAs is used, M OD F
At a mixed crystal ratio of about
The threshold voltage vth of
Persistent Photoconductiv
ity (P, P.
C,)等の現象が起こるという欠点がある。また、第5
図のごときGaAs/InGaAs系M OD F E
Tでは、電子供給層9中に、D−Xセンターが存在しな
いため、上記のような不良は生じないが、スペーサ一層
と電子走行層との間の伝導帯の不連続さに関してはGa
AsとInGaAsとの伝導帯の不連続さが、A lx
G al −xA s (X = 0.3)とGaAs
との伝導帯の不連続さく0.3eV)に比べ小さいため
、ヘテロ接合界面の2次元電子のシートキャリア濃度が
、AlGaAs/GaAs系MODFBTに比べ低くな
ってしまい、glの向上に、つながらないという欠点が
ある。There is a drawback that phenomena such as C, ) occur. Also, the fifth
GaAs/InGaAs system MOD F E as shown in the figure
In T, since there is no DX center in the electron supply layer 9, the above-mentioned defects do not occur, but regarding the discontinuity of the conduction band between the spacer layer and the electron transit layer, Ga
The conduction band discontinuity between As and InGaAs causes Alx
Gal-xA s (X = 0.3) and GaAs
Since the conduction band discontinuity (0.3eV) is smaller than that of the conduction band, the two-dimensional electron sheet carrier concentration at the heterojunction interface is lower than that of AlGaAs/GaAs-based MODFBT, which does not lead to an improvement in gl. There is.
本発明は、上記のような構造のMODFETでは不可能
な電子のドリフト速度の向上や、シートキャリア濃度の
増加や、特性安定性の向上等を同時に実現し得る電界効
果型半導体装置を堤供するものである。The present invention provides a field-effect semiconductor device that can simultaneously achieve improvements in electron drift velocity, increase in sheet carrier concentration, and improvement in characteristic stability that are impossible with MODFETs having the above-described structure. It is.
(ニ)問題点を解決するための手段
本発明は、ゲート電極と化合物半導体基板との間に、S
iドープGaAsからなる電子供給層と、InGaAs
からなる電子走行層と、両層の間に介在され、ノンドー
プAlGaAsからなるスペーサ層とを積層してなる電
界効果型半導体装置である。(d) Means for Solving the Problems The present invention provides an S
An electron supply layer made of i-doped GaAs and InGaAs
This is a field-effect semiconductor device formed by laminating an electron transport layer consisting of the above-mentioned electron transit layer and a spacer layer interposed between the two layers and made of non-doped AlGaAs.
すなわち、第4〜5図に示すごとき電子供給層のSiド
ープn″GaAsと電子走行層のInGaAsとの間の
スペーサ層として、ノンドープAlGaAsを用いるこ
とによって、しきい値電圧vthの温度による変化を少
なくすると共にP、P、C,現象の防止を保障したうえ
で、更に電子走行層とスペーサ層との間の伝導帯の不連
続さを改良し、それによって相互インダクタンスg、の
向上を図ることができる。That is, by using non-doped AlGaAs as a spacer layer between the Si-doped n''GaAs of the electron supply layer and the InGaAs of the electron transport layer as shown in FIGS. 4 and 5, changes in the threshold voltage vth due to temperature can be suppressed. In addition to ensuring the prevention of the P, P, and C phenomena, the discontinuity of the conduction band between the electron transit layer and the spacer layer is improved, thereby improving the mutual inductance g. Can be done.
(ホ)作用
本発明の電界効果型半導体装置では、電子供給層として
D−Xセンターの存在しないSiドープGaAsを用い
ているため、従来SiドープAlGaAs層を電子供給
層として用いているものに比べ、しきい値電圧vthの
温度変化が少なく、P、P、C。(e) Function The field-effect semiconductor device of the present invention uses Si-doped GaAs without a DX center as the electron supply layer, and is therefore compared to a conventional device using a Si-doped AlGaAs layer as the electron supply layer. , P, P, C with little temperature change in threshold voltage vth.
が無くなる。また、スペーサ層としてGaAsよりもバ
ンドギャップが大きく、かつ、電子親和力の小さいノン
ドープAlGaAs層を用いているため、電子走行層で
あるInGaAsとの伝導帯の不連続さを従来のGaA
s/1nGaAs系M OD F E Tよりも大きく
することができ、2次元電子ガスのシートキャリア濃度
を高めることが可能となり、g、の向上が実現できる。disappears. In addition, since a non-doped AlGaAs layer with a larger band gap and lower electron affinity than GaAs is used as the spacer layer, the discontinuity of the conduction band with InGaAs, which is the electron transport layer, is reduced compared to that of conventional GaAs.
It can be made larger than the s/1nGaAs-based MOD FET, the sheet carrier concentration of the two-dimensional electron gas can be increased, and an improvement in g can be realized.
(へ)実施例
以下、第1及び第2図を参照しながら本発明の一実施例
を工程順に詳細に説明する。(F) Example Hereinafter, an example of the present invention will be described in detail in the order of steps with reference to FIGS. 1 and 2.
まず、GaAs基板を分子線エビタキシー(Molec
ular Beam Epitaxy、以下M B E
と称す)に使用する前に硫酸系エッチャント(硫酸:過
酸化水素:水=3:1:l)中に30秒間浸漬し、前処
理を行う。次に、GaAs基板をMBE装置の成長室に
搬入し、As圧力下で、600℃、1時間のベーキング
を行い、GaAs基板表面に付着している酸化膜を除去
する。その後、基板温度を580℃に下げ、G a(8
84℃)セルシャッターを開け、第2図(a)に示すよ
うに、GaAs基板1上にノンドープGaAsからなる
バッファ一層2を1μm成長させる。その後、I n(
950℃)セルシャッターを開け、ノンドープInGa
As7からなる電子走行層を300人成長させる。その
後、I n(950℃)セルシャッターを閉じ、同時に
A I(1020℃)セルシャッターを開け、ノンドー
プAlGaAs3からなるスペーサ一層を30人成長さ
せる。さらに、A I(1020℃)セルの温度を、毎
秒1℃の割合で下げA1セルが950℃に達した所でA
Iセルシャッターを閉じ、同時にS i (1040℃
)セルシャッターを開け、Siドープn′″−GaAs
9からなる電子供給層を6000人成長させる。その後
、Siセルシャッター及びGaセルシャッターを同時に
閉じ、基板温度を400℃まで下げ、Asセルシャッタ
ーを閉じた後、基板温度を室温にもどす。その後、Ga
As基板1をMBE成長室から取り出す。First, a GaAs substrate was coated with molecular beam epitaxy (Molec).
ular beam epitaxy, hereinafter MBE
Before using it in a sulfuric acid-based etchant (sulfuric acid: hydrogen peroxide: water = 3:1:l), it is immersed for 30 seconds for pretreatment. Next, the GaAs substrate is carried into a growth chamber of an MBE apparatus, and baked at 600° C. for 1 hour under As pressure to remove the oxide film adhering to the surface of the GaAs substrate. After that, the substrate temperature was lowered to 580°C, and Ga(8
84 DEG C.) The cell shutter was opened, and a buffer layer 2 made of undoped GaAs was grown to a thickness of 1 .mu.m on the GaAs substrate 1, as shown in FIG. 2(a). Then I n (
950℃) Open the cell shutter and remove the non-doped InGa.
Grow 300 electron transport layers consisting of As7. Thereafter, the I n (950° C.) cell shutter is closed and the A I (1020° C.) cell shutter is simultaneously opened to grow 30 single layer spacers made of non-doped AlGaAs3. Furthermore, the temperature of the A I (1020°C) cell was lowered at a rate of 1°C per second, and when the A1 cell reached 950°C, the
Close the I cell shutter and at the same time S i (1040℃
) Open the cell shutter and remove Si-doped n'''-GaAs.
Grow the electron supply layer consisting of 9 people by 6000 people. Thereafter, the Si cell shutter and the Ga cell shutter are closed simultaneously to lower the substrate temperature to 400° C., and after the As cell shutter is closed, the substrate temperature is returned to room temperature. After that, Ga
The As substrate 1 is taken out from the MBE growth chamber.
その後、GaAs成長層上にフォトレジストを用いてメ
サパターンIOを形成する(第2図(a)参照)。その
後、このメサパターン10をマスク材として、成長層の
エツチングを行い(第2図(b)参照)、素子間を分離
さけ、その後上記メサエッチング用フォトレジストIO
を、有機溶剤を用いて除去する。その後、通常のフォト
リソグラフィー、電極蒸着、アロイ処理を行い、オーミ
ック電極5を形成する(第2図(c)参照)。その後、
フォトレジストを用いてゲートパターンIIを形成しく
第2図(d)参照)、このゲートパターン11をマスク
材として、n”−GaAs層9の一部をリン酸系エッチ
ャント(リン酸:過酸化水素:水=3+l:50)を用
いてエツチングし、第2図(e)に示すようなりセス形
状を得る。その後、ゲート電極6を電子ビームEB蒸着
機を用いて蒸着し、その後上記フォトレジスト11を有
機溶媒を用いて除去し、第1図に示すような構造の電界
効果型半導体装置を得る。Thereafter, a mesa pattern IO is formed on the GaAs growth layer using a photoresist (see FIG. 2(a)). Thereafter, using this mesa pattern 10 as a mask material, the growth layer is etched (see FIG. 2(b)) to avoid separation between elements, and then the photoresist IO for mesa etching is etched.
is removed using an organic solvent. Thereafter, ordinary photolithography, electrode deposition, and alloying processing are performed to form the ohmic electrode 5 (see FIG. 2(c)). after that,
A gate pattern II is formed using a photoresist (see FIG. 2(d)), and using this gate pattern 11 as a mask, a part of the n''-GaAs layer 9 is etched with a phosphoric acid-based etchant (phosphoric acid: hydrogen peroxide). :water=3+l:50) to obtain a grooved shape as shown in FIG. is removed using an organic solvent to obtain a field effect semiconductor device having a structure as shown in FIG.
以上のような方法でD−Xセンターのない電子供給層を
有し、ヘテロ界面での伝導帯の不連続さの大きい半導体
装置が得られ、2次元電子ガスのシートキャリア濃度を
IX 10”/ am’程度高めることができ、その結
果50m5/mm程度g、を向上することが可能となっ
た。また、vthについては、300に、 77にテ各
々−1,10V、−1,08Vとなり、温度依存性がほ
ぼ無くなり、また、P、P、C,を全く無くすことが可
能となった。By the method described above, a semiconductor device having an electron supply layer without a D-X center and a large conduction band discontinuity at the heterointerface can be obtained, and the sheet carrier concentration of the two-dimensional electron gas can be reduced to IX 10"/ As a result, it became possible to improve g by about 50 m5/mm. Also, vth was -1, 10 V and -1,08 V for 300 and 77, respectively. Temperature dependence has almost disappeared, and it has become possible to completely eliminate P, P, and C.
なお、本発明は、GaAs基板を用いたInGaAs系
MODFETばかりでなく、化合物半導体基板の材料と
して、I nAs、 r nP等を利用したMODF
ETに対しても適用し得る。Note that the present invention is applicable not only to InGaAs-based MODFETs using GaAs substrates, but also to MODFETs using InAs, rnP, etc. as materials for compound semiconductor substrates.
It can also be applied to ET.
(ト)発明の効果
以上のように本発明によれば、電子供給層としてD−X
センターの存在しないSiドープGaAsを用いている
ため、従来SiドープAlGaAs層を電子供給層とし
て用いているものに比べ、しきい値電圧vthの温度変
化か少なく、P、P、C,が無くなる。また、スペーサ
層としてGaAsよりもバンドギャップが大きく、かつ
、電子親和力の小さいノンドープAlGaAs層を用い
ているため、電子走行層であるInGaAsとの伝導帯
の不連続さを従来のGaAs/InGaAs系MODF
’ETよりも大きくすることができ、2次元電子ガスの
シートキャリア濃度を高めることが可能となり、gaの
向上が実現できる効果がある。(g) Effects of the invention As described above, according to the present invention, D-X
Since Si-doped GaAs without a center is used, the temperature change in threshold voltage vth is smaller than that in a conventional Si-doped AlGaAs layer used as an electron supply layer, and P, P, and C are eliminated. In addition, since a non-doped AlGaAs layer with a larger band gap and lower electron affinity than GaAs is used as the spacer layer, the discontinuity of the conduction band with InGaAs as the electron transport layer is reduced compared to the conventional GaAs/InGaAs-based MODF.
'ET, it becomes possible to increase the sheet carrier concentration of the two-dimensional electron gas, and there is an effect that an improvement in ga can be realized.
第1図は本発明の一実施例による。ノンドープスペーサ
一層のみにAlGaAsを用いたGaAs/UnGaA
s系MODFETの断面図、第2図(a)〜(e)は上
記電界効果型半導体装置の工程説明図、第3図は従来構
造のAlGaAs/GaAs系MODFETの断面図、
第4図は従来構造のAlGaAs/InGaAs系M
OD F E Tの断面図、第5図は従来構造のGaA
s/InGaAs系MODFETの断面図である。
l・・・・・・GaAs基板、
2・・・・・・ノンドープGaAsバッファ一層、3・
・・・・・ノンドープAlGaAsスペーサ一層、5・
・・・・・オーミック電極、 6・・・・・・ゲー
ト電極、7−=InGaAs層、
9・・・・・・Siドープn″GaAs層。
第2図(a)
(b)
第2図(C)
第3図
第4図FIG. 1 is in accordance with one embodiment of the present invention. GaAs/UnGaA using AlGaAs only in one layer of non-doped spacer
A sectional view of an s-based MODFET, FIGS. 2(a) to 2(e) are process explanatory diagrams of the field-effect semiconductor device, and FIG. 3 is a sectional view of an AlGaAs/GaAs-based MODFET with a conventional structure.
Figure 4 shows the conventional structure of AlGaAs/InGaAs system M.
A cross-sectional view of OD FET, Figure 5 shows the conventional structure of GaA.
FIG. 2 is a cross-sectional view of an s/InGaAs-based MODFET. l...GaAs substrate, 2...non-doped GaAs buffer layer, 3...
...Non-doped AlGaAs spacer layer, 5.
...Ohmic electrode, 6...Gate electrode, 7-=InGaAs layer, 9...Si-doped n''GaAs layer. Fig. 2 (a) (b) Fig. 2 (C) Figure 3 Figure 4
Claims (1)
プGaAsからなる電子供給層と、InGaAsからな
る電子走行層と、両層の間に介在され、ノンドープAl
GaAsからなるスペーサ層とを積層してなる電界効果
型半導体装置。1. An electron supply layer made of Si-doped GaAs and an electron transport layer made of InGaAs are interposed between the gate electrode and the compound semiconductor substrate, and non-doped Al
A field effect semiconductor device formed by laminating a spacer layer made of GaAs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8630887A JPS63250863A (en) | 1987-04-08 | 1987-04-08 | Field-effect semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8630887A JPS63250863A (en) | 1987-04-08 | 1987-04-08 | Field-effect semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63250863A true JPS63250863A (en) | 1988-10-18 |
Family
ID=13883203
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8630887A Pending JPS63250863A (en) | 1987-04-08 | 1987-04-08 | Field-effect semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63250863A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01187878A (en) * | 1988-01-21 | 1989-07-27 | Mitsubishi Electric Corp | Two-dimensional hetero-junction element |
US5331185A (en) * | 1991-07-17 | 1994-07-19 | Sumitomo Electric Industries, Ltd. | Field effect transistor having a GaInAs/GaAs quantum well structure |
-
1987
- 1987-04-08 JP JP8630887A patent/JPS63250863A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01187878A (en) * | 1988-01-21 | 1989-07-27 | Mitsubishi Electric Corp | Two-dimensional hetero-junction element |
US4967242A (en) * | 1988-01-21 | 1990-10-30 | Mitsubishi Denki Kabushiki Kaisha | Heterojunction field effect transistor |
US5331185A (en) * | 1991-07-17 | 1994-07-19 | Sumitomo Electric Industries, Ltd. | Field effect transistor having a GaInAs/GaAs quantum well structure |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1214575A (en) | Method of manufacturing gaas semiconductor device | |
US5023675A (en) | Semiconductor device | |
JPH06132318A (en) | Heterojunction field-effect transistor and its manufacture | |
JP2873583B2 (en) | High-speed semiconductor devices | |
JPH10209434A (en) | Heterojunction field effect transistor, and its manufacturing method | |
JPH0684957A (en) | High electron mobility field effect semiconductor device | |
JPH05259193A (en) | Semiconductor device | |
JPS63250863A (en) | Field-effect semiconductor device | |
US5311045A (en) | Field effect devices with ultra-short gates | |
JPS6353711B2 (en) | ||
JPH08213594A (en) | Field-effect transistor | |
JPH05235055A (en) | Compound semiconductor device | |
JPH025438A (en) | Insulated-gate field-effect transistor | |
JPH03211839A (en) | Compound semiconductor device and method of manufacturing the same | |
JP2867472B2 (en) | Semiconductor device | |
JP2559412B2 (en) | Semiconductor device | |
JPH0684958A (en) | Inp field effect semiconductor device | |
JPS61276269A (en) | Hetero-junction type field-effect transistor | |
JP2824269B2 (en) | Semiconductor element | |
JPH0323641A (en) | Manufacture of field-effect transistor | |
JPH06163598A (en) | High electron mobility transistor | |
JPH01120871A (en) | Semiconductor device | |
JP3109097B2 (en) | Method for manufacturing field effect transistor and etching method | |
JPH03159135A (en) | Semiconductor device and its manufacture | |
JP2514948B2 (en) | Method for manufacturing semiconductor device |