JPS63237577A - Manufacture of misfet - Google Patents
Manufacture of misfetInfo
- Publication number
- JPS63237577A JPS63237577A JP7325387A JP7325387A JPS63237577A JP S63237577 A JPS63237577 A JP S63237577A JP 7325387 A JP7325387 A JP 7325387A JP 7325387 A JP7325387 A JP 7325387A JP S63237577 A JPS63237577 A JP S63237577A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate electrode
- thickness
- film
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 abstract description 24
- 239000010409 thin film Substances 0.000 abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000005498 polishing Methods 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000123 paper Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＭＩＳＦＥＴ製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a MISFET manufacturing method.
近年、ＳＯＩ基板（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ｏｎ
Ｉｎ５ｕｌａｔｏｒ）を用いた積層デバイスが多く考
案されている。その−例として、Ａ、 Ｈ，５ｈａｈら
による積層ＣＭＯ５ＳＲＡＭ（１９８４，シンポジウム
オン ブイエルニスアイシンポジウム、ダイジェスト
オン テクニカルペーパース、 （１９８４，Ｓｙｍ
ｐｏｓｉｕｍ ｏｎ ＶＬＳＩ Ｔｅｃｈｎｏ−１ｏｇ
ｙ Ｄｉｇａｓｔ ｏｆ Ｔｅｃｈｎｉｃａｌ ｐａｐ
ｅｒｓ））がある。そう
の構造を第２図に示す０図より、ゲート電極３をｎＭＯ
３ＦＥＴと９ＭＯ３ＦＥＴとを共通に使用していること
がわかる。In recent years, SOI substrates (Semiconductor on
Many laminated devices using In5ulator) have been devised. As an example, a stacked CMO5 SRAM by A. H. Hah et al.
posium on VLSI Techno-1og
y Digast of Technical pap
ers)). The gate electrode 3 is made of nMO.
It can be seen that 3FET and 9MO3FET are used in common.
しかしながら、上層に位置するｐ ＭＯＳＦＥＴ用の半
導体膜表面が平坦化されていないため、ソース・ドレイ
ン領域を形成するときに、イオン注入用マスクとして使
用するフォトレジストの露光精度が上がらず、これが素
子の微細化にとって欠点となっている。However, since the surface of the semiconductor film for the p-MOSFET located in the upper layer is not planarized, the exposure accuracy of the photoresist used as an ion implantation mask when forming the source/drain regions cannot be improved, and this results in This is a drawback for miniaturization.
本発明の目的はこのような従来の欠点を除去したにｌ５
ＦＥＴ製造方法を提供することにある。The purpose of the present invention is to eliminate such conventional drawbacks.
An object of the present invention is to provide a FET manufacturing method.
本発明、はＳＯＩ基板を用いた肘５ＦＥＴ製造方法にお
いて、半導体基板上に絶縁膜とゲート電極とを順次形成
し、その後、前記ゲート電極表面にゲート絶縁膜を成長
させ、更に前記ゲート電極膜厚とゲート絶縁膜厚との合
計膜厚より厚い半導体膜を形成したのち、前記ゲート絶
縁膜が露出しない程度に前記半導体膜表面を平坦化し、
次にチャネル領域となる部分にイオン注入用マスクを形
成したのち、イオン注入によりソースおよびドレイン領
域を形成することを特徴とするＭＩＳＦＥＴ製造方法で
ある。The present invention is a method for manufacturing an elbow 5FET using an SOI substrate, in which an insulating film and a gate electrode are sequentially formed on a semiconductor substrate, and then a gate insulating film is grown on the surface of the gate electrode, and the gate electrode film thickness is After forming a semiconductor film thicker than the total thickness of the gate insulating film and the gate insulating film, planarizing the surface of the semiconductor film to such an extent that the gate insulating film is not exposed,
This MISFET manufacturing method is characterized in that, after forming an ion implantation mask in a portion that will become a channel region, source and drain regions are formed by ion implantation.
゛以下、本発明の実施例について図面を参照して詳細に
説明する。゛Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
ここで、ＭＩＳＦＥＴとして、シリコンを用いたｎＭ。Here, the MISFET is an nM transistor using silicon.
５ＦＥＴを例にとって説明する。シリコンは他の半導体
膜でも、また、ｎ ＭＯ５ＦＥＴ以外にｐ ＭＯＳＦＥ
Ｔでも可能である。This will be explained using a 5FET as an example. Silicon is also used in other semiconductor films, and in addition to n MO5FET, p MOSFE
It is also possible with T.
第１図（ａ）において、Ｓｉ基板１上にまず１μ５Ｓｉ
Ｏ□２を熱酸化法により形成する。つぎに、ｎ ”ｐｏ
ｌｙ−３ｉをＬＰＣＶＤ法により０．５−成長したのち
、ゲート電極３をレジスト工程およびエツチング工程に
より形成する。つぎに、熱酸化法を用いてゲート電極３
の表面に絶縁膜としてゲート酸化膜４を４００人成長さ
せる。その後、第１図（ｂ）に示すように０．７−の膜
厚を有するＳｉ薄膜５を堆積させる。このＳｉ薄膜５の
表面にはゲート電極３の形状に対応した凹凸が形成され
る。この凹凸を平坦化するために機械化学研磨法を用い
てゲート酸化膜４の表面が露出しない程度に表面を研磨
し、第１図（ｃ）に示すような表面が平坦化されたＳｉ
薄膜６を得る。このとき、ゲート電極３上のＳｉ薄膜６
の膜厚は０．１μｍ以下となるようにする。In FIG. 1(a), first 1μ5Si is placed on the Si substrate 1.
O□2 is formed by a thermal oxidation method. Next, n”po
After growing ly-3i by 0.5-cm by the LPCVD method, the gate electrode 3 is formed by a resist process and an etching process. Next, the gate electrode 3 is made using a thermal oxidation method.
A gate oxide film 4 is grown as an insulating film on the surface of 400 layers. Thereafter, as shown in FIG. 1(b), a Si thin film 5 having a thickness of 0.7 - is deposited. On the surface of this Si thin film 5, irregularities corresponding to the shape of the gate electrode 3 are formed. In order to flatten these irregularities, the surface of the gate oxide film 4 is polished using a mechanical chemical polishing method to such an extent that the surface of the gate oxide film 4 is not exposed.
A thin film 6 is obtained. At this time, the Si thin film 6 on the gate electrode 3
The film thickness is set to be 0.1 μm or less.
つぎにに第１図（ｄ）のようにチャネル領域となる部分
を覆うようにフォトレジスト７を露光したのち、ソース
領域８およびドレイン領域９を形成するために、ヒ素元
素をイオン注入により導入する。Next, as shown in FIG. 1(d), after exposing the photoresist 7 to cover the portion that will become the channel region, arsenic element is introduced by ion implantation in order to form the source region 8 and the drain region 9. .
その後、第１図（ｅ）に示すように表面保護膜となる５
ｉｎ２１０を０．５μｍＬＰｃＶＤ法により成長し、ソ
ース領域８、ドレイン領域９にコンタクト孔を開孔し、
ＡＱによるソース電極１１およびドレイン電極１２を形
成して肘５ＦＥＴを完成する。Thereafter, as shown in FIG. 1(e), 5
In210 was grown by 0.5 μm LPcVD method, and contact holes were formed in the source region 8 and drain region 9.
A source electrode 11 and a drain electrode 12 are formed using AQ to complete the elbow 5FET.
本発明のゲート電極をＳＯＩ薄膜の裏面に有したＭＩＳ
ＦＥＴの製造方法によれば、 ＳＯＩ薄膜表面を研磨な
どにより平坦化し、さらにチャネル領域となるＳＯＩ薄
膜の膜厚を薄くできるため、素子の微細化に際し、素子
の露光の工程や素子の電気特性にとって極めて有利であ
り、また、チャネル領域となる半導体膜が平坦化処理に
よって薄膜化されるため１作製したＭＯＳＦＥＴのドレ
イン電流−ゲート電圧特性において、サブスレッショル
ド電流の傾きをより急峻なものにすることができる。MIS with the gate electrode of the present invention on the back surface of the SOI thin film
According to the FET manufacturing method, the surface of the SOI thin film can be flattened by polishing, etc., and the thickness of the SOI thin film that will become the channel region can be made thinner, so when miniaturizing the device, it is possible to improve the exposure process of the device and the electrical characteristics of the device. This is extremely advantageous, and since the semiconductor film that will become the channel region is made thinner by the planarization process, it is possible to make the slope of the subthreshold current steeper in the drain current-gate voltage characteristics of the MOSFET that is manufactured. can.
第１図（ａ）〜（ｅ）は本発明の実施例を工程順に示す
断面図、第２図は従来例を示す断面図である。
１・・・Ｓｉ基板 ２，１０・・・Ｓｉｎ
。
３・・・ゲート電極 ４・・・ゲート酸化膜５
．６・・・Ｓｉ薄膜 ７・・・フォトレジ
スト８・・・ソース領域 ９・・・ドレイン領
域１１・・・ソース電極 １２・・・ドレイン
電極（α）
（ｂ）
（Ｃ）
苑１図FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing a conventional example. 1...Si substrate 2,10...Sin
. 3... Gate electrode 4... Gate oxide film 5
．． 6...Si thin film 7...Photoresist 8...Source region 9...Drain region 11...Source electrode 12...Drain electrode (α) (b) (C) Figure 1
Claims (1)
て、半導体基板上に絶縁膜とゲート電極とを順次形成し
、その後、前記ゲート電極表面にゲート絶縁膜を成長さ
せ、更に前記ゲート電極膜厚とゲート絶縁膜厚との合計
膜厚より厚い半導体膜を形成したのち、前記ゲート絶縁
膜が露出しない程度に前記半導体膜表面を平坦化し、次
にチャネル領域となる部分にイオン注入用マスクを形成
したのち、イオン注入によりソースおよびドレイン領域
を形成することを特徴とするＭＩＳＦＥＴ製造方法。(1) In a MISFET manufacturing method using an SOI substrate, an insulating film and a gate electrode are sequentially formed on a semiconductor substrate, and then a gate insulating film is grown on the surface of the gate electrode, and the thickness of the gate electrode and the gate electrode are After forming a semiconductor film that is thicker than the total thickness including the insulating film thickness, the surface of the semiconductor film is flattened to such an extent that the gate insulating film is not exposed, and then an ion implantation mask is formed in a portion that will become a channel region. A method for manufacturing a MISFET, characterized in that source and drain regions are formed by ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7325387A JPS63237577A (en) | 1987-03-26 | 1987-03-26 | Manufacture of misfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7325387A JPS63237577A (en) | 1987-03-26 | 1987-03-26 | Manufacture of misfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63237577A true JPS63237577A (en) | 1988-10-04 |
| JPH0586074B2 JPH0586074B2 (en) | 1993-12-09 |
Family
ID=13512825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7325387A Granted JPS63237577A (en) | 1987-03-26 | 1987-03-26 | Manufacture of misfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63237577A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439967A (en) * | 1990-06-05 | 1992-02-10 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor |
| JPH05275452A (en) * | 1992-03-25 | 1993-10-22 | Semiconductor Energy Lab Co Ltd | Thin film insulated-gate type semiconductor device and its manufacture |
| JPH0799317A (en) * | 1993-08-12 | 1995-04-11 | Semiconductor Energy Lab Co Ltd | Insulated thin-film gate type semiconductor device and manufacture thereof |
| US6124155A (en) * | 1991-06-19 | 2000-09-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and thin film transistor and method for forming the same |
| US6331717B1 (en) * | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JP2009033134A (en) * | 2007-06-29 | 2009-02-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device, method for manufacturing semiconductor device, and electronic appliance |
-
1987
- 1987-03-26 JP JP7325387A patent/JPS63237577A/en active Granted
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439967A (en) * | 1990-06-05 | 1992-02-10 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor |
| US6797548B2 (en) | 1991-06-19 | 2004-09-28 | Semiconductor Energy Laboratory Co., Inc. | Electro-optical device and thin film transistor and method for forming the same |
| US6756258B2 (en) | 1991-06-19 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US6124155A (en) * | 1991-06-19 | 2000-09-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and thin film transistor and method for forming the same |
| US6166399A (en) * | 1991-06-19 | 2000-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix device including thin film transistors |
| US6847064B2 (en) | 1991-06-19 | 2005-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a thin film transistor |
| US6335213B1 (en) | 1991-06-19 | 2002-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and thin film transistor and method for forming the same |
| US6323069B1 (en) | 1992-03-25 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using light irradiation to form impurity regions |
| US6569724B2 (en) | 1992-03-25 | 2003-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and method for forming the same |
| JPH05275452A (en) * | 1992-03-25 | 1993-10-22 | Semiconductor Energy Lab Co Ltd | Thin film insulated-gate type semiconductor device and its manufacture |
| US6887746B2 (en) | 1992-03-25 | 2005-05-03 | Semiconductor Energy Lab | Insulated gate field effect transistor and method for forming the same |
| JPH0799317A (en) * | 1993-08-12 | 1995-04-11 | Semiconductor Energy Lab Co Ltd | Insulated thin-film gate type semiconductor device and manufacture thereof |
| US6331717B1 (en) * | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US6437366B1 (en) | 1993-08-12 | 2002-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US6500703B1 (en) | 1993-08-12 | 2002-12-31 | Semicondcutor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US7381598B2 (en) | 1993-08-12 | 2008-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JP2009033134A (en) * | 2007-06-29 | 2009-02-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device, method for manufacturing semiconductor device, and electronic appliance |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0586074B2 (en) | 1993-12-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |