JPS5834934B2 - How to form microstructures - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a fine structure of a semiconductor element, etc.
An opening is formed in the layer (first layer) formed on the substrate, and only a part or one side of the side wall (inner surface) of the opening is side-etched, and the part removed by the side etching is removed. When forming a required area in or on a substrate through a process, even if there are demands for miniaturization, dimensional accuracy, and alignment that go beyond the limits of conventional photoetch technology, it can meet these demands well. The purpose is to provide a method.

As mentioned above, in order to first explain how the technique of selectively side-etching only a part or one side of the side wall of the opening has been used in the manufacturing process of various devices, we will introduce the first part.
3, a conventional manufacturing process for a field effect transistor will be explained as an example.

As shown in FIG. 1-a, in this example, a semiconductor substrate is used as the substrate 1, and as will be described later, the first layer to be subjected to selective side etching is the 5i02 layer formed thereon. Membrane 2 does this.

Further, the second mask material 3 described later may be a polycrystalline Si film.

The manufacturing steps are explained below. First, Si is deposited on the semiconductor substrate 1.
A relatively thick O2 film 2 (for example, 1μ or more) is resistant to adhesion or formed, and a thin film (for example, about 500 people) is formed on top of it.
is N4 film 3 is resistant to adhesion or generated.

In a normal hot etching process, in order to photoetch the Si 3 N 4 film 3 with good control, a SiO 2 film 4 is further deposited (FIG. 1-a).

Next, as shown in FIG. 1-b, openings 5 and 6 are formed through the multilayer thin film using a conventional photoetching technique.

That is, a resist film is adhered onto the S102 film 4 using photoetching technology, and this resist film is selectively subjected to a photo exposure process to dissolve away portions corresponding to the openings 5 and 6 with a developer, and then subjected to appropriate processing. 81 through that part.
02 membrane 4 is dissolved away with an HF-based solution, and then the S i 3N4 membrane 3 is dissolved away with a heated phosphoric acid-based solution, and the S i 3N4 film 3 is dissolved away.
t 3 Using the openings in the N4 film 3 as a mask, thick S i02
Film 2 is selectively etched.

At this time, since the resist has already been removed with a heated phosphoric acid solution, the thick SiO2 film 2 is selectively etched, so that the thin SiO2 film 4 on the top is completely dissolved away.

However, the S 13 N4 film 3 remains as a mask because it is not soaked in the HF-based liquid.

Thereafter, impurities having a conductivity type opposite to that of the substrate 1 are diffused through the openings 5 and 6 to form regions 10.11 near the surface of the substrate.

With this diffusion, an oxide film 10 is formed on the surface of the region 10.11.
I, 111 may be formed.

Next, the process moves to a step of performing side etching not on the entire side wall of the opening 5, but only on one side of the necessary part or cross section.

For this purpose, in this example, the S t 3 N 4 film 3 is interposed between the two, but the side surface of the opening 5 of the SiO □ film 2 on which side etching is not desired is placed in the It is covered with a third layer 7 of masking material.

Of course, in the conventional manufacturing process described here, this layer 7
The selective formation of is done by conventional photoetching techniques,
Therefore, it has the drawbacks described below.

Incidentally, since the side etching is targeted, there is no need to consider the intervening layer 3, and the SiO□ film 2 can be called the first layer and the selective side etching mask layer 7 can be called the second layer.
It can also be said that the first layer consists of layers 2 and 3.

In any case, only the main operating portion can be formed by forming the mask layer 7 for side-etching a portion of the opening in the first layer and then performing side-etching.

(Figure 1d).

Next, as shown in FIG. 1-e, the third mask material 7 is removed, and if necessary, the second layer S t 3 N4 is removed.
The film 3 is removed, and an insulating film 13 is formed on the entire semiconductor surface or a side-etched portion of the semiconductor surface by oxidation, vapor phase growth, vapor deposition, or the like.

Finally, as shown in Figure 1-f, contact holes IOC and 11C are formed on regions 10 and 11, and
0.11, electrodes 10E and IIE are formed through contact holes 1oc and iic, and a control electrode 14 is formed on the insulating film 13 of the main operating portion 12 at the end of the region 10 and Si0
It is formed so as to span two films 2.

The main part of the device is completed by forming the electrode 1E on the substrate 1.

For example, if the substrate 1 is p-type and the high-resistance Si1 regions 10 and 11 are n-type, this device becomes a depletion type high frequency field effect transistor.

The effective channel length is shown in the figure.

Therefore, in principle, it should be possible to easily make it to a submicron length, and therefore the human power capacity is small and the cutoff frequency is high.

And that's it. can be obtained almost uniformly in the direction perpendicular to the drawing.

When the region 10 is used as a source and the region 11 is used as a drain, the capacitance between the electrode 14, which is the gate, and the drain becomes very small, resulting in a reasonable device with small feedback capacitance.

The above description is for a device in which an inversion layer is already induced on the semiconductor surface in region 10.11, but if an inversion layer is not induced, a relatively high voltage is applied between region 10.11. to bias the punch-through state by applying
It can also be used as a device in which the punch-through current is controlled by the electrode 14.

This case also has the same advantages as the depression type field effect transistor.

Furthermore, in order to make the depletion type field effect transistor shown in FIG. 1-f an enhancement type, before the step of forming an insulating film on the side etched portion shown in FIG. A region 17 having a lower surface concentration than the region 10 and having a different conductivity type from the region 10 is formed by diffusion through the opening 5 into the etched portion.

Thereafter, an insulating film 13 is formed to obtain a structure as shown in FIG. 1-g.

Next, contact holes IOC and 11C are formed in the necessary parts in the same manner as in Fig. 1-f, and electrodes are formed to complete the main process (Fig. 1-h).
In many cases, the header (the base portion of the transistor container) to which the substrate 1 is attached plays this role in the device assembly process.

In the case of field effect transistors, if the semiconductor substrate is p-type and has high resistance, an inversion layer is usually formed on the surface, so if the source and drain are striped, for example, they cannot be controlled by the gate electrode. An uncontrolled current may flow between the drain and the source through the inversion layer from the edge of the stripe.

In this case, in order to suppress this, either the surface region 16 of the same conductivity type as the substrate 1 is doped in advance on the outside of the channel (Fig. 1-f), or the source region 10 or gate electrode 14 is doped in a planar manner. A planar structure surrounding the drain region 11 is adopted.

In addition, if an inversion layer on the semiconductor surface is not used, it is necessary to form a shallow region near the substrate surface at least between the source and drain or between the drain and the region 17 and having a conductivity type different from that of the substrate.

Although this region can be formed by selective diffusion, it can be formed with better reproducibility by using ion implantation or eviaxial growth.

In the case of ion implantation, an impurity having a conductivity type different from that of the substrate 1 is selectively implanted shallowly into the region of the substrate 1 spanning the source and drain, and then the process starts from the process shown in Figure 1-a described above. The device may be constructed through the steps from Fig. 1-b to Fig. 1-h.

When epitaxial growth is used, as shown in FIG. 2-a, a region 15 of the opposite conductivity type to the substrate 1 is uniformly formed on the substrate 1, a diffusion mask 9 is formed thereon, and a source
A portion of the diffusion mask 9 is selectively removed by photoetching so as to cover the drain portion.

Next, as shown in FIG. 2-b, an impurity having the same conductivity type as that of the substrate 1 is diffused deeper than the region 15 to form a region 16, and the region 15 is selectively used as a source.

Leave an area slightly larger than the drain and the area in between.

Next, the diffusion mask 9 is removed, and the entire semiconductor crystal consisting of the region 1°15.16 is regarded as a substrate in the next step in a broad sense, and the first and second mask materials 2, 3 and the etch mask 4 of the second mask 3 are deposited or formed, and then the steps of FIG. 1-a, FIG. 1-b, FIG. 1-a,
Figures 2-c and 2d corresponding to Figures 1-g and 1-h.
The main part of the device is completed through the steps shown in Figures 2-e, 2-f, and 2-g.

In this case, the leakage current (uncontrolled current) between the drain and source is eliminated by the region 16, but in order to omit the step of selectively diffusing the region 16, it is also possible to adopt a configuration in which the drain region 11 is surrounded by the source region 10. .

Figure 3 shows yet another example of the conventional manufacturing process.
It includes a process in which the drain is self-aligned, such as a silicon gate process.

As shown in Figure 3-a, a substrate 1 is photo-etched, with a thin insulating film 2 formed on the surface corresponding to the source, drain, and channel forming regions and a thick insulating film 2-1 formed on the other parts. technology and insulating film formation techniques such as vapor phase growth or oxidation.

The thin insulating film 2 is made of a material that also functions as a diffusion mask.

Next, a polycrystalline Si film 3 is further formed on the insulating film on the substrate as a second mask material (etch mask for the insulating film 2) using a vapor growth technique.

Next, as shown in FIG. 3-b, the polycrystalline Si film is left only in the portion facing the channel forming region by photoetching, and the polycrystalline Si film 3 with the thin insulating film 2 left thereon is then dissolved away using as a mask.

At this time, the surface of the thick insulating film 2-1 is slightly etched.

Impurities of the first conductivity type are selectively diffused through the openings 5 and 6 thus obtained to form regions 18 and 19.

Note that 18I and 19I are used in areas 1B and 1 during selective diffusion.
This is an insulating film formed on 9.

A third mask material 7 is then adhered to the surface, and portions 8 including the openings to be side-etched are dissolved away using conventional photolithography techniques (7 may be photoresist).

Using the polycrystalline Si film and the third mask material 7 as a mask, the side surface of the opening 6 near the opening 5 (part of the insulating film 2) is removed by side etching to a required length (Fig. 3-C). )
.

Next, the mask material 7 and, if necessary, the oxide films 18I and 19I are removed, and the drain 11 is formed by diffusion of the second conductivity type impurity.
, the region of the source 10 is formed through the openings 6 and 5.

At this time, the surface of the source side portion 19-1 of the region 19 is completely covered with the second conductivity type impurity region 11,
Region 19 does not impede conduction through the channel of the semiconductor surface between the drain and source.

On the other hand, if the impurity of the second conductivity type is diffused deeply, the source region will be diffused from the same diffusion hole as the region 18, so the surface of the region 18 will have a region between the source and drain.
Only the difference Lc between the diffusion length of 8 and the diffusion length of the source region remains, which is submicron.

Therefore, by using the remaining polycrystalline Si film 3 as a gate, it is possible to form a high frequency device in which the channel length is effectively the difference in diffusion distance.

In addition to the above explanation, Fig. 3-d shows that after forming the drain/source region, an insulating film 13 is formed on the surface of the opening and the surface of the polycrystalline Si film.
A cross-sectional view of what was generated is shown.

After that, contact holes 10C, 211C, 3 are formed on the insulating film 13 on the source, drain, and polycrystalline Si (gate) films.
C and form each electrode to complete the main part (3rd-
Figure e).

The device also operates if the substrate 1 is of the first or second conductivity type.

Specific examples of semiconductor device manufacturing processes have been explained above, but as mentioned earlier, during these manufacturing processes, for example, the steps shown in Figures 1-c and d, Figure 2-e, and Figure 3-c are shown. As shown in FIG. 2, it can be seen that there are cases where it is desired to perform side etching on only a portion of the side wall of an opening formed in a layer, rather than all of it.

This is because it will lead to smaller element dimensions.

However, with the conventional photoetching technique, even if such a request is made, there are cases in which it is not possible to form the mask 7 for selective side etching into a desired pattern.

For example, if multiple holes are very close to each other and the alignment accuracy is below the limit of existing photoetch technology, it is extremely difficult or impossible to remove the required amount of the bottom surface of the holes in the mask 7. It was.

Of course, even if this is not the case, it is extremely difficult to achieve a precision in the distance between the end face of the mask 7 and the surface to be side-etched, and it has certainly not been possible to exceed the precision achieved by ordinary photoetching techniques.

The present invention has been made in consideration of this point, and aims to provide a forming method that can be applied with good reproducibility even in the case of microstructures that require precision exceeding that of ordinary photoetching. be.

Embodiments of the present invention will be described below with reference to FIG.

As with the conventional manufacturing side described above, taking the case of manufacturing a field effect transistor as an example, first, a first layer is formed on the substrate 1, which is to undergo selective side etching by applying the present invention. After forming the first mask material layer 2,
Openings are formed using a normal photoetching technique, and source and drain regions 10 and 11 are formed by diffusion of impurities through the openings.

An oxide film 1 is formed on the source region 10 and the drain region 11.
0I, 111 may also be formed.

Next, although FIG. 4-a shows a state in which the openings 8 have already been made, the first layer is coated over the entire surface including the first layer on the substrate, the diffusion mask 2, and the bottom surface of the openings. A mask layer 7 is formed as a second layer made of a photosensitive material that is resistant to the etching method described above.

Therefore, when opening the opening 8, avoid exposure from the direction perpendicular to the main surface as in normal photoetching techniques, and expose the mask from a direction that is at an angle to the perpendicular direction, which is inclined toward the side wall of the opening where side etching is desired. When layer 7 is exposed, the shadowed portion of the side wall of the opening will not be exposed.

Therefore, according to the development process after such processing,
The unexposed portions are dissolved in the developing solution, and the desired openings 8 are obtained in the mask 7, as shown in Figure 4-b.

The size of this opening 8 or the distance between the exposed side wall of the mask 2 and the facing end surface of the mask 7 is determined with a fairly high degree of accuracy, unlike in ordinary photoetching techniques, which are limited by alignment accuracy. be able to.

In addition, since the diagonal line in Figure 4-8 is the direction of light irradiation, as you will soon see, the above distance is a function of the degree of inclination in the diagonal direction, that is, the angle of inclination of the direction of light irradiation, and the design is excellent. It is obvious from this figure that

If the required opening 8 can be formed in this way, the portion of the mask 2 to be side-etched is side-etched as expected by the normal process explained in conjunction with FIG. 1, and the substrate surface is exposed. Insulating film 13, contact holes 10C, 11C.

By forming the electrodes 10E, 11E, and 12, an element is completed, as shown in Figure 4C, which has the original features of the element shown in Figures 1-F, but with much higher dimensional accuracy and reproducibility.

As described above, according to the present invention, FIG. 1-e is taken as an example, but as described above, as shown in FIG. 2-e and FIG. In applications where it is desired to side-etch only a part of the side wall of the hole, if the structure is so small that the mask alignment accuracy is constrained, it is natural that the mask or second layer 7 will not be etched as expected due to the constraint. In contrast to the actual situation in which it was not possible to form the required openings 8 and therefore the subsequent formation of area matching means was not possible, this defect is completely overcome.

Because it can be done, its effectiveness is quite impressive.

In addition, in the examples, regions formed in the substrate, such as source and drain regions, are mentioned as foreign regions formed in the substrate, but the point is that the regions formed in the substrate are matched with such regions. The gist of the present invention lies in overcoming the fact that conventionally, when using side etching as a means of forming the desired area, this cannot be done if the size is too small, and the structure represented by oblique exposure for this purpose. Therefore, as long as the region concerned is related to the substrate and is formed relative to the first layer opening, even if it is on the substrate,
Even in the removed area where the substrate at the bottom of the hole is removed appropriately, there is no problem in the negative direction.

In either case, the present invention can be applied to such a configuration since it can be combined with a heterogeneous region provided on the substrate.

In other words, it is sufficient to go through the steps of applying the second layer 7 over the entire surface, obliquely exposing it to light, and developing and removing the light-shielded portion.

For example, the above-mentioned region, that is, the heterogeneous region provided in the substrate through the opening, may be a vapor deposited layer for forming a Schottky junction, a silicide layer made of an alloy, a low resistance region layer, or the like.

Further, the matching region obtained by the means for forming a region matching the above-mentioned heterogeneous region obtained as a result of application of the present invention also has an arbitrary closed head depending on the element, and may be a plated layer or the like.

As a result, if the method of the present invention is applied to a field effect transistor as in the illustrated embodiment, even if the dimensions are so small that the desired selective side etching process cannot be performed, it will be possible to perform the desired selective side etching process. In addition to its original features, it is possible to achieve further miniaturization and, therefore, to improve performance such as high frequency performance.

In other cases, a through hole is formed in the first layer formed on the substrate,
We would like to use selective side etching of the hole as a means of forming an area that should be aligned with the heterogeneous area provided on the substrate in the hole, but conventional photoetching techniques are not accurate. The present invention can be applied to all kinds of applications that would otherwise be impossible, and is truly useful in such fields.

[Brief explanation of drawings]

FIGS. 1 to 3 are explanatory diagrams of examples of conventional microstructure manufacturing processes, and FIG. 4 is explanatory diagrams of manufacturing processes of an embodiment of the present invention. In the figure, 1 is a substrate, 2 is a first layer, 5 is an opening, and 7 is a second layer made of side etching mask material.

Claims (1)

[Claims] 1. After forming a first layer of a first mask material on a substrate, forming an opening penetrating through the first layer, and forming a region different from the substrate in the substrate in the opening portion, applying a second layer of photosensitive material resistant to the etching means of the first layer;
After exposing the substrate to light from an oblique direction, the second layer of the light-shielding portion on the side surface of the opening is removed by development, and a part of the first layer is selectively side-etched and removed from the exposed side surface, A method for forming a microstructure, characterized in that the removed portion is used as a means for forming a region that matches the foreign region.