JPS6320374B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to manufacturing a semiconductor device using a processing technique that opens a diffusion window of any size at any location on a side surface (wall surface) cut in a direction perpendicular to the semiconductor surface. It is about the method.

Recently, the development of semiconductor devices has been remarkable, especially electrostatic induction type semiconductor devices. Taking advantage of their basically excellent characteristics, new structures are being developed based on new concepts one after another with the goal of achieving higher speeds and lower power consumption. Transistors, thyristors, ICs, memories, etc. have been proposed. For example, as an example of a static induction transistor (hereinafter referred to as SIT), an example of a surface gate type structure is shown in FIGS. 1 and 2. Figure 1 shows a planar gate type SIT in which the gate and source are placed on the same plane.
This is an example of the structure, and the cross section of four channels of n ⁺ channel SIT is illustrated. n ⁺ region 1 is the drain, n ^- region 2 is the channel and channel-drain region, p ⁺ region 3 is the gate, n ⁺ region 4 is the source, surface protection region 5 is an insulator such as an oxide film, and metal electrode 6 is A gate electrode, 7 a source electrode, and 8 a drain electrode. Although this structure is easy to manufacture, it has the disadvantage that the gate is relatively large and close to the source, resulting in large source-gate capacitance and drain-gate capacitance. On the other hand, in order to reduce the source-gate capacitance and drain-gate capacitance, a structure has been proposed in which the gate is formed small at a position cut below the semiconductor surface, as shown in Figure 2. . Regions 1 to 8 represent the same regions as in FIG. 1, and region 9 is an insulator or a void. This structure can reduce each parasitic capacitance and is suitable for high frequency and high speed operation.

However, while the three-dimensional structure shown in FIG. 1 can be manufactured using conventional planar semiconductor device manufacturing technology that requires only planar processing, the structure shown in FIG. 2 is difficult to manufacture using conventional planar processing technology. In particular, machining the side walls perpendicular to the main surface is incompatible with conventional flat surface machining techniques.

In a three-dimensional semiconductor device that has a cut from the semiconductor surface, it is almost impossible to process a diffusion window, contact window, etc. on the side surface (wall surface) of the cut using conventional photolithography technology.
When manufacturing a SIT with the structure shown in the figure, plasma etching, Si 3 N ₄ CVD, and Si ₃ N 4 CVD are used to form the gate diffusion window.
A method is used in which processes such as film formation and selective oxidation are combined. This method requires almost no photolithography technology, but it involves a large number of steps.
It had many problematic drawbacks.

The present invention provides a method for forming a diffusion window and a contact window on the side surface (wall surface) of a notch in a semiconductor device having a notch as described above by directly applying the conventional planar processing technology and by photolithography technology. This is what we provide.
In particular, even when the side wall of the cut recess is substantially perpendicular to the main surface, processing can be performed on the side wall with high precision.

This will be explained below with reference to the drawings. In this embodiment, an example of the manufacturing process of n-channel SIT will be sequentially explained.

(1) As shown in Figure 3a, n ⁺ substrate (impurity density approximately
10 ¹⁸ /cm ³ ) 1 by epitaxial growth etc. to form an n ^- region (impurity density approximately 1×10 ¹³ /cm ³ ) 2.
It grows about 10μ. Next, an oxide film 5 of about 5000 Å is formed by conventional thermal oxidation, and a photoresist 9 is selectively formed in areas other than the cut portions by conventional photolithography.

(2) As shown in Figure 3b, the n region 2 is etched by about 10 μm until it reaches the n ^- substrate by directional plasma etching, etc.
The photoresist 9 is removed, and an oxide film 5 of about 5000 Å is formed by ordinary thermal oxidation, and the oxide film is also formed on the side surfaces (wall surfaces) and the bottom surface of the cut portion.

(3) As shown in FIG. 3c, a positive type photoresist 9 (for example, AZ-1350) is applied, and a mask glass plate 10 is closely placed to align the mask and the cut portion. This positioning exposure method was developed by the inventor of the present invention in February 1980.
“Mask positioning exposure device” filed on the 15th
It is best to do this by using The mask has a glass substrate 10, a mask material 11 such as Cr, and a mask opening 12, and is aligned with the cut portion as shown in the figure. The photoresist 9 is exposed by irradiating the exposure light 13 from an oblique direction (angle Θ). Note that the refraction of light in the glass plate is not illustrated. Further, although only the right side surface is shown in this figure, exposure to the cut side surface (wall surface) is also performed on the left side surface (wall surface). Although the configuration is shown in which the opening of the mask is offset from the center of the notch, it can also be arranged symmetrically, or both the left and right sides can be exposed at the same time.

(4) As shown in Fig. 3d, after developing the photoresist 9, the oxide film 5 is etched by plasma etching, etc., a window is opened, and the oxide film 5 is etched by normal diffusion, etc.
A gate of p ⁺ region (surface density approximately 10 ¹⁹ /cm ³ ) 3 is formed. Since the position of the window can be arbitrarily selected depending on the mask and the exposure angle Θ, it can be formed at a desired depth. For example, the depth should be about 1 μm from the above surface.

(5) As shown in Figure 3e, the oxide film 5 on the upper surface is removed using normal photolithography technology, and an n ⁺ region (surface density of approximately 10 ²¹ /cm ³ ) is formed by normal diffusion, etc.
4 sources are formed to a depth of 0.5μ. Subsequently, contact holes are formed in the p ⁺ region 3 and the n ⁺ region 4 using the usual emitter washing method or the above-mentioned photolithography technique.

(6) As shown in Fig. 3f, polyimide or photoresist is applied to the entire surface as the insulating material 9, and
Unnecessary parts are removed from the bottom of the incision by plasma etching, leaving a gate opening, and metal electrodes 6 and 7 are formed by vapor deposition, plating, and conventional photolithography techniques. Alternatively, if the metal electrode 6 is formed by plating from both gates without forming the insulator 9, the area below can be made into a void. Further, a metal electrode 8 is similarly formed on the n ⁺ substrate 1.

The above method has the advantage that the SIT, in which the gate is formed at a position cut from the semiconductor surface, can be manufactured in the same process as a conventional planar gate type SIT, and the number of process steps can be reduced.

In this embodiment, an n-channel SIT was explained, but it is obvious that the same can be done for a p-channel, and it can also be applied to thyristors, SITL, memories, etc. The present invention is effective in manufacturing not only electrostatic induction type semiconductor devices but also semiconductor devices having a recess cut inward from the main surface and having an impurity doped region on the sidewall of the recess.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the planar gate type SIT, Figure 2 is a cross-sectional view of the notched gate type SIT, and Figures 3 a to f.
FIG. 2 is a cross-sectional view showing the manufacturing process of the cut gate type SIT according to the present invention. 1... n ⁺ substrate, 2... channel in n ^- region or channel-drain region, 3... gate in p ⁺ region, 4... source in n ⁺ region, 5... insulator such as oxide film, 6... Gate metal electrode, 7...
Source metal electrode, 8... Drain metal electrode, 9...
...Insulator or void.

Claims (1)

[Scope of Claims] 1. Forming a recess inward from the main surface with a width d and a depth h in a semiconductor chip having a main surface; and forming a photoresist film on at least the surface of the recess. arranging on the main surface a mask having a predetermined pattern having a portion where the dimension W of at least one side satisfies W<d, and the angle between the mask and the normal to the main surface forming >arctan (W/h); selectively exposing only the photoresist film on the side wall of the concave portion from the direction through the mask to form a window corresponding only to the size determined by the predetermined pattern size and the angle and the shape of the predetermined pattern. A method for manufacturing a semiconductor device, comprising: a step of adding an impurity through the window.