JPS5635421A - Manufacture of minute structure - Google Patents

Manufacture of minute structure

Info

Publication number
JPS5635421A
JPS5635421A JP8427780A JP8427780A JPS5635421A JP S5635421 A JPS5635421 A JP S5635421A JP 8427780 A JP8427780 A JP 8427780A JP 8427780 A JP8427780 A JP 8427780A JP S5635421 A JPS5635421 A JP S5635421A
Authority
JP
Japan
Prior art keywords
film
diffusion
regions
substrate
electroconductive type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8427780A
Other languages
Japanese (ja)
Other versions
JPS5834934B2 (en
Inventor
Yutaka Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP55084277A priority Critical patent/JPS5834934B2/en
Publication of JPS5635421A publication Critical patent/JPS5635421A/en
Publication of JPS5834934B2 publication Critical patent/JPS5834934B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To manufacture a device of good high-frequency properties, by coating an SiO2 film and an Si3N4 film on a semiconductor substrate of one electroconductive type, making openings in these films to produce regions of another electroconductive type in the substrate by diffusion, etching the side faces of the remaining film and producing another region of the former electroconductive type at an etched portion of the film by diffusion so that the latter region is in contact with one of the former regions. CONSTITUTION:A thick SiO2 film 2 is coated on a semiconductor substrate 1 of one electroconductive type and then covered with a thin Si3N4 film 3 and a thin SiO2 film 4. Openings 5, 6 are provided in the films to correspond to diffused regions. The regions 10, 11 of another electroconductive type are produced by diffusion in the portions of the substrate 1 exposed in the openings 5, 6. Thin SiO2 films 101, 111 produced on the regions 10, 11 due to the diffusion are etched off. At the same time, the side faces of the film 2 are etched. Another region 17 of the former electroconductive type is produced by diffusion in the substrate 1 at an etched side face 12 so that a shallow region 17 being diffusion formed is in contact with the former region 10. Other openings 10c, 11c are provided in an SiO2 film 13 being produced as a result of said process, while electrodes 10E, 11C are fitted thereon respectively. Another electrode 1E is coated on the reverse side of the substrate 1.
JP55084277A 1980-06-21 1980-06-21 How to form microstructures Expired JPS5834934B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55084277A JPS5834934B2 (en) 1980-06-21 1980-06-21 How to form microstructures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55084277A JPS5834934B2 (en) 1980-06-21 1980-06-21 How to form microstructures

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP49029614A Division JPS50123273A (en) 1974-03-16 1974-03-16

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4004182A Division JPS57202737A (en) 1982-03-13 1982-03-13 Formation of minute structure

Publications (2)

Publication Number Publication Date
JPS5635421A true JPS5635421A (en) 1981-04-08
JPS5834934B2 JPS5834934B2 (en) 1983-07-29

Family

ID=13825952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55084277A Expired JPS5834934B2 (en) 1980-06-21 1980-06-21 How to form microstructures

Country Status (1)

Country Link
JP (1) JPS5834934B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57159028A (en) * 1981-03-25 1982-10-01 Fujitsu Ltd Manufacture of semiconductor device
US5023203A (en) * 1988-07-28 1991-06-11 Korea Electronics & Telecommunications Research Institute Et Al. Method of patterning fine line width semiconductor topology using a spacer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61122354A (en) * 1984-11-16 1986-06-10 松下電器産業株式会社 Body panel of building

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50123273A (en) * 1974-03-16 1975-09-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50123273A (en) * 1974-03-16 1975-09-27

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57159028A (en) * 1981-03-25 1982-10-01 Fujitsu Ltd Manufacture of semiconductor device
JPH0119259B2 (en) * 1981-03-25 1989-04-11 Fujitsu Ltd
US5023203A (en) * 1988-07-28 1991-06-11 Korea Electronics & Telecommunications Research Institute Et Al. Method of patterning fine line width semiconductor topology using a spacer

Also Published As

Publication number Publication date
JPS5834934B2 (en) 1983-07-29

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