JPH04192472A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To obtain a thin-film transistor whose electric mobility made large and whose responsiveness can be made good by a method wherein the film thickness of a channel formed so as to correspond to a gate-electrode formation part in a semiconductor layer is made thinner than the film thickness of a source region and a drain region. CONSTITUTION:The filling degree of local oxide layers 26, 27 with reference to a polysilicon layer 22 is made thin in such a way that the film thickness of the polysilicon layer 22 at individual lower parts of the local oxide films 26, 27 is at about several tens of Angstrom to 1000Angstrom . Then, a silicon nitride layer 33 and the local oxide layers 26, 27 are etched and removed wholly. In this state, regions corresponding to individual gate-electrode formation parts for a P-MOSFET and an N-MOSFET, i.e., channel regions 28, 29, are recessed in the polysilicon layer 22; the film thickness of the recessed regions is made thinner than the film thickness in parts on both sides. Thereby, the electric mobility of the channel regions 28, 29 can be made large, and it is possible to obtain a thin-film transistor whose electric mobility is large and whose responsiveness is good.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to a method for manufacturing a thin film transistor.

[Prior art] As a thin film transistor, for example, a field effect (FET)
CMOS transistors of the type are known. Such conventional thin film transistors are manufactured as shown in FIGS. 3(A) to 3(C).

That is, as shown in FIG. 3(A), first, two polysilicon layers 2.3 are patterned on a substrate 1 made of ceramic or the like, and these polysilicon layers 2.3 are covered with a gate insulating film 4.5. A gate electrode 6.7 is provided on each gate insulating film 4.5 in a portion corresponding to the central portion of the polysilicon layer 2.3.

Next, only the right side of the polysilicon layer 3 is covered with a resist 8, and in this state, B (boron) ions are implanted as an acceptor impurity into the left side of the polysilicon layer 2 to form the polysilicon layer 2 on both sides of the gate electrode 6. Impurity regions 9 for source and drain are formed. This will cause the PM on the left side to
An O3FET is formed.

Next, as shown in Figure 3 (B), the PM03FE on the left
Only T is covered with a resist 10, and in this state, P (phosphorus) ions are implanted as donor impurities into the right side of the polysilicon layer 3 to form source/drain impurity regions 11 in the polysilicon layer 3 on both sides of the gate electrode 7. do. As a result, an NMO3FET is formed on the right side.8 Next, as shown in FIG.
After forming the insulating film 12, contact holes 13.14 are formed in portions corresponding to each impurity region 9.11 by etching, and each contact hole 13.12 is formed.
14 through each source/drain impurity region 9.11
A metal wiring 15 connected to the metal wiring 15 is patterned. Thus, a CMO3FET is formed.

[Problems to be Solved by the Invention] However, in such conventional thin film transistors, in both PMO3FET and NMO3FET, the polysilicon layer 2.3 has a uniform thickness of 1000 to 1000 nm.
Since the metal is formed as thick as about 3000, the electric mobility between the source and drain impurity regions 9.31 is small.
There was a problem with poor responsiveness.

Note that if the polysilicon layer 2.3 is formed to have a thin film thickness of 1000 Å or less, the electrical mobility between the impurity regions 9.11 will increase, but the sheet resistance of the impurity regions 9.11 and the metal wiring 15 will increase. The contact resistance between the transistor and the transistor becomes high, and in this case also, a problem arises in that the operating speed of the transistor becomes slow.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a method for manufacturing a thin film transistor that can increase electrical mobility and improve responsiveness.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides at least a local oxidation layer in a portion corresponding to a gate electrode formation portion of a polysilicon layer formed to a substantially constant thickness. By etching this local oxidation layer, the thickness of the channel region formed in the semiconductor layer corresponding to the gate electrode formation portion is changed to that of the source region and drain region. It is made to be thinner than the film thickness.

[Function] According to the present invention, even if the semiconductor layer is initially formed to have a substantially constant thickness, a local portion of the semiconductor layer corresponding to the gate electrode forming portion is provided so as to be at least partially buried in the semiconductor layer. By etching the oxide layer, the thickness of the region of the semiconductor layer corresponding to the gate electrode formation portion can be made thinner than the thickness of the impurity regions on both sides thereof. Therefore, the film thickness of the channel region is formed thinner than that of the source and drain regions, the electrical mobility in the channel region increases, and the sheet resistance and contact resistance of the source and drain regions can be kept small. Therefore, a thin film transistor with high electrical mobility and good responsiveness can be obtained.

[Example code] Hereinafter, the present invention will be described in detail with reference to Examples.

FIGS. 1A to 1I each show the manufacturing steps of a thin film transistor according to an embodiment of the present invention. Therefore, a method for manufacturing a thin film transistor will be described with reference to these figures in order.

First, as shown in FIG. 1(A), a polysilicon layer (semiconductor layer) 22 is deposited to a substantially constant thickness on a substrate 21 made of ceramic, glass, quartz, etc. by plasma CVD.
On this polysilicon layer 22, a silicon nitride layer 23 for a local oxidation mask is formed.

Next, although not shown, using well-known photolithography techniques such as photoresist coating, masking, exposure, and development, the silicon nitride layer 23 is formed at the portions corresponding to the locations where the gate electrodes of the PMO3FET and NMO3FET are to be formed. and open it as shown in Figure (B).
Form 24.25.

Next, the portions of polysilicon layer 22 exposed through openings 24 and 25 are oxidized by heat treatment.

In this case, the oxidation of the polysilicon layer 22 progresses at approximately the same rate on the outside and inside of the polysilicon layer 22, so the first! As shown in ff1 (C), polysilicon layer 2
A portion of the corresponding openings 24 and 25 of No. 2 is covered with polysilicon layer 2.
Local oxidation layers 26 and 27 embedded in 2 are formed. At this time, the polysilicon layer 22 other than the portions where the local oxidation layers 26 and 27 are formed is covered with the silicon nitride layer 23 and is therefore not oxidized. The degree of burying of the local oxide layers 26 and 27 in the polysilicon layer 22 is as follows.
6. The thickness of the polysilicon layer 22 under each of the layers 27 is made to be approximately several tens to 1,000 metal layers.

Next, as shown in FIG. 1(D), the silicon nitride layer 23
and the local oxide layers 26, 27 are all etched away. In this case, the polysilicon layer 22 below each local oxide layer 26, 27 to be removed by etching.
Since the film thickness has been adjusted in the previous step to be as thin as several O to +oooA, it is desirable that this etching step be completed with just the right amount of etching. In the state shown in FIG. 1(D), the polysilicon layer 22 is connected to the PMO5FET and NMOSFET.
The regions corresponding to the pole forming portions of each gate, that is, the channel regions 28 and 29, are recessed, and the film thickness of this recessed region is thinner than the film thickness of the portions on both sides thereof.

Next, as shown in FIG. 1E, the polysilicon layer 22 is separated into a polysilicon layer 22a forming a PMO5FET and a polysilicon layer 22b forming an NMOSFET by isolation. Insulators [31 and 32 made of silicon oxide films or the like are formed on the surfaces of the silicon layers 22a and 22b.

Next, as shown in the first @ (F), each polysilicon layer 2
Gate ridges 33.34 are formed on portions of the insulating film 31.32 corresponding to the channel regions 28.29 of 2a and 22b. The gate @ horizontal 33.34 is formed from polysilicon or metal material doped with ion impurities, and the portion of the insulating film 3 corresponding to the gate electrode 33.34
1.32 becomes the gate insulating film.

Next, as shown in FIG. 1(G), only the right side of the polysilicon layer 22b is covered with a resist 35, and in this state, B is added to the left side of the polysilicon layer 22a as an acceptor impurity.
(Boron) ions are implanted to form a source region and a drain region 36 in the polysilicon layer 22a on both sides of the gate electrode 33. In this case, the film thickness of the polysilicon layer 22a on both sides of the gate electrode 33 is 1000-3.
Since the thickness is approximately 1,000 mm, the metal contact resistance and contact resistance can be suppressed to small values, and the response speed of the transistor can be increased. Thus, on the left side P
A MO3FET is formed. After that, the resist 35 is removed.

Next, as shown in Figure 1 (H), the PMO3FE on the left
Only T is covered with a resist 37, and in this state, P (phosphorus) ions are implanted as a donor impurity into the right polysilicon layer 22a to form a source region and a drain region 38 in the polysilicon layer 22a on both sides of the gate electrode 34. . In this case as well, the thickness of the polysilicon layer 22b on both sides of the gate electrode 34 is as thick as about 1,000 to 3,000 layers, so that the metal contact resistance and the contact resistance can be reduced. Thus, NMOS F E on the right side
A T is formed. After this, the resist 37 is removed.

Next, as shown in FIG. 1(I), an insulating film 41 is formed on the entire surface.
After forming this insulating film 41, contact holes 4 are formed in portions corresponding to each impurity region 36 and 38.
2.43 are provided respectively, and each contact hole 42.4 is provided.
3 through each source/drain impurity region 36.38
Metal wirings 44 and 45 connected to are patterned.

In this way, a thin belly transistor made of CMO3FET is formed.

In the thin film transistor manufactured in this way, the thickness of the channel region formed corresponding to each gate electrode forming portion of the polysilicon layers 22a and 22b is several 10 to 100 nm thick.
Since the metal is thinner than the film thickness of the source region and drain region 36.38 of about 1,000 to 3,000 nanometers, the electrical mobility of the channel region can be increased and the responsiveness can also be improved. I can do it.

In the above embodiment, first, as shown in FIG. 1'(A), a silicon nitride layer 23 for a local oxidation mask is directly formed on the polysilicon layer 22, and then, as shown in FIG. and 25, the silicon nitride layer 2
Openings 24 and 25 are formed in the portions corresponding to the gate electrode forming portions in No. 3.
Then, as shown in FIG. 1(C), an oxidation step is performed to form local oxide layers 26 and 27 partially buried in the polysilicon layer 22 in the portion corresponding to the gate electrode formation portion. Then, as shown in FIG. 1D, by etching and removing all of the silicon nitride layer 23 and local oxide layers 26, 27, the channel regions 28, 29 of the polysilicon layer 22 are recessed. Although the film thickness of the portion is made thinner, it is not limited to this.

For example, as shown in FIG. 2(A), a polysilicon layer 2
A silicon oxide film 51 is formed on the silicon oxide film 51, a silicon nitride layer 23 is formed on the silicon oxide film 51, and an opening 02 is formed in a portion of the silicon nitride layer 23 corresponding to the gate electrode formation portion.
4.25, and then, as shown in FIG. 2(B), an oxidation process is performed to form a local oxidation layer 26. 27 and then silicon nitride layer 2
By etching and removing all of the polysilicon layer 3 and the local oxide layers 26 and 27, the thickness of the channel region 28 and 29 of the polysilicon layer 22 may be reduced, as shown in FIG. 1(D). .

In this case, the etching selectivity between the silicon nitride layer 23 and the silicon oxide film 51 and the etching selectivity between the silicon oxide film 51 and the polysilicon layer 22 are higher than the etching selectivity between the silicon nitride layer 23 and the polysilicon layer 22. Since both etching selectivity ratios are better, there is less film loss due to etching of the polysilicon layer 22, and therefore the thickness of the polysilicon layer 22 in the gate electrode forming area can be easily controlled.

Further, in the above embodiment, the present invention is applied to a coplanar type thin film transistor, but the present invention is not limited to this, and can of course be applied to an inverted staggered type, a staggered type, an inverted staggered type, etc. It is.

[Effects of the Invention] As explained above, according to the present invention, even if the semiconductor layer is initially formed to have a substantially constant thickness, at least a portion of the semiconductor layer corresponds to the gate electrode formation portion. By etching the local oxide layer buried in the semiconductor layer, the channel region of the semiconductor layer can be made thinner than the source and drain regions, increasing the electrical mobility of the channel region. And sauce
The sheet resistance and contact resistance of the drain region can be kept low, and therefore a thin film transistor with high electrical mobility and good responsiveness can be obtained as a whole.

[Brief explanation of the drawing]

FIGS. 1(A) to (1) are cross-sectional views showing each manufacturing process of a thin film transistor according to one embodiment of the present invention, and FIGS. 2(A) and (B) are respectively sectional views of thin film transistors according to another embodiment of the present invention. FIGS. 3A to 3C are cross-sectional views showing each manufacturing process of a conventional thin film transistor. 2111111. Substrate, 22.22a, 22b =-
Polysilicon layer, 23...Silicon nitride layer, 2
6.27...Local oxidation layer, 31.32...
・Insulating film, 33.34...Gate electrode, 36.3
8... Source train area. 21 suction

Claims (1)

[Claims] A local oxidation layer is provided in a portion of the semiconductor layer formed to have a substantially constant thickness corresponding to the gate electrode formation portion so that at least a portion thereof is buried in the semiconductor layer, and this local oxidation layer is etched. 1. A method of manufacturing a thin film transistor, characterized in that the thickness of a channel region formed corresponding to a gate electrode forming portion of a layer is thinner than that of a source region and a drain region.