JPH03289137A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH03289137A JPH03289137A JP9071590A JP9071590A JPH03289137A JP H03289137 A JPH03289137 A JP H03289137A JP 9071590 A JP9071590 A JP 9071590A JP 9071590 A JP9071590 A JP 9071590A JP H03289137 A JPH03289137 A JP H03289137A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- source
- insulating film
- drain
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract 2
- 238000000034 method Methods 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 230000004913 activation Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 22
- 239000010410 layer Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 241000244317 Tillandsia usneoides Species 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野コ 本発明は、薄膜トランジスタに関する。[Detailed description of the invention] [Industrial application fields] The present invention relates to thin film transistors.
［従来の技術］
従来の絶縁性基板上に薄膜トランジスタを形成する際の
、−殻内な製造方法の例を第３図に示す。[Prior Art] FIG. 3 shows an example of a conventional in-shell manufacturing method for forming a thin film transistor on an insulating substrate.
まず、透明絶縁性基板３０１上に、ソース・ドレイン領
域として高濃度不純物を添加した半導体薄膜層３０２を
形成し、バターニングした後、能動領域として不純物を
含まない真性半導体層３０３を積層・バターニングし、
その後ゲート絶縁膜３０４とゲート電極３０５、層間絶
縁膜３０６を積層し、コンタクトホール３０７を開口し
た後、ソース電極端子３０８、ドレイン電極端子３０９
を形成して薄膜トランジスタが完成する。First, a semiconductor thin film layer 302 doped with high concentration impurities is formed as a source/drain region on a transparent insulating substrate 301, and after patterning, an intrinsic semiconductor layer 303 containing no impurities is laminated and patterned as an active region. death,
After that, a gate insulating film 304, a gate electrode 305, and an interlayer insulating film 306 are laminated, and after opening a contact hole 307, a source electrode terminal 308 and a drain electrode terminal 309 are formed.
is formed to complete the thin film transistor.
［発明が解決しようとする課題］
しかし、前述の従来の技術では、ソース・ドレイン領域
となる高濃度不純物を添加した半導体薄膜層と能動領域
となる真性半導体を別途に形成しなければならない。又
前述の従来の技術では、薄膜トランジスタのチャネル長
はソース・トレイン領域の距離により決定される。現状
では、大型基板対応のアライナ−の最小加工寸法は、３
〜４μｍが限度であり、短チャネルの薄膜トランジスタ
の製作は非常に困難である。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, it is necessary to separately form a semiconductor thin film layer doped with high concentration impurities to serve as the source/drain region and an intrinsic semiconductor to serve as the active region. Furthermore, in the conventional technology described above, the channel length of a thin film transistor is determined by the distance between the source and train regions. Currently, the minimum processing size of aligners for large substrates is 3.
The maximum thickness is ~4 μm, making it extremely difficult to manufacture short-channel thin film transistors.
本発明は、この様な従来の薄膜トランジスタの問題点を
解決するもので、その目的とするところは、ソース・ド
レイン領域の形成を容易する薄膜トランジスタ及び、短
チヤネル薄膜トランジスタを提供するところにある。The present invention solves the problems of conventional thin film transistors, and its purpose is to provide a thin film transistor and a short channel thin film transistor in which source/drain regions can be easily formed.
［課題を解決するための手段］
本発明の薄膜トランジスタは、
絶縁性基板上にソース・ドレイン電極として高濃度不純
物を添加した半導体層と、能動領域としての真性半導体
層とを有する薄膜トランジスタにおいて、前記絶縁性基
板表面に付与された段差部を含む領域に形成された真性
半導体層に、イオン打ち込みを行う事によりソース・ド
レイン電極を形成したことを特徴とする薄膜トランジス
タ。[Means for Solving the Problems] A thin film transistor of the present invention includes a semiconductor layer doped with high concentration impurities as source/drain electrodes on an insulating substrate, and an intrinsic semiconductor layer as an active region. 1. A thin film transistor characterized in that source and drain electrodes are formed by ion implantation into an intrinsic semiconductor layer formed in a region including a stepped portion provided on a surface of a transparent substrate.
［実施例コ
第１図は、本発明の第１の実施例を、工程順に示す図で
ある。まず第１図（ａ）に示すように、絶縁性基板１０
１の表面に、ホトリソグラフィー技術を用いて、所望の
段差を付与する。次に不純物を含まない真性半導体層１
０３を、シランの熱分解などによって１００ＯＡ程度の
厚さに積層し、バターニングする。この状態が第１図（
ｂ）である、シランは３００℃以上で分解するが、理想
的には６００℃前後が望ましい、ついで、全面にゲート
絶縁膜となる絶縁薄膜１０４を、約１５００Ａ程度の厚
さに積層し、第１図（ｃ）とする。前記絶縁薄膜には、
二酸化珪素膜や窒化珪素膜などが、常圧ＣＶＤ法、減圧
ＣＶＤ法、プラズマＣＶＤ法、ＥＣＲプラズ７ＣＶＤ法
、光ＣＶＤ法、またはこれらの組合せにより、形成され
、使用される。[Example 1] Fig. 1 is a diagram showing a first example of the present invention in order of steps. First, as shown in FIG. 1(a), an insulating substrate 10
A desired level difference is provided on the surface of 1 using photolithography technology. Next, an intrinsic semiconductor layer 1 containing no impurities
03 is laminated to a thickness of about 100 OA by thermal decomposition of silane, etc., and buttered. This state is shown in Figure 1 (
In b), silane decomposes at temperatures above 300°C, but ideally around 600°C. Next, an insulating thin film 104 that will become a gate insulating film is laminated to a thickness of about 1500 A over the entire surface, and the 1 (c). The insulating thin film includes:
A silicon dioxide film, a silicon nitride film, or the like is formed and used by a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, an ECR Plas 7 CVD method, a photoCVD method, or a combination thereof.
ついでソース・ドレイン形成の為の不純物をイオ・ン打
ち込み法により打ち込み、活性化の為の熱処理を施した
のちにゲート電極となる導体薄膜層をスパッタ法などに
より形成した後、ゲート電極１０５となる部分を除きエ
ツチングして、第１図（ｄ）を得る。ゲート電極には、
アルミニュウムあるいはクロム等の金属や、多結晶シリ
コン膜が使用される。次に、層間絶縁膜１０６を積層、
ついで、ソース・ドレイン電極を形成する部分の絶縁薄
膜１０４と層間絶縁膜１０６を除去し、コンタクトホー
ル１０７としその部分にソース電極１０８、 ドレイン
電極１０９を形成し、第１図（ｅ）となる。上記層間絶
縁膜１０６には、前記絶縁薄膜１０４と同じ方法で形成
された絶縁膜の他に、ボリノミド等の有機膜が使用され
ることもある。Next, impurities for forming the source and drain are implanted by ion implantation, heat treatment is performed for activation, and a conductive thin film layer that will become the gate electrode is formed by sputtering or the like, and then the gate electrode 105 is formed. The portion is removed and etched to obtain the image shown in FIG. 1(d). The gate electrode has
A metal such as aluminum or chromium or a polycrystalline silicon film is used. Next, an interlayer insulating film 106 is laminated,
Next, the insulating thin film 104 and the interlayer insulating film 106 in the portions where the source/drain electrodes are to be formed are removed, a contact hole 107 is formed, and a source electrode 108 and a drain electrode 109 are formed in the contact hole 107, as shown in FIG. 1(e). In addition to an insulating film formed by the same method as the insulating thin film 104, an organic film such as boronomide may be used for the interlayer insulating film 106.
第２図は、本発明の第２の実施例を、工程順に示す図で
ある。まず第２図（ａ）に示すように、絶縁性基板２０
１の表面に、ホトリソグラフィー技術を用いて、所望の
段差を付与する。次に不純物を含まない真性半導体層２
０３を、シランの熱分解などによって１００ＯＡ程度の
厚さに積層し、ついでソース・ドレイン形成の為の不純
物をイオン打ち込み法によりうちこみ、活性化の為の熱
処理を施したのちにバターニングする。この状態が第２
図（ｂ）である。ついで、全面にゲート絶縁膜となる絶
縁薄膜２０４を、約１５００Ａ程度の厚さに積層し、第
１図（Ｃ）とする。前記絶縁薄膜には、二酸化珪素膜や
窒化珪素膜などが、常圧ＣＶＤ法、減圧ＣＶＤ法、プラ
ズマＣＶＤ法、 ＥＣＲプラズマＣＶＤ法、光ＣＶＤ法
、またはこれらの組合せにより、形成され、使用される
。FIG. 2 is a diagram showing a second embodiment of the present invention in order of steps. First, as shown in FIG. 2(a), an insulating substrate 20
A desired level difference is provided on the surface of 1 using photolithography technology. Next, an intrinsic semiconductor layer 2 containing no impurities
03 is laminated to a thickness of about 100 OA by thermal decomposition of silane, impurities for forming sources and drains are implanted by ion implantation, heat treatment is performed for activation, and buttering is performed. This state is the second
It is figure (b). Next, an insulating thin film 204, which will become a gate insulating film, is laminated on the entire surface to a thickness of about 1500 Å, as shown in FIG. 1(C). A silicon dioxide film, a silicon nitride film, or the like is formed and used as the insulating thin film by a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, an ECR plasma CVD method, a photoCVD method, or a combination thereof. .
ついで、ゲート電極となる導体薄膜層をスパッタ法など
により形成した後、ゲート電極２０５となる部分を除き
エツチングして、第１図（ｄ）を得る。ゲート電極には
、アルミニュウムあるいはクロム等の金属や、多結晶シ
リコン膜が使用される。Next, a conductive thin film layer that will become the gate electrode is formed by sputtering or the like, and then etched except for the portion that will become the gate electrode 205, to obtain the structure shown in FIG. 1(d). A metal such as aluminum or chromium or a polycrystalline silicon film is used for the gate electrode.
次に、層間絶縁膜２０６を積層、ついで、ソースドレイ
ン電極を形成する部分の絶縁薄膜２０４と層間絶縁膜２
０６を除去し、コンタクトホール２０７としその部分に
ソース電極２０８、ドレイン電極２０９を形成し、第１
図（ｅ）となる。上記層間絶縁膜２０６には、前記絶縁
薄膜２０４と同じ方法で形成された絶縁膜の他に、ポリ
イミド等の有機膜が使用されることもある。Next, an interlayer insulating film 206 is laminated, and then the insulating thin film 204 and the interlayer insulating film 2
06 is removed, a contact hole 207 is formed, and a source electrode 208 and a drain electrode 209 are formed in the contact hole 207.
The result is shown in Figure (e). In addition to an insulating film formed by the same method as the insulating thin film 204, an organic film such as polyimide may be used for the interlayer insulating film 206.
［発明の効果］
以上述べた様に本発明の薄膜トランジスタによれば、ソ
ース・ドレイン領域となる高濃度不純物を添加した半導
体薄膜層と能動領域となる真性半導体を別途に形成する
必要がない。この為プロセスの簡略化が可能である。[Effects of the Invention] As described above, according to the thin film transistor of the present invention, there is no need to separately form a semiconductor thin film layer doped with high concentration impurities to serve as the source/drain region and an intrinsic semiconductor to serve as the active region. Therefore, the process can be simplified.
さらには、絶縁性基板表面に付与する段差の寸法により
、薄膜トランジスタのチャネル長を決定できるので、大
型基板においても短チャネルの薄膜トランジスタ
大型基板対応のアライナ−の最小加工寸法が、３〜４μ
ｍであり短チャンネルが不可能な現状と比較すると、非
常に効果がある。Furthermore, since the channel length of the thin film transistor can be determined by the dimension of the step provided on the surface of the insulating substrate, the minimum processing size of the aligner for short channel thin film transistors on large substrates is 3 to 4 μm even on large substrates.
This is extremely effective compared to the current situation where short channels are not possible.
第１図（ａ）〜（ｅ）は、本発明の第一の実施例を示す
薄膜トランジスタの製造工程ごとの素子断面図 第２図
（ａ）〜（ｅ）は、本発明の第二の実施例を示す薄膜ト
ランジスタの製造工程ごとの素子断面図。第３図（ａ）
〜（ｅ）は従来の薄膜トランジスタの素子断面図。
１０１、２０１，３０１・・・絶縁性基板１０２、２０
２，３０２・・・ソース・ドレイン領域
１０３、２０３，３０３・・・真性半導体層１０４、２
０４，３０４・・・ゲート絶縁膜１０５、２０５．３Ｃ
１５・・・ゲート電極１０６、２０６，３０６・・・層
間絶縁膜↓
↓
↓
↓
↓
↓
◆
↓
ｒヘノイオンビーム
第１図
０７。
２０７。
３０７・・・コンタクトホー
０８。
０９。
２０８、３０８・・・ソース電極
２０９、 ３０９・・・ドレイン電極
以上FIGS. 1(a) to (e) are cross-sectional views of elements for each manufacturing process of a thin film transistor showing a first embodiment of the present invention. FIGS. 2(a) to (e) are device sectional views showing a second embodiment of the present invention. FIG. 2 is a cross-sectional view of an example thin film transistor for each manufacturing process. Figure 3(a)
-(e) are element cross-sectional views of conventional thin film transistors. 101, 201, 301... Insulating substrates 102, 20
2, 302... Source/drain region 103, 203, 303... Intrinsic semiconductor layer 104, 2
04,304...Gate insulating film 105, 205.3C
15... Gate electrodes 106, 206, 306... Interlayer insulating film ↓ ↓ ↓ ↓ ↓ ↓ ◆ ↓ r Heno ion beam Figure 1 07. 207. 307...Contact Ho08. 09. 208, 308...Source electrode 209, 309...Drain electrode or higher
Claims (1)
純物を添加した半導体層と、能動領域としての真性半導
体層とを有する薄膜トランジスタにおいて、前記絶縁性
基板表面に付与された段差部を含む領域に形成された真
性半導体層に、イオン打ち込みを行う事によりソース・
ドレイン電極を形成したことを特徴とする薄膜トランジ
スタ。In a thin film transistor having a semiconductor layer doped with high concentration impurities as source/drain electrodes on an insulating substrate and an intrinsic semiconductor layer as an active region, the thin film transistor is formed in a region including a stepped portion provided on the surface of the insulating substrate. By implanting ions into the intrinsic semiconductor layer, the source and
A thin film transistor characterized by forming a drain electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9071590A JPH03289137A (en) | 1990-04-05 | 1990-04-05 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9071590A JPH03289137A (en) | 1990-04-05 | 1990-04-05 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03289137A true JPH03289137A (en) | 1991-12-19 |
Family
ID=14006238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9071590A Pending JPH03289137A (en) | 1990-04-05 | 1990-04-05 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03289137A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0418525A (en) * | 1990-05-14 | 1992-01-22 | Matsushita Electron Corp | Liquid crystal display device and production thereof |
-
1990
- 1990-04-05 JP JP9071590A patent/JPH03289137A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0418525A (en) * | 1990-05-14 | 1992-01-22 | Matsushita Electron Corp | Liquid crystal display device and production thereof |
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