JPH06120507A - Thin film transistor - Google Patents

Abstract

PURPOSE:To avoid the fluctuation in the characteristics of the FET used as a load of a SRAM caused by the dispersion in the offset region length in a drain region during manufacturing step. CONSTITUTION:A gate electrode 5 is formed on a polycrystalline silicon film 3 with a TFT channel formed thereon through the intermediary of a gate insulating film 4 and then a P<+>type source region 6 and a P<->type drain 7 are provided. In such a constitution, the impurity concentration in the drain region 7 is lower than that in the source region 6 furthermore, any offset region does not exist in the drain region 7 so that the TFT chracteristics may not be fluctuated by the dispersion in the offset region length.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (Th
In Film Transistor), and more particularly to a thin film transistor used as a load element of a static RAM.

[0002]

2. Description of the Related Art A conventional thin film transistor (hereinafter referred to as TFT) will be described with reference to the drawings.

3 (a) to 3 (c) are sectional views showing the order of steps for explaining a conventional method of manufacturing a TFT.

First, as shown in FIG. 3A, a thickness of 100 to 20 deposited on the silicon substrate 1 by the CVD method.
A thickness of 3 is formed on the 0 nm silicon oxide film 2 by the CVD method.
A polycrystalline silicon film 3 having a thickness of 0 to 50 nm is deposited. next,
Phosphorus is introduced into the polycrystalline silicon film 3 and then patterned to form an active region having an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . Then, a silicon oxide film having a thickness of 20 to 50 nm is deposited on the surface including the polycrystalline silicon film 3 by the CVD method to form the gate insulating film 4.

Next, as shown in FIG. 3B, a polycrystalline silicon film having a thickness of 100 to 150 nm is deposited on the gate insulating film 4 by the CVD method and impurities are introduced to make it conductive. After that, the gate electrode 5 is formed by patterning.
Next, a photoresist film 9 is applied to the surface including the gate electrode 5 and patterned to form a pattern for forming an offset region. Next, with the photoresist film 9 as a mask, boron ions are implanted in the polycrystalline silicon film 3 at a high concentration, and the P ⁺ -type source regions 6 and P having an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ are formed. ^{A +} type drain region 10 is formed. Here, the P ⁺ -type drain region 10 is separated from the end of the gate electrode 5 to form an offset structure, and the impurity concentration of the offset region is lower than that of the P ⁺ -type drain region 10.
^{By using the} -type, it is possible to improve the on / off characteristics of the TFT by, for example, "Spring 1991: 38th Joint Lecture on Applied Physics / Proceedings, 2nd Volume, 671st.
Page, 30p-T-2 ".

Next, as shown in FIG. 3C, after the photoresist film 9 is removed, boron ions are ion-implanted at a low concentration into the polycrystalline silicon film 3 using the gate electrode 5 as a mask so that the impurity concentration is 1 ×. P that is 10 ¹⁷ to 1 × 10 ¹⁸ cm ^-3
- -type offset region 11.

After that, an interlayer insulating film, a metal wiring, a surface protective film, etc. are sequentially formed to form a TFT.

[0008]

[Problems that the Invention is to Solve In the conventional TFT, the P ⁺ type source and drain regions using photoresist film to provide a P- type offset region between the gate electrode and the P ⁺ -type drain region Is forming. In a 4M bit class static RAM, the TFT gate electrode length is about 1.0 μm and the offset region length is about 0.5 μm, but the alignment accuracy of the photoresist mask for determining the source / drain regions is ± 0.15 μm. Since the photoresist mask is misaligned with respect to the gate electrode of the TFT, the low-concentration offset region length varies by 0.35 to 0.65 μm in the manufacturing process of the TFT. Since the variation of the offset region length has a great influence on the on / off characteristics of the TFT, the conventional T
The FT has a problem that the on / off characteristics are likely to vary.

[0009]

Means for Solving the Problem First TFT of the present invention
Is a polycrystalline silicon film of one conductivity type selectively provided on an insulating film provided on a semiconductor substrate, a gate insulating film provided on the surface of the polycrystalline silicon film, and provided on the gate insulating film. A gate electrode, a high impurity concentration reverse conductivity type source region provided in the polycrystalline silicon film in alignment with the gate electrode, and a source region provided in the polycrystalline silicon film in alignment with the gate electrode. And a reverse-conductivity-type drain region having a low impurity concentration and a substantially uniform concentration distribution.

A second TFT of the present invention comprises a gate electrode provided on an insulating film provided on a semiconductor substrate and a block electrode containing one conductivity type impurity, and a gate provided on the surface including the gate electrode and the block electrode. An insulating film; a contact hole formed in the gate insulating film to expose the upper surface of the block electrode; a reverse conductivity type polycrystalline silicon film formed on the gate insulating film including the contact hole; A drain region having one conductivity type low impurity concentration provided in the polycrystalline silicon film connected to the block electrode through the contact hole on one side and a higher concentration than the drain region provided on the other side of the gate electrode. And a source region having an impurity concentration of one conductivity type.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

As shown in FIG. 1, first, a silicon substrate 1
A silicon oxide film 2 having a thickness of 100 to 200 nm is formed thereon by the CVD method. Next, after depositing a polycrystalline silicon film 3 having a thickness of 30 to 50 nm on the silicon oxide film 2 by a CVD method, phosphorus is introduced so as to have an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^−3. Then, patterning is performed to form an active region. Then, a silicon oxide film having a thickness of 20 to 50 nm is deposited on the surface including the polycrystalline silicon film 3 by the CVD method to form the gate insulating film 4. Next, a polycrystalline silicon film having a thickness of 100 to 150 nm is deposited on the gate insulating film 4 and patterned to form a gate electrode 5, which is made conductive by a known means. Next, using a photoresist film, the gate electrode 5 and the drain formation region are masked and boron ions are ion-implanted into the polycrystalline silicon film 3 at a high concentration to form a 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ film. A P ⁺ type source region 6 having an impurity concentration is formed.

At this time, since it is not necessary to form the low-concentration offset region as in the conventional example, the requirement for the alignment accuracy of the photoresist film with respect to the gate electrode is relaxed.

Next, after removing the photoresist film, boron ions are ion-implanted at a low concentration into the polycrystalline silicon film 3 by self-alignment using the gate electrode 5 as a mask, and then 1 × 1.
A P ⁻ type drain region 7 having an impurity concentration of 0 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ is formed.

At this time, the P ⁺ type source region 6 previously formed
Boron is again introduced into the semiconductor substrate, but the impurity concentration of the P ⁺ type source region 6 is sufficiently high and is not affected by the introduction of boron at the time of forming the drain region.

2 (a) and 2 (b) are sectional views showing the order of steps for explaining the manufacturing method of the second embodiment of the present invention.

First, as shown in FIG. 2A, a silicon oxide film 2 formed on a silicon substrate 1 has a thickness of 10
A polycrystalline silicon film of 0 to 150 nm is deposited and patterned to form a gate electrode and a block electrode 5a, and boron is introduced so as to have an impurity concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ . Next, a silicon oxide film having a thickness of 20 to 50 nm is deposited on the surface including the gate electrode 5 and the block electrode 5a to form the gate insulating film 4. Next, the gate insulating film 4 on the block electrode 5a is selectively etched to form a contact hole 8.

Next, as shown in FIG. 2B, a polycrystalline silicon film 3 having a thickness of 30 to 50 nm is formed on the gate insulating film 4.
Then, phosphorus is introduced and patterned to form 1 × 1
An active region having an impurity concentration of 0 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ is formed. Next, heat treatment is performed in a nitrogen atmosphere at 900 ° C. to diffuse boron from the block electrode 5a in the contact hole 8 into the polycrystalline silicon film 3 to form 1 × 10 ¹⁸ cm ^−3.
A P ⁻ type drain region 7 having an impurity concentration of less than is formed.
At this time, the gate electrode 5 is adjusted by adjusting the heat treatment time.
It is possible to stop the diffusion of boron forming the P ⁻ type drain region 7 at the edge of the. Even if the end of the P ⁻ type drain region 7 is slightly inward from the end of the gate electrode 5, T
Although it does not seriously affect the electrical characteristics of FT, when a conventional TFT having a low concentration offset region is manufactured by this method, the length of the offset region must be strictly controlled using a photoresist mask. The difficulty of manufacturing increases. Next, the photoresist film is used to mask the channel region of the polycrystalline silicon film 3 and the P ⁻ -type drain region 7, and boron is introduced into the polycrystalline silicon film 3 at a high concentration to obtain 1 × 10 ¹⁹ to 1 × 10 7. A P ⁺ type source region 6 having an impurity concentration of ²⁰ cm ⁻³ is formed.

[0020]

As described above, the present invention eliminates the offset region by making the impurity concentration in the drain region lower than the impurity concentration in the source region and making the impurity concentration distribution in the drain region substantially constant. The effect of relaxing the requirement for the alignment accuracy of the photoresist film with respect to the gate electrode when introducing a high concentration impurity into the source region using the photoresist film is obtained.

Further, the TFT of the present invention can be used as a static RA.
When used as a load element of M, the off characteristic of the TFT, which is particularly important, is not impaired as compared with the conventional TFT.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention.

2A to 2D are sectional views showing the manufacturing method of the second embodiment of the present invention in the order of steps for explaining the manufacturing method.

3A to 3D are cross-sectional views showing the order of steps for explaining a conventional method for manufacturing a TFT.

[Explanation of symbols]

1 Silicon Substrate 2 Silicon Oxide Film 3 Polycrystalline Silicon Film 4 Gate Insulating Film 5 Gate Electrode 5a Block Electrode 6 P ⁺ Type Source Region 7 P ⁻ Type Drain Region 8 Contact Hole 9 Photoresist Film 10 P ⁺ Type Drain Region 11 P ⁻ Mold offset area

Claims (2)

[Claims] 1. A polycrystalline silicon film of one conductivity type selectively provided on an insulating film provided on a semiconductor substrate, a gate insulating film provided on the surface of the polycrystalline silicon film, and on the gate insulating film. A high-impurity-concentration reverse-conductivity-type source region provided in the polycrystalline silicon film in alignment with the gate electrode, and the source provided in the polycrystalline silicon film in alignment with the gate electrode. A thin film transistor having an opposite conductivity type drain region having an impurity concentration lower than that of the region and having a substantially uniform concentration distribution. 2. A gate electrode provided on an insulating film provided on a semiconductor substrate and a block electrode containing an impurity of one conductivity type,
A gate insulating film provided on the surface including the gate electrode and the block electrode, a contact hole provided on the gate insulating film to expose the upper surface of the block electrode, and a reverse provided on the gate insulating film including the contact hole. A conductive type polycrystalline silicon film, a drain region having one conductivity type low impurity concentration provided in the polycrystalline silicon film connected to the block electrode through the contact hole on one side of the gate electrode, and the gate electrode A thin film transistor, comprising: a source region provided on the other side and having a higher concentration of one conductivity type impurity concentration than the drain region.