JPH0354865A - Thin film field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an FET with a higher mu-factor and a less leakage current by surrounding a region where a gate electrode includes a channel region of an active layer semiconductor thin film via a gate insulating to apply an electric field over the whole thin film. CONSTITUTION:A first gate electrode 2 and a second gate electrode 7 surround a channel region 4b of an active layer semiconductor thin film 4 via gate insulating films 3, 5. Additionally, the electrodes 2, 7 are connected with each other via a contact 6 and electric potentials thereof become equal to each other. Accordingly, a channel can be formed with satisfactory controllability in the vicinity of an upper surface S1 and side surfaces S2, S3 in contact with the films 3, 5 of the region 4b. Hereby, the effective width of the channel is increased with a mu-factor increased. Further, since the electrodes 2, 7 apply the electric field over the whole film 4 to control the potential of the whole region 4b, a leakage current flowing through the film 4 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a thin film field effect transistor, and more particularly to a thin film field effect transistor with a high amplification factor and low leakage current, and a method for manufacturing the same.

(Prior art) Thin film field effect transistor (TFT)
A film transistor is a field effect transistor in which a source, drain, and channel are provided in a semiconductor thin film formed on an insulating layer (an insulating layer formed on an insulating substrate or other substrate). The conventional TPT is.
There are two types: (1) those in which a gate insulating film is provided on the upper surface of a semiconductor thin film, and (2) those in which a gate insulating film is provided on the lower surface of a semiconductor thin film.

The above type (1) TPT will be explained with reference to FIG. After depositing the semiconductor thin film 4 on the insulating layer l, a resist having an active region pattern is formed and the semiconductor thin film is subjected to RIE (RIE).
Patterning is performed by reactive ion etching (reactive ion etching), etc.

Next, after removing the resist, a gate insulating film 9 is formed on the semiconductor thin film 4, and a material for a gate electrode 10 is deposited. After this. A resist having a pattern of the gate electrode 10 is formed, and the gate electrode material and gate insulating film 9 are patterned by RIE. Subsequently, impurity ions are implanted to form the source/drain 4a, 4C and channel region 4b in a self-aligned manner.

next. The TPT of type (2) will be explained with reference to FIG. First, after depositing the material for the gate electrode lO,
A resist having a pattern of the gate electrode 10 is formed.
Buttering the gate electrode material. Next, after removing the resist, a gate insulating film 9 is formed on the gate electrode 10. Deposit semiconductor thin film 4. After this, a resist having an active layer pattern is formed, and a semiconductor thin film 4 is formed by RIE.
and patterning the gate insulating film 9. Subsequently, after forming a resist pattern, impurity ions are implanted to form the source/drain 4a, 4c and channel region 4b.
form.

(Problems to be Solved by the Invention) However, the above-mentioned conventional technology has the following problems.

Since the TPT is a transistor formed in a semiconductor thin film such as a non-quality silicon film or a polycrystalline silicon film, there is a problem in that the leakage current between the source and drain is larger than that in a transistor formed in single crystal silicon. Furthermore, the amplification factor of TPT was low because the carrier mobility in the semiconductor thin film is inferior to the carrier mobility in a single crystal.

The present invention has been made to solve the above problems, and its purpose is to: It is an object of the present invention to provide a thin film field effect transistor with low leakage current and high amplification factor.

(Means for Solving the Problems) A thin film field effect transistor of the present invention includes a first gate electrode formed on an insulating layer; a first gate insulating film formed on the first gate electrode; a semiconductor thin film formed on the first gate insulating film; a channel region formed in the semiconductor thin film; formed on the semiconductor thin film. a second gate insulating film that covers at least all of the upper surface and two side surfaces of the channel region; a second gate electrode covering all of the top surface and two side surfaces, the second gate electrode and the first gate electrode being electrically connected; This achieves the above objective.

The method for manufacturing the thin film field effect transistor of the present invention is as follows. A method for manufacturing a thin film field effect transistor according to claim 1. After forming the second gate electrode, impurity ions are implanted into the semiconductor thin film to form a source and drain in a self-aligned manner. Thereby, the above objective is achieved.

(Example) The present invention will be described below with reference to Examples. FIG. 1 shows a plan view of an embodiment of the apparatus of the present invention, FIG. 2A shows a sectional view taken along line AA in FIG. 1, and FIG. 2B shows a sectional view taken along line BB.

A first gate electrode 2 is formed on an insulating layer (an insulating layer formed on an insulating substrate or other substrate) l, and a first gate insulating film 3 is formed on the first gate electrode 2. is formed. A source/drain 4a is formed on the gate insulating film 3.
, 4c and a channel region 4b, a polycrystalline silicon semiconductor thin film (thickness: 600 mm) 4 is provided as an active layer of the TPT.

A second gate electrode 5 is formed on the surface of the semiconductor thin film 4 including the upper surface S1 and two side surfaces S2 and S3 of the channel region 4b shown in FIG. 2B. A second gate electrode 7 covers the upper surface Sl and two side surfaces S2 and S3 of the channel region 4b via the second gate insulating film 5.

The second gate electrode 7 is in contact with the first gate electrode 2 via a contact 6. Therefore, the potential of the l-th gate electrode 2 and the potential of the second gate electrode 7 are equal.

In this embodiment, as shown in FIG. 1, FIG. 2A, and FIG. 2B. The first gate electrode 2 and the second gate electrode 7 surround the channel region 4b of the TPT active layer semiconductor thin film 4 via the gate insulating film 3.5. Also, the first
The potential of the gate electrode 2 and the potential of the second gate electrode are equal. Therefore, the electric field due to the first and second gate electrodes 2 and 7 is . In the vicinity of the upper surface Sl, lower surface and side surfaces S2 and 33 in contact with the gate insulating films 3 and 5 of the channel region 4b,
An inversion layer (channel) can be formed with good controllability. Therefore, the effective width W of this channel is approximately expressed by the following equation using the thickness t of the active layer and the width W of the active layer (channel region).

W=2(t+w) Generally, the amplification factor of TPT is proportional to the effective width W of the channel.

As shown in the above equation, the effective width W of the channel of the TPT of this embodiment is significantly increased compared to the conventional one (W=w), and the TPT has a correspondingly large amplification factor.

In addition, the first gate electrode 2 and the second gate electrode 7 apply an electric field to the entire active layer semiconductor thin film 4, thereby controlling the potential of the entire channel region 4b of the active layer semiconductor thin film M4. The leakage current flowing through the active layer semiconductor thin film 4 observed in the conventional example is significantly reduced.

In this way, the T-FT of this embodiment has its channel region 4b.
The region including the gate electrode 2 is connected to the gate electrode 2 via the gate insulating film 3.5
．． 7, it is possible to achieve a large amplification factor and low leakage current.

Next, the manufacturing method of this example is shown in FIGS. 3A and 3B (1
) to (4). Figure 3A is A of Figure 1.
A sectional view taken along line A and FIG. 3B are sectional views taken along line BB in FIG. 1, and the left and right views correspond to the respective steps (1) to (4).

First, a polycrystalline silicon film (500 nm thick) is deposited as a material for the first gate electrode 2 by the CVD method on the insulating Nl, and then phosphorus is diffused into the polycrystalline silicon film. Thereafter, a first gate insulating film (thickness: 500 mm) 3 is formed on the surface of the polycrystalline silicon film using the CVD method (see Fig. 3A).
1) and Figure 3B (1)).

Next, a polycrystalline silicon film (film thickness: 600), which will become the active layer 4.
is deposited on the gate insulating film 3 by the CVD method. Perform ion implantation to adjust the threshold voltage.

After forming a resist pattern having a desired pattern as an active layer on the gate insulating film 3, the polycrystalline silicon film is patterned using a method such as RIE (reactive ion etching).

The resist pattern is removed, and a second gate insulating film (film thickness: 500 mm) is formed on the surface of the patterned polycrystalline silicon by the CVD method (see Figure 3A (2) and Figure 3).
Figure B (2)). Next, in order to expose a predetermined part of the surface of the first gate electrode 2. Figure 3A (3) and 3rd
After forming a resist having a pattern of contact holes 6 as shown in Figure B (3). First gate insulating film 3
Etch. After depositing a polycrystalline silicon film (thickness: 3000 nm) as a material for the second gate electrode 7 using the CVD method, phosphorus is diffused into the polycrystalline silicon film. Next, a resist pattern having the pattern of the second gate electrode 7 is formed on the polycrystalline silicon film, and then the polycrystalline silicon is patterned using a method such as RIE. The second gate electrode 7 thus formed covers the channel region 4b of the TPT via the second gate insulating film 5, and serves as a mask for ion implantation in the next step. Next, Figure 3A (4
) and as shown in Figure 3B (4). After boron (B) is ion-implanted into the active layer semiconductor thin film 4, the boron is activated to form sources and drains 4a and 4c.

Thereafter, by forming an interlayer insulating film, wiring, etc. (not shown), the TPT of this example is manufactured.

In the manufacturing method of this embodiment, a second gate insulating film 5 is formed on the region that will become the channel region 4b of the active layer semiconductor thin film 4.
After forming the second gate electrode 7 via the ion implantation method, ion implantation is performed to form the source and drain. Sources and drains 4a and 4c are formed in a self-aligned manner.

As a result, the second gate electrode 7 and the source/drain 4a. Since the positional relationship with the 4C end is matched, the operational performance and manufacturing yield of the TPT can be improved, and the TPT can be miniaturized.

Note that in this embodiment, the first and second gate electrodes 2.7
A polycrystalline silicon film was used as the material. Other high melting point conductive materials may be used, such as a multilayer film of high melting point materials such as high melting point metal, high melting point metal silicide, or polycide.

(Effects of the Invention) As described above, according to the thin film field effect transistor of the present invention, the amplification factor is greatly increased and leakage current is significantly reduced.

Further, according to the method for manufacturing a thin film field effect transistor of the present invention. Since the gate electrode and the source/drain can be matched with good controllability, it is possible to easily miniaturize elements and improve transistor characteristics with high yield.

4. Figure 1 is a plan view for explaining an embodiment of the present invention;
Figure 2A is a sectional view taken along line AA in Figure 1, Figure 2B is a sectional view taken along line BB in Figure 1, and Figures 3A (1) to (4).
) and Figures 3B (1) to (4) are sectional views taken along line AA and line BB in Figure 1, Figure 4, and Figure 3B (1) to (4) respectively. FIG. 5 is a sectional view for explaining a conventional example.

1...Insulating layer. 2...l-th gate electrode, 3...
No. 2 gate insulating film, 4... active layer semiconductor thin film, 4a
, 4c... Source/drain, 4b... Channel region, 5... Second gate insulating film, 6... Contact hole, 7... Second gate electrode, 8... Resist 9 ...gate insulating film, lO...gate electrode, SL
... Upper surface of the channel region, S2, S3 ... Side surfaces of the channel region.

that's all

Claims (1)

[Claims] 1. A first gate electrode formed on an insulating layer;
a first gate insulating film formed on the gate electrode; a semiconductor thin film formed on the first gate insulating film; and a channel region formed in the semiconductor thin film. a second gate insulating film formed on the semiconductor thin film and covering at least an upper surface and two side surfaces of the channel region; a second gate insulating film formed on the second gate insulating film; a second gate electrode covering all of the upper surface and two side surfaces of the channel region, the second gate electrode and the first gate electrode being electrically connected, a thin film field effect transistor. 2. The method for manufacturing a thin film field effect transistor according to claim 1, wherein after forming the second gate electrode,
A method for manufacturing a thin film field effect transistor, in which a source and a drain are formed in a self-aligned manner by implanting impurity ions into the semiconductor thin film.