JPH0312935A - Manufacture of electronic device - Google Patents

Abstract

PURPOSE: To make continuous masks not be aligned during an assembling process, by exposing photoresist material stuck on a substrate to a light transmitting the substrate, before the material is chemically etched. CONSTITUTION: In photolithographic masking and chemical etching processes, photoresist material 16 stuck on the single side of a transparent substrate 10 is exposed to a light transmitting the substrate 10, before chemical etching. That is, by self-alignment effect wherein a photoresist layer 16 is exposed to the light through the transparent substrate 10, excellent precision is achieved in the mutual formation of source, gate and drain contacts. Thereby it can be evaded that continuous masks are accurately aligned during transistor manufacture.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing electronic devices, and is particularly applicable to the manufacture of field effect transistors from diamond materials, as well as transistors made by the same method.

FETs have been manufactured that include an entirely conventional field effect transistor (FET) structure fabricated on a diamond substrate instead of a silicon substrate. Due to the physical properties of diamond, it has superior properties in this application over silicon (Si), gallium arsenide (GaAs) or other known semiconductor materials. In particular, diamond FETs can offer lower resistance, higher gain and maximum frequency than transistors using conventional materials.

Field-effect transistors are conventionally made with the help of photolithographic masking and chemical etching methods, whereby the gate and drain regions of the transistor are photolithographically defined using a photoresistor material and the substrate of the transistor is The various overly deposited mask layers are selectively removed by etching to form the source, gate and drain regions and metal contacts to these regions. Due to the small size of transistor structures, it is difficult to align successive masks during the assembly process. Thus, conventional technology tolerances set lower limits on the size of transistor structures, thereby placing limits on some of the transistor's operating parameters, such as its high frequency limitations.

In accordance with one aspect of the invention, a photolithographic process is performed in which a photoresist material deposited on a substrate is exposed to light transmitted through the substrate prior to chemical etching.
A method of manufacturing an electronic device is provided that includes a masking and chemical etching step.

More particularly, in accordance with the present invention, a method for manufacturing an electronic device on a semiconductor substrate that is transparent to light of a particular wavelength comprises: selective photolithographic masking and chemical etching, including processing and exposing a layer of photoresist material deposited on one side of the substrate to light of a specific wavelength transmitted through the substrate from a light source on the other side of the substrate; forming a conductive contact in the region.

In one embodiment according to the invention, a method of manufacturing a field effect transistor includes the steps of: providing a diamond substrate transparent to light of a predetermined wavelength; and forming source, gate, and drain regions of the transistor on or in the substrate. forming and forming source, gate and drain region contacts by selective photolithographic masking and chemical etching, the at least one masking and etching step of forming photoresist material deposited on one side of the substrate; forming a contact in the region including subjecting the layer to light of a predetermined wavelength passing through the substrate from a light source on the other side of the substrate.

Another preferred embodiment method includes the steps of: providing a p-type diamond substrate transparent to ultraviolet light; depositing a layer of insulating material on a surface of the substrate; and depositing a layer of insulating material on the layer of insulating material. depositing a layer of a first metal; selectively removing the deposited layer to form a gate region of the transistor; and depositing source and drain regions of the transistor adjacent the gate region by ion implantation or chemical etching. forming a layer of photoresist material over the source, gate and drain regions; exposing the layer of photoresist material to ultraviolet light passing through the substrate; removing the exposed photoresist material remaining over the gate region; depositing a second layer of metal over the source, gate and drain regions; and depositing a second layer of photoresist material over the gate region. selectively removing layers of two metals, thereby resulting in a MISFET structure comprising source and drain contacts of the second metal and gate contacts of the first metal; Contains.

The layer of insulating material may include an oxide, nitride, oxynitride, or carbide.

The first metal is preferably a metal with a low work function such as aluminum or chromium.

Preferably, the second metal is a high work function metal such as gold, platinum, a gold/tantalum alloy, or palladium.

Embodiments of the invention will now be described in detail with reference to the accompanying drawings.

In FIG. 1g, a substrate 10 of optically transparent p-type diamond material is shown.

A thin layer 12 of insulating material is deposited on the surface of substrate 10. Insulating layer 12 includes an oxide, nitride, oxynitride, or carbide material.

As shown in FIG. 1, a layer 14 of a first metal is deposited over the layer 12 of insulating material. The first metal is a low work function metal such as aluminum or chromium.

The next step, shown in Figure 1c, is to form the gate region of the transistor. This is accomplished by conventional photolithographic masking and chemical etching steps that selectively remove layers 12 and 14 except in the area of the gate (G).

The next step in the process is to remove the source (S) and drain (D).
) regions are formed in the upper surface of substrate 10 by ion implantation or chemical etching of discrete regions adjacent the gate regions. For ion implantation, boron, gallium,
Carbon or lithium ions are used. Alternatively, argon etching can be used. The source and drain regions span the surface of substrate 10 as shown in Figure 1d.

1e, a layer 16 of photoresist material sensitive to ultraviolet (UV) light is deposited over the structure shown in FIG. 1d. This structure is then exposed to ultraviolet light from below the substrate 10. Since the substrate 10 is transparent to UV light, the photoresist layer 16 is exposed to this light except over the gate region (G), where the metal layer 14 is exposed to the UV light.
Shield the photoresist layer from light.

Photoresist layer 16 is subsequently treated with a solvent, which dissolves layer 16 in the areas exposed to UV light.

Thus, following this step, the photoresist layer 16 is removed except from the metal layer 14 over the gate region (G).

This is shown in Figure 1f.

In Figure 1g, a layer of second metal 18 has been deposited over the entire substrate. The second metal is a low work function metal such as gold, platinum, a gold/tantalum alloy, or palladium.

Finally, as shown in the diagram, a lift-off etch (1if-offet) is performed to remove the layer 16 of photoresist material over the gate region while exposing the metal layer 14.
ch) method is used. The layer of second metal 18 is trimmed without removing portions of the layer that are not overlying the source and drain regions of the transistor. In this way, MIS
The FE structure is fabricated with source and drain contacts of the second metal and gate contacts of the first metal.

Due to the self-aligned effect of exposing the photoresist layer 16 through the transparent substrate 10, great precision is achieved in the mutual formation of the source, gate and drain contacts. In particular, the problem of accurately aligning successive masks during transistor fabrication is avoided.

[Brief explanation of the drawing]

FIG. 1 shows the manufacturing process for manufacturing a field effect transistor according to the present invention. Explanation of symbols: 1 10... Substrate; 12... Layer of insulating material; 14... Layer of first metal; 16... Layer of photoresist material; 18... Layer of second metal;

Claims (7)

[Claims] (1) comprising a photolithographic masking and chemical etching step such that a photoresist material deposited on one side of a transparent substrate is exposed to light transmitted through the substrate prior to chemical etching; A method of manufacturing electronic devices. (2) treating the substrate to form at least one region having electrical properties different from the substrate and transmitting light through the substrate from a light source on the other side of the substrate to a layer of photoresist material deposited on one side of the substrate; forming conductive contacts in the region by selective photolithographic masking and chemical etching; A method of manufacturing electronic devices on a semiconductor substrate. (3) providing a diamond substrate transparent to light of a predetermined wavelength; forming transistor source, gate, and drain regions on or in the substrate; and selective photolithographic masking and chemical forming contacts of the source, gate, and drain regions by etching, at least one masking and etching step of passing through the substrate from a light source on the other side of the substrate to a layer of photoresist material deposited on one side of the substrate; A method of manufacturing a field effect transistor, comprising the step of: forming the region, the region being exposed to light of a predetermined wavelength. (4) providing a p-type diamond substrate transparent to ultraviolet light, depositing a layer of insulating material on the surface of the substrate, and depositing a layer of a first metal on the layer of insulating material; selectively removing the deposited layer to form a gate region of the transistor; forming source and drain regions of the transistor adjacent the gate region by ion implantation or chemical etching; depositing a layer of photoresist material over the gate and drain regions; and exposing the layer of photoresist material to ultraviolet light passing through the substrate, such that the layer of photoresist material remains over the gate region. removing the exposed photoresist material; depositing a layer of a second metal over the source, gate, and drain regions; and selectively depositing the layer of photoresist material, i.e., the layer of second metal over the gate region. removing the MISFET, thereby comprising source and drain contacts of the second metal and gate contacts of the first metal;
4. A method according to claim 3, comprising the step of selectively removing a (metal-insulated semiconductor field-effect transistor) structure. (5) The layer of insulating material is oxide, nitride, oxynitride,
The method according to claim 4, characterized in that the method comprises a carbide or a carbide. (6) Claim 4 or 5, wherein the first metal is a metal with a low work function such as aluminum or chromium.
Method by description. (7) The method according to any one of claims 4 to 6, wherein the second metal is a metal with a high work function such as gold, platinum, a gold/tantalum alloy, or palladium.