KR19980057703A - Gate Forming Method of Semiconductor Device - Google Patents

Abstract

The present invention discloses a gate forming method of a semiconductor device. The method may include forming a first oxide film on the semiconductor substrate; Forming a gate conductive layer on the first oxide layer using a conductive material; Forming a second oxide film on the gate conductive layer; Patterning the second oxide film and the gate conductive layer using a photolithography method; Forming a spacer on sidewalls of the patterned second oxide / gate conductive layer using an insulating material; Etching the first oxide layer using the spacers as a mask; Removing the second oxide film; And forming a silicide layer on the gate conductive layer and on the surface of the semiconductor substrate. As a result, the silicide layer is prevented from becoming a constant shape due to over-etching or under-etching of the insulating film during the etching process of the insulating film for forming the spacer, thereby providing an electrically stable gate.

Description

Gate Forming Method of Semiconductor Device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device.

Highly integrated semiconductor devices are generally composed of numerous MOS Field Effect Transistors (MOSFETs). In order to achieve higher integration, the MOSFETs are formed in a very small size. As the size becomes smaller, the sheet resistance of the MOSFET increases. This increase in sheet resistance results in delayed signal transmission time in the integrated circuit.

On the contrary, if the sheet resistance is reduced, the signal transmission time can be shortened.

Another problem of high integration is that the contact resistance increases as the contact area between the gate and the source / drain and the wiring layer becomes smaller. This delays the signal transmission time as above.

In order to solve the problem of increasing the sheet resistance and the contact resistance of the MOSFET, a semiconductor device having a salicide (self aligned silicide) structure is used.

1A to 1D are cross-sectional views sequentially illustrating a gate forming method of a semiconductor device according to the prior art.

Reference numeral 1 denotes a semiconductor substrate, 3 占 a represents an oxide film, 5 represents a gate conductive layer, 7 represents an insulating film, 7a represents a spacer, and 9a 占 9b represents a silicide layer.

Referring to FIG. 1A, after the oxide film 3 is formed on the semiconductor substrate 1, the gate conductive layer 5 is formed on the oxide film 3 using a conductive material.

The gate conductive layer 5 is formed by depositing polycrystalline silicon doped with impurities on the oxide film 3 and patterning the same using a photo process.

Subsequently, a process of forming an oxide film (not shown) having a thickness of several hundred micrometers on the surface of the gate conductive layer 5 is performed.

Referring to FIG. 1B, an insulating material is deposited on the entire surface of the semiconductor substrate 1 on which the gate conductive layer 5 is formed to form an insulating film 7.

The insulating film 7 is to form an insulating spacer on the sidewall of the gate conductive layer 5 and is patterned in a subsequent process.

Referring to FIG. 1C, the insulating layer 7 is etched until the gate conductive layer 5 is exposed to form a spacer 7a on the sidewall of the gate conductive layer 5, and then the oxide layer 3 is etched. An oxide film 3a is formed under the jade conductive layer 5.

When the insulating layer is etched, the oxide layer on the gate conductive layer 5 is also etched.

In the etching process for forming the spacer 7a, it is difficult to control the etching degree, so that the insulating layer 7 on the sidewall of the gate conductive layer 5 is overetched or the upper portion of the gate conductive layer 5 and the semiconductor substrate 1 are etched. The phenomenon that the insulating film remains on the surface is not completely removed.

When the insulating layer 7 on the sidewall of the gate conductive layer 5 is overetched, a portion of the sidewall of the gate conductive layer 5 is exposed to form a portion of the gate conductive layer 5 and the surface of the semiconductor substrate during subsequent silicide layer formation. There is a problem that the short between the silicide layer, and if the insulating film on the gate conductive layer 5 remains, there is a problem that the silicide layer is not formed because titanium and silicon as the constituent material of the gate conductive layer 5 do not react. .

Referring to FIG. 1D, titanium (Ti) is deposited on the entire surface of the semiconductor substrate 1 formed as a result of the processes, and then heat-treated to form silicide layers 9a and 9b on the surface of the gate conductive layer 5 and the semiconductor substrate 1. ) And a process of removing unreacted titanium on the spacer 7a.

As a result, a gate oxide film composed of the oxide film 3a and a gate electrode of the silicide layer 9a / gate conductive layer 5 structure are completed.

The silicide layers 9a and 9b are formed by reacting titanium (Ti) with silicon (Si) which is a constituent material of the gate conductive layer 5 and the semiconductor substrate 1 during heat treatment. It is for.

Accordingly, the constituent materials of the silicide layers 9a and 9b may be titanium silicide (TiSi₂), and may be formed by heat-treating metals such as platinum (Pt) and molybdenum (Mo).

During the heat treatment, the gate conductive layer 5 exhibits a silicide reaction not only on the top thereof but also on sidewalls exposed when the spacer 7a is formed. This narrows the gap between the silicide layer 9a formed on the top and sidewalls of the gate conductive layer 5 and the silicide layer 9b formed on the surface of the semiconductor substrate 1, and as a result, the silicide layer 9a and the silicide layer. There is a problem that 9b is electrically shorted.

An object of the present invention is to provide a method for forming a gate of a semiconductor device to eliminate the problems caused by over or under etching of the insulating film during the etching process of the insulating film for forming the spacer.

1A to 1D are cross-sectional views sequentially illustrating a gate forming method of a semiconductor device according to the prior art.

2A through 2E are cross-sectional views sequentially illustrating a method of forming a gate of a semiconductor device according to the present invention.

The present invention to achieve the above object, the step of forming a first oxide film on the semiconductor substrate; Forming a gate conductive layer on the first oxide layer using a conductive material; Forming a second oxide film on the gate conductive layer; Patterning the second oxide film and the gate conductive layer using a photolithography method; Forming a spacer on sidewalls of the patterned second oxide / gate conductive layer using an insulating material; Etching the first oxide layer using the spacers as a mask; Removing the second oxide film; And forming a silicide layer on the gate conductive layer and on the surface of the semiconductor substrate.

The second oxide layer may be removed by a reactive ion beam etching (RIE) method using a mixed gas including CF 4, CHF 3, and an inert gas.

Accordingly, the method for forming a gate of a semiconductor device according to the present invention forms an electrically stable gate by preventing the silicide layer from becoming a constant shape due to overetching or underetching of the insulating film during the etching process of the insulating film for forming the spacer. There is an advantage to this.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views sequentially illustrating a method of forming a gate of a semiconductor device according to the present invention.

Reference numeral 21 denotes a semiconductor substrate, 23 · 23a denotes a first oxide film, 25 denotes a gate conductive layer, 27 denotes a second oxide layer, 29 denotes an insulating film, 29a denotes a spacer, and 31a · 31b denotes a silicide layer. .

2A shows a process of forming a first oxide film 23 on a semiconductor substrate 21, a process of forming a gate conductive layer (patterned to 25 in a subsequent process) using a conductive material on the first oxide film, and the gate Forming the second oxide film (patterned to 27 in a subsequent process) on the conductive layer and patterning the second oxide film / gate conductive layer using a photolithography method to form the second oxide film 27 / gate conductive layer 25 The process of forming) is carried out in order.

The gate conductive layer 25 is formed using polycrystalline silicon doped with impurities.

The process of forming the second oxide film 27 / gate conductive layer 25 will be described in detail. First, a photoresist film (not shown) is deposited on the second oxide film, and the gate of the semiconductor substrate 21 is removed. Patterning the photoresist film so as to expose a portion other than a portion to be formed, etching the second oxide film using the patterned photoresist as a mask to form a second oxide film 27, removing the photoresist film, and The process of etching the gate conductive layer is sequentially performed using the second oxide film 27 as a mask.

The second oxide layer 27 is formed to prevent the sidewall of the gate conductive layer 25 from being exposed in the process of etching the insulating layer to form a subsequent spacer.

Subsequently, a process of forming an oxide film (not shown) having a thickness of several hundred micrometers on the surface of the second oxide film 27 / gate conductive layer 25 is performed.

Referring to FIG. 2B, an insulating material is deposited on the entire surface of the semiconductor substrate 21 to form an insulating film 29.

The insulating layer 29 is formed on the sidewalls of the gate conductive layer 25 to be patterned in a subsequent process.

Referring to FIG. 2C, the insulating layer 29 is etched until the second oxide layer 27 is exposed to form spacers 29a on sidewalls of the second oxide layer 27 and the gate conductive layer 25.

At this time, the second oxide film 27 is performed in an atmosphere where the etching is not etched.

Subsequently, the first oxide film 23 is etched using the spacer 29a as a mask to form a first oxide film 23a.

Referring to FIG. 2D, the second oxide layer 27 is removed.

At this time, the spacer 29a and the surface of the semiconductor substrate 21 proceed in an atmosphere not etched.

In one embodiment, a mixed gas including CF 4, CHF 3, and an inert gas may be used to perform a reactive ion-beam etching (RIE) method. The result is the second oxide layer 27 as shown in FIG. 3. It can be clearly seen that this has been completely removed.

Referring to FIG. 2E, titanium (Ti) is deposited on the entire surface of the semiconductor substrate 21 and then heat-treated to form silicide layers 31a and 31b on the gate conductive layer 25 and the surface of the semiconductor substrate 21. A process of removing unreacted titanium on the spacer 29a is performed.

The silicide layers 31a and 31b are formed by reacting titanium (Ti) with silicon (Si), which is a constituent material of the gate conductive layer 25 and the semiconductor substrate 21 during heat treatment. It is for.

The silicide layers 31a and 31b may be made of titanium silicide TiSi₂, and may be formed by heat-treating metals such as platinum (Pt) and molybdenum (Mo).

As a result, a gate oxide film made of the first oxide film 23a and a gate electrode of the silicide layer 31a / gate conductive layer 25 structure are completed.

The present invention is not limited to this, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, the gate forming method of the semiconductor device according to the present invention prevents the silicide layer from becoming a constant shape due to overetching or underetching of the insulating film during the etching process of the insulating film for forming the spacer. As a result, a stable gate can be formed.

Claims (2)

Forming a first oxide film on the semiconductor substrate; Forming a gate conductive layer on the first oxide layer using a conductive material; Forming a second oxide film on the gate conductive layer; Patterning the second oxide film and the gate conductive layer using a photolithography method; Forming a spacer on sidewalls of the patterned second oxide / gate conductive layer using an insulating material; Etching the first oxide layer using the spacers as a mask; Removing the second oxide film; And Forming a silicide layer on the gate conductive layer and on the surface of the semiconductor substrate. The method of claim 1, wherein the second oxide film A method of forming a gate of a semiconductor device, characterized in that the removal by the reactive ion beam etching (RIE) method using a mixed gas containing CF4, CHF3 and an inert gas.