JPS62224084A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To improve the performance of a field-effect transistor by forming at least a second layer and first and third layers in films consisting of three layers by films having difference characteristics. CONSTITUTION:Since a first layer film 3 has a function separating other electrodes such as source-drain and a gate electrode to be shaped, a distance between source-drain and a distance between gate-drain are determined through a hole 6 is bored to the first layer 3 while the film thickness of a second layer 7 decides gate size. A third layer 8 is used for burying the hole 6 formed in the first layer 3 and it is desirable that the film thickness of the third layer 8 is set at approximately a value acquired by subtracting the thickness of the second layer 7 from the thickness of the first layer 3, thus bringing film thickness up to the third layer 8 in a region, in which the hole in the first layer 3 is bored, to approximately the same as the thickness of the first layer 3 in other regions. On the other hand, a resist is buried into the recessed section in order to remove the third layer 8 except the recessed section 6, and a photo- resist film is eliminated, thus forming an approximately flat surface.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing a high-performance junction field effect transistor, and in particular, to a method for producing a gate electrode with stability, high precision, and high reliability of the device. It's about things.

[Conventional technology]

It was believed that the conventional method could form an ultra-fine gate pattern with an offset structure, as described in Japanese Patent Laid-Open No. 60-70768. It is true that the shortening between the source and gate is self-aligned, but no consideration was given to forming the gate metal pattern.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into account the formation of gate metal, and there are basic problems in transistor operation and difficulties in manufacturing methods. In other words, the distance between the source region and gate electrode is very short, and the second insulating film must be removed and buried in it to form the gate metal. There is a risk that a short circuit may occur through the gate metal. The lift-off method cannot be applied to gate metal formation in this case. Further, the gate electrode drawing method also increases the number of steps, which increases the complexity of the steps.

An object of the present invention is to solve the above-mentioned drawbacks, provide a manufacturing method with high stability and high reproducibility in device manufacturing, and improve the performance of field effect transistors.

[Means for solving problems]

The objectives listed below can be achieved by following the outline below. Three types of membranes are used in Figure 1. These three types of membranes are 1. Second
．． The third layer consists of at least the second layer and the first layer. The third layer is a film with different characteristics. For example, etching properties also fall into this category. Second.

1st. Second. The uneven portions formed by the third layer are flattened by conventional physical and chemical etching methods using a photoresist film or the like.

Therefore, the gist of the present invention is to form a fine pattern by overlapping up to the third layer, and to easily form even a metal pattern, and is based on the above gist.

[Effect]

The three-layer film is used for the following reasons. The first layer film has the function of separating the gate electrode to be formed from other electrodes such as the source/drain.Therefore, although a hole is made in the first layer, the distance between the source and drain and the distance between the gate and drain You'll have to decide on the distance. The second M determines the gate dimensions. In other words, the gate dimensions are approximately determined by the thickness of the second layer. The third layer is used to fill the hole formed in the first layer, and the thickness of the third layer should be set to approximately the value obtained by subtracting the thickness of the second layer from the thickness of the first layer. is desirable. Therefore, the thickness of the first layer up to the third layer in the region where the hole is formed is approximately the same as the thickness of the first layer in other regions.

On the other hand, in order to remove the third layer other than the recessed portions, this method of embedding a resist in the recessed portions, leaving the resist in that portion, and removing the third layer through it is a relatively easy method. Of course, this photoresist film is removed after the third layer is partially removed.

As a result, a substantially flat surface can be formed.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the process steps shown in FIG.

Example 1 As shown in FIG. 1(a), an active layer and
Sort 4 and drain 5 electrodes were formed.

That is, Si ions were implanted into a semi-insulating GaAs substrate 1 (100), (accelerated type 75KoV2 x 10
Ion implantation for the active layer was performed at a dose of "■-2".

After that, an annealing method using a kip (800°C.

The implanted Si ions were activated for 15 minutes (in a N2 atmosphere) to form an active layer 2. After that, the first
Layers 5iN11!53 and 400o were deposited using a photolithography process to form source 4. A drain 5 electrode was formed. The lift-off method was used as the formation method. In addition, the electrode material is AuGe.
Ni-based material is used, and the alloy temperature is 400°C. after that,
A hole 66 was opened in a region that would become part of the gate electrode formation. This 66 is made by drilling holes in photoresist during the photolithography process and using this as a mask.

The first layer of S and LNa is removed by dry etching using CF4 gas.
It was formed by drilling holes and removing the resist. Next, as shown in FIG. 1(b), a 5iOt film 7, which will become a second layer insulating film, was deposited on the entire surface to a thickness of 2,000 mm using the pyrolytic CVD method. Next, as shown in FIG. 1(Q), an S x N film 8 is formed as a third layer insulating film.
2,000 people arrived. The deposition method was a plasma method. After that, as shown in FIG. 1(d), a photoresist film 9 is applied to the four parts.
left behind. Although a hoji-type photoresist material was used, a negative-type photoresist material can also be used. That is, after applying a positive resist 9 to a thickness of 2 μm over the entire surface and flattening it, the photoresist 9 is etched using oxygen gas or by active ion etching to expose the upper part of the third layer 8. Stop etching at that point. Note that if a portion of the CF4 gas is introduced, etching of 5iN8 occurs, and it becomes possible to monitor the etching stop by exposing the top of the SiN8 by spectroscopy. Thereafter, the third layer 5iN8 was plasma etched with CFa gas using the photoresist 9 left on the four parts as a mask to expose the upper part 5iOz 7 of the second layer.

After that, the photoresist 9 was removed and the next step started. As shown in FIG. 1(e), the source voltage 144 is
A hole is made on the side using a photolithography process, and the second layer S j,0
2. Film 7 was etched using a photoresist film as a mask. Buffered hydrofluoric acid was used as the etching solution. 5iOz
After exposing the active layer surface 2 by etching the film, the photoresist was removed. Next, as shown in FIG. 1(f), the gate metal 1 is
1 was formed. The metal used was Au/Mo, and the metal was coated on the entire surface to a thickness of 6000 mm. After that, a photoresist process was performed to leave a photoresist with a width of 1 μm, and using this photoresist film as a mask, ion milling was performed using Ar ions for Au.

The gate metal was processed by plasma etching using CF and gas to form a T-shaped gate metal 11 as shown in FIG. 1(f). Thereafter, holes were made in predetermined electrode portions to create a field effect transistor. Gate length is 0.18μ
It was finished in about m.

Example 2 Gate metal formation was performed using a lift-off method. in this case,
By using the gate photoresist film used in FIG. 1(f) as is, the number of photolithography steps can be reduced by one compared to the first embodiment. First, a photoresist film was applied to a thickness of 1.5 μm, a hole was made with a processing size of 1 μm, and then the SiO2 film 7 was etched using the photoresist film as a mask. The etching solution was the same as in the example. After that, AQ Gold Metal 5000 was applied with the photoresist and cyst film remaining.
AQ deposited on the photoresist film was removed together with the photoresist film using a photoresist and a remover to form a gate metal pattern 11. A sharp AQ gate metal pattern could be formed.

As described above, according to the present invention, the gate metal can be formed on a flat surface, a super-submicron pattern can be easily formed, and the characteristics can be significantly improved.

〔Effect of the invention〕

According to the present invention, the fine gate is determined by the thickness of the second insulating film, and can be manufactured stably with high precision compared to using light, electron beams, X-rays, etc. or lithography technology, and has a lower process margin. It is characterized by its large size. Furthermore, by using the third layer film, the gate metal pattern could be stably formed and disconnections could be significantly reduced. Along with this, it has become possible to form ultra-fine gate metals at high yields, and the performance of field effect transistors has also been improved by a factor of 8. In particular, this manufacturing method combines technologies that have been developed in the past, and also incorporates a new self-alignment method, so there are no particular problems with the technology and it is extremely stable.

The examples of this manufacturing method are described using GaAs as a representative, but Si
Needless to say, the present invention can be applied to compound semiconductor samples including InP-based compounds, and can be applied not only to junction field effect transistors including pn junctions, but also to MOS and MIS field effect transistors.

[Brief explanation of drawings]

FIG. 1 is a process diagram of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Active layer, 3... First layer film, 4
...Saw No./Figure

Claims (1)

[Claims] 1. A process of making a hole of a predetermined size in the first insulating film of the active layer in a field effect transistor having an ultra-fine patterned gate electrode by offsetting the gate and drain using two types of films. A step of depositing a second insulating film having different characteristics from the first insulating film to a thickness that determines the dimensions, a step of depositing a third insulating film near the thickness of the first insulating film, and a step of depositing a photoresist film in the recessed region. a step of removing the third layer insulating film to the second insulating film through the photoresist film;
1. A method for manufacturing a field effect transistor, comprising the step of forming a gate electrode in a portion in contact with an insulating film and the second insulating film, and forming a gate electrode by flattening an offset region between a gate and a drain.