JPH01500550A - Method of manufacturing self-aligned MESFET - Google Patents
Method of manufacturing self-aligned MESFETInfo
- Publication number
- JPH01500550A JPH01500550A JP62503800A JP50380087A JPH01500550A JP H01500550 A JPH01500550 A JP H01500550A JP 62503800 A JP62503800 A JP 62503800A JP 50380087 A JP50380087 A JP 50380087A JP H01500550 A JPH01500550 A JP H01500550A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- substitute
- substrate
- oxide
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 17
- 238000005468 ion implantation Methods 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910052785 arsenic Inorganic materials 0.000 claims description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 2
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 2
- 239000003779 heat-resistant material Substances 0.000 claims description 2
- 229910000476 molybdenum oxide Inorganic materials 0.000 claims description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- -1 oxynitride Chemical compound 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 5
- 238000001312 dry etching Methods 0.000 claims 2
- VLMNXWITUUMWCD-UHFFFAOYSA-M [O-2].[OH-].O.P.[In+3] Chemical compound [O-2].[OH-].O.P.[In+3] VLMNXWITUUMWCD-UHFFFAOYSA-M 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 108091008695 photoreceptors Proteins 0.000 claims 1
- 239000002699 waste material Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 241000894007 species Species 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910000413 arsenic oxide Inorganic materials 0.000 description 2
- 229960002594 arsenic trioxide Drugs 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000343219 Bironides Species 0.000 description 1
- 241000218645 Cedrus Species 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910001362 Ta alloys Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- IKWTVSLWAPBBKU-UHFFFAOYSA-N a1010_sial Chemical compound O=[As]O[As]=O IKWTVSLWAPBBKU-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KWLSQQRRSAWBOQ-UHFFFAOYSA-N dipotassioarsanylpotassium Chemical compound [K][As]([K])[K] KWLSQQRRSAWBOQ-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- JZLMRQMUNCKZTP-UHFFFAOYSA-N molybdenum tantalum Chemical compound [Mo].[Ta] JZLMRQMUNCKZTP-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910001392 phosphorus oxide Inorganic materials 0.000 description 1
- 239000011819 refractory material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/053—Field effect transistors fets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/139—Schottky barrier
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/14—Schottky barrier contacts
Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 自己整合性き１ＥｓＦＥＴの製造方法 攻４分互 本発明は、Ｍ Ｅ Ｓ Ｆ Ｅ Ｔのゲートを自己整合するための方法：こ開す る。[Detailed description of the invention] Manufacturing method of self-aligned 1EsFET Attack 4 divisions The present invention provides a method for self-aligning the gate of MEESFET: Ru.
１！技諸 自己整合技術’％１．従来のき１０ＳＦＥＴ技術で日常的に使われている。1! Techniques Self-alignment technology’%1. Conventional 10SFET technology is routinely used.
従来の技術は、シリコンゲート技術と呼ばれてきた。しかし、ｌ１ｌ−ｌ〜Ｖｉ 化合物の使用ｊよ、シリコン技術に伴うのと異なる問題をもたらす。例え：ｉ、 ＩＩＬ１〜８′ｙ：化合物半導体の製造におけるアニール工程は、元素の蒸発を 防くため一般にキャップを必要とする。カリウムひ素デバイスの製造では、ひ素 の蒸発を防ぎｔ才料物質のストイキオメトリ−（化学量論比）を一定に保つため に、キャップが一般に使われている。The conventional technology has been referred to as silicon gate technology. However, l1l-l~Vi The use of compounds poses different problems than those associated with silicon technology. Example: i, IIL1-8'y: The annealing process in the manufacture of compound semiconductors involves the evaporation of elements. generally requires a cap to prevent In the manufacture of potassium arsenide devices, arsenic To prevent evaporation of the substance and keep the stoichiometry (stoichiometric ratio) of the substance constant. Caps are commonly used.
自己整合技術の実施二二「ブしては、トランジスタがまずゲートメタルにまで製 造されろ。次いてイオン注入を行い、ソース及びトレイン用の高導電性領域を形 成する。このイオン注入工程で、ゲートが一部の領域をゲート注入から保護ずろ マスクとして機能する。従って、高導電性のソース及びドレイン領域がゲーＩ・ 領域の真下の領域まで延び、ソースとグー１−間の抵抗を減少させる。その後、 アニールキャップが付着され、注入したイオン種の活性化のためにサンプルがア ニールされる。アニールキャップの除去後、更に別の製造工程を施して半導体デ バイスか作製される。Implementation of self-alignment technology Be built. Ion implantation is then performed to form highly conductive regions for the source and train. to be accomplished. During this ion implantation process, the gate protects some areas from the gate implant. Acts as a mask. Therefore, the highly conductive source and drain regions are It extends to the region directly below the region to reduce the resistance between the source and the source. after that, An anneal cap is attached and the sample is annealed for activation of the implanted ionic species. Nealed. After removing the annealing cap, another manufacturing process is performed to A vise is made.
半導体デバイスの製造て；よ、ゲート長さの制御が極めて重要て５ろ。In the manufacture of semiconductor devices, controlling gate length is extremely important.
トランジスタの性能：、ｔゲートの長さによって強く影響さ７Ｌるので、回路の 性能はゲートの長さに依存する。半導体のゲート下方のチャネル長さは、わずか たけ長くするのが極めて望ましい。長過ぎるチャネルは、ゲ−１−てのブレーク ダウン電圧を減少させるからである。また、ゲートとチャネル間の漏れ電流を減 し・ろとともに、トルンとゲート間及びゲートとソース間のフィードバック（ミ ラー効果）容ｔを減じることも望ましい。Transistor performance: is strongly influenced by the length of the t-gate, so the circuit Performance depends on gate length. The channel length below the semiconductor gate is only It is highly desirable to make it very long. Channels that are too long will result in a game break. This is because the down voltage is reduced. It also reduces leakage current between the gate and channel. Along with the It is also desirable to reduce the volume t.
従来、基板のチャネル領域頂部の二酸化シリコン層の上ここダミーゲートが付着 さｚｌでいた。つまり、エツチング技術を用いて二酸化シリコン層の一部を除去 ずろ前に、アルミ層が二数（ヒシリコン層の上に（を着された。こうし・で得ら れたダミーゲートは、二酸化シリコン層がその上に付着されたアルミキャップを 有する構造である。次いて、チャネルをイオン注入から保護するマスクとしてア ルミキャップを用い、ウェハにイオン注入を施した。その後ダミーゲートをエツ チングし・、アルミマスクの下方にアンダーカッｌ−を形成し・た。このプロセ ス：こおいては、ダミーゲートの除去後あと：こ残ったスペース内にゲートメタ ルが付着されるので、最終的なゲーＩ・メタルの長さをチャネルの長さより短く てきる。Traditionally, a dummy gate is deposited on top of the silicon dioxide layer on top of the channel region of the substrate. I was in Sazzl. In other words, part of the silicon dioxide layer is removed using etching technology. Before long, two layers of aluminum (on top of the hissilicon layer) were deposited. The dummy gate consists of an aluminum cap with a silicon dioxide layer deposited on top of it. It has a structure that has It is then applied as a mask to protect the channel from ion implantation. Ion implantation was performed on the wafer using Lumicap. Then the dummy gate An undercut was formed under the aluminum mask. This process In this case, after removing the dummy gate, there is a gate metal in the remaining space. Since the metal is deposited, the final metal length should be shorter than the channel length. I'll come.
高温のアニールを行う前に、アルミキャップを引き剥しアニールキャップを施す ことによって、ガリウムび素デハイスニこおけるひ素のＴ発ＴＪ）防止される。Before performing high temperature annealing, peel off the aluminum cap and apply an annealing cap. This prevents the release of arsenic (TJ) in the gallium bironide dioxide film.
しかしこの方法では、アンダーカットの作業を充分制御できないので、ゲート長 さの一様性を確実に制御するのが不可能である。However, with this method, the undercut work cannot be controlled sufficiently, so the gate length It is impossible to reliably control the uniformity of the thickness.
更に、ゲート構造がでこぼこ状になるので、アルミの粒径が大きくなり過ぎサブ ミクロンのジェオメトリ；こは適さない。また、二酸化シリコンのアニールキャ ップを付着した後におけろアルミゲートマスクの除去：よ、化学的エツチングで 行うのが困難である。ゲートの長さがＦＥＴの性能に強く影響を及ぼすため、ゲ ートの長さを一貫して一様にてきなければ、回路の性能を制御するのは難し・い 。Furthermore, since the gate structure becomes uneven, the aluminum grain size becomes too large and the sub- Micron geometry; this is not suitable. Also, silicon dioxide annealing cap Removal of the aluminum gate mask after applying the mask: chemical etching Difficult to do. Gate length strongly affects FET performance, so It is difficult to control circuit performance unless the length of the circuit is consistently uniform. .
１９８５年８月６日伺けてＳｃｈｕｅｒｍｅｙｅｒに発行された米国特許第４． ５３２．Ｃｉ９５号、名称「自己整合性ＩＧＦＥＴの作製方法」によれば、窒化 シリコンの層と二酸化シリコンの層で被覆されたガリウムひ素のウェハ上にＩＣ ＦＥＴが形成される。トランジスタ領域の二酸化シリコンがエッチ除去され、イ オン注入がチャネル用ドーピングを与える。モリブデンなど耐熱メタルのゲート が付着され、輪郭形成される。このゲートと二酸化シリコンが、ソース及びドレ インのイオン注入用マスクとして機能する。US Pat. No. 4, issued to Schuermeyer on August 6, 1985. 532. According to Ci95, titled "Method for fabricating self-aligned IGFET", nitriding ICs on a gallium arsenide wafer coated with a layer of silicon and a layer of silicon dioxide A FET is formed. The silicon dioxide in the transistor area is etched away and the The on-implant provides doping for the channel. Gate made of heat-resistant metal such as molybdenum is applied and contoured. This gate and silicon dioxide are connected to the source and drain. Functions as a mask for ion implantation.
ゲートの長さを制御するのに、ダミ一つまり代用ゲートは一切使われない。No dummy or surrogate gates are used to control gate length.
１９８４年９月２５日付けてＴｏｙｏｄａ他に発行された米国特許第４，４７２ ，８７２号、名称「ショットキーゲート電界効果トランジスタの作製方法」によ れば、半導体基板上；こ相互に対面したＭｌ及び第２のスタックを形成すること によってショットキーゲートＦＥＴが製造されろ。各スタックは、オーミック電 極とスペーサフィルムとて構成されている。両スタックがその上に形成された基 板上に、絶縁層が形成され、ブレーナ表面部が露出されるまで、その厚さ方向に 沿って非等方的にエツチングされる。この結果、絶縁層の一部が両スタックの対 向側壁上に残る。スペーサフィルムを除去して各残部と各電極の開に段状部を画 成した後、基板と共にショットキーバリヤを形成可能なメタル材料の層が形成さ れる。次いて残部を除去し、メタル材料の層をパターン化することによって、シ ョットキーゲート電極を形成する。U.S. Patent No. 4,472 issued September 25, 1984 to Toyoda et al. , No. 872, entitled "Method for manufacturing Schottky gate field effect transistor". If so, on the semiconductor substrate; forming Ml and a second stack facing each other; A Schottky gate FET is manufactured by Each stack has an ohmic It consists of poles and a spacer film. Both stacks have a base formed on top of them. An insulating layer is formed on the board in the thickness direction until the brainer surface is exposed. etched anisotropically along the As a result, part of the insulating layer is It remains on the opposite wall. Remove the spacer film and define a step in the opening of each remaining and each electrode. After that, a layer of metal material is formed that can form a Schottky barrier with the substrate. It will be done. The remainder is then removed and the layer of metal material is patterned. Form a Schottky gate electrode.
且匪少皿不 本発明は、半導体デバイスを作製するための改良された方法を提供する。つまり 本発明は、イオン注入工程の間にチャネル領域をマスクする側壁構造を持つ代用 ゲートを用いた方法を提供する。且匪小板ふ The present invention provides an improved method for making semiconductor devices. In other words The present invention provides an alternative method with sidewall structures to mask the channel region during the ion implantation process. A method using gates is provided.
本方法は、支持基板の表面上に絶縁材料の層を付着することを備える。The method comprises depositing a layer of insulating material on a surface of a support substrate.
基板は、所望な導電型のキャリヤ濃度を持つ表面の下方にチャネル領域を含む。The substrate includes a channel region below the surface having a carrier concentration of the desired conductivity type.
絶縁材料の選択部分を除去し、基板表面上に代用ゲートを形成する。代用ゲート と結合する側壁が形成され、代用ゲートと協働する有効マスク領域を限定する。Selected portions of the insulating material are removed and a substitute gate is formed on the substrate surface. substitute gate Sidewalls are formed that interface with the surrogate gate to define an effective mask area that cooperates with the surrogate gate.
マスクされていない領域上にイオン注入し、基板の非マスク領域内にドーパント を打ち込んで、所望の領域にｎｏのチャネルドーピングを与える。側壁を除去し 、得られたデバイスをアニールし・て基板内のドーパントを活性化する。代用ゲ ートを除去し、ゲート除去後に残ったスペース内にゲートメタルを付着して、ゲ ートの長さを制御する。メタルゲートの長さは代用ゲートと同じである一方、チ ャネルの長さは代用ゲートと側壁の和と同じである。チャネルの長さをゲートの 長さより長くするのが、非常に望ましい。Ion implantation over unmasked areas and dopants into unmasked areas of the substrate implant to provide no channel doping in the desired region. remove side wall , the resulting device is annealed to activate the dopants in the substrate. Substitute game Gate metal is removed and gate metal is deposited in the space left after gate removal. control the length of the route. The length of the metal gate is the same as the substitute gate, while the length of the metal gate is the same as the substitute gate. The length of the channel is equal to the sum of the surrogate gate and sidewall. Gate length of channel It is highly desirable to make it longer than the length.
第１及び第２のオーミック接点が相互に正しい位置間係で基板上に付着され、相 互接続メタルがオーミック接点と電気導通されて付着され、半導体デバイスを作 製する。The first and second ohmic contacts are deposited on the substrate in the correct positional relation to each other, and Interconnect metals are deposited in electrical continuity with ohmic contacts to create semiconductor devices. make
支持基板は半絶縁性のガリウムひ素を含むのが好ましいが、その他の１１ｉ１〜 族化合物またはシリコンともし得る。絶縁材料は二酸化シリコンとし・得るが、 側壁は窒化シリコン、ポリマーまたはフォトレジスタでも形成できる。ｎ型つま りｎｏ、−型注入種がイオン注入される間、ゲートと側壁がマスクとして機能し 、それらのマスクしている領域直下へのイオン注入を防ぐ。側壁の除去は、ドラ イエツチングまたは反応性イオンエツチングによってなされる。本方法を完全な ものとするため、超過圧ポリマーやフォトレジスト等のブレーナ化材料が、基板 表面と代用ゲート上に共形の層として施され、代用ゲートを露出するようにエッ チバックされた後、緩衝フッ化水素酸を施すことによって代用ゲートが除去され る。ブレーナ１ヒ（３料が、ブレーナ化材料構造の頂部、該構造の底部及び基板 の表面間に、代用ゲートの輪郭に従って所望の角度を形成する。The supporting substrate preferably contains semi-insulating gallium arsenide, but other 11i1- It can also be a group compound or silicon. The insulating material can be silicon dioxide, The sidewalls can also be formed of silicon nitride, polymer or photoresistor. n type toe The gate and sidewalls act as a mask while the -type implant species are implanted. , to prevent ion implantation directly under those masked regions. Removal of side walls is done by This is done by etching or reactive ion etching. This method is complete To achieve this, brainerized materials such as overpressure polymers and photoresists are It is applied as a conformal layer over the surface and the surrogate gate and is etched to expose the surrogate gate. After being tested back, the surrogate gate is removed by applying buffered hydrofluoric acid. Ru. Brainer 1 (3 materials are the top of the brainerized material structure, the bottom of the structure and the substrate) form the desired angle between the surfaces according to the contour of the surrogate gate.
このアンダーカットが、代用ゲートの除去によって開いた領域内に付着されるゲ ートメタルの一定形状を限定する。本方法の残りの工程は、半導体デバイスの製 造分野で標準的なものである。This undercut is the area where the surrogate gate is removed. Limits the shape of the base metal. The remaining steps in the method include manufacturing semiconductor devices. This is standard in the construction field.
本発明のその他の利点及び特徴は、以下の説明から明かとなろう。Other advantages and features of the invention will become apparent from the description below.
図□面ｍ次皿 以下本発明を更に詳し・く説明し・、新規と考える特許請求の範囲の項に詳細に 記述する。本発明は、下記の添付図面を萼照することによって最も明瞭に理解さ れよう： 第１図は本発明二二従って作製された電界効果トランジスタの側断面図；及び 第２図は本発明の７〜ＩＥＳＦＥＴの製造における代表的な工程を示す。Figure □ Surface m-order plate The present invention will be described in more detail below, and the claims, which are considered novel, will be described in more detail. Describe. The invention is best understood by referring to the accompanying drawings below. Let's try: FIG. 1 is a side sectional view of a field effect transistor manufactured according to the present invention; and FIG. 2 shows typical steps in manufacturing the 7-IESFET of the present invention.
几肌亙ス＃ＬｔＪＩ汝虫五１Ω彫店 第１図を参！ｌＺすると、本発明によって作製された電界効果トランジスタ１０ が示しである。図示のごとく、トランジスタｌＯは、半絶縁性のガリウムひ素、 シリコン、インジウムリん等の合成物、あるいはガラス、単結晶シリコン、マイ ラー、ステンレス鋼なと別の基板の頂面上に施した上記のうち任意の膜からなる 半導体材料の基板１２上に形成されている。基板１２は表面１４を有し、該表面 の下方に、ｎ、ｎ”、ｎ−１ｐまたはｐ十等所望な導電型のキャリヤ濃度を含ん だチャネル領域１６を含んでいる。#LtJI Gomushigo 1Ω carving shop See Figure 1! lZ Then, the field effect transistor 10 manufactured according to the present invention is the indication. As shown in the figure, the transistor IO is made of semi-insulating gallium arsenide, Synthetic materials such as silicon and indium phosphide, or glass, single crystal silicon, and consisting of any of the above films applied on the top surface of another substrate such as steel or stainless steel. It is formed on a substrate 12 of semiconductor material. Substrate 12 has a surface 14, the surface below the carrier concentration of the desired conductivity type, such as n, n'', n-1p or p10. It includes a channel region 16.
基Ｆｉ１２上にゲート２２が付着され、チャネルの＃４１８からゲートまでの分 離］６を大きくすることでゲートにおけるブレークダウン電圧を減じるように、 ゲート２２は制御された寸法のゲート長さを有する。ゲート２２は基板１２との 境界面に近接してチャネル領域Ｊ６を形成じ、トランジスタｌＯで比較的高い相 互コンダクタンスを達成可能とするように作用する。基板１２の頂部：こ、トレ イン２４とソース２６が位置する。A gate 22 is attached on the base Fi12, and a portion from #418 of the channel to the gate is attached. In order to reduce the breakdown voltage at the gate by increasing the separation]6, Gate 22 has a gate length of controlled dimensions. The gate 22 is connected to the substrate 12. A channel region J6 is formed close to the interface, and a relatively high phase in the transistor IO is formed. It acts to make it possible to achieve mutual conductance. Top of board 12: Inn 24 and source 26 are located.
代用ゲートに用いる絶縁材料は二酸化シリコンまたはフォトレジストが望ましい が、窒化アルミ、酸化アルミ、酸化タンタル、酸化チタン、酸化タングステン、 酸化ガリウム、酸化ひ素、酸化モリブデン、酸窒化物、酸化ガリウムひ素、酸化 アルミガリウムひ素、酸化インジウムガリウムひ素りん、及び酸化インジウムリ んから成る群の中から選ばれた合成物ともし得る。The insulating material used for the substitute gate is preferably silicon dioxide or photoresist. However, aluminum nitride, aluminum oxide, tantalum oxide, titanium oxide, tungsten oxide, Gallium oxide, arsenic oxide, molybdenum oxide, oxynitride, gallium arsenic oxide, oxide Aluminum gallium arsenide, indium gallium arsenide phosphorus, and indium oxide It can also be a compound selected from the group consisting of:
ゲート２２：よ一般に、プラチナや金等の耐熱を１料からなる多層構造で形成さ れている。ゲート２２は基板１２の頂部に直接付着される。また基板１２上に、 ドレイン電極として機能するオーミック材料のドしイン２４が付着されている。Gate 22: Generally, a multilayer structure made of a single heat-resistant material such as platinum or gold. It is. Gate 22 is attached directly to the top of substrate 12. Moreover, on the substrate 12, A doin 24 of ohmic material is deposited to serve as a drain electrode.
同じくオーミック（才料からなるソース２６が、ゲート２２に対してドレイン２ ４と反対側に基板１２上に付着されている。ドレイン２４とソース２６は、アル ミ、モリブデンまたはモリブデン・タンタル合金、クロム、チタン、タングステ ン、パラジウム及びプラチナ等任曾の適切なオーミック材料で形成し得る。好ま しくは、オーミック材料は金−ゲルマニウムである。またドレイン２４とソース ２６は、所望な導電型、好ましくはｎｏのキャリヤ導電性を有するイオン注入領 域を含む。ドレイン２４とソース２６は共に、ゲート２２に対して自己整合され る。メタル相互接続体２８がトレイン２４とソース２６両方の頂部上に付着され 、トランジスタにおける電流導通路用の電電接続として機能する。Similarly, the source 26, which is made of ohmic material, is connected to the drain 2 with respect to the gate 22. 4 and is attached on the substrate 12 on the opposite side. The drain 24 and source 26 are aluminum, molybdenum or molybdenum-tantalum alloy, chromium, titanium, tungsten It may be formed of any suitable ohmic material, such as copper, palladium, and platinum. Like Alternatively, the ohmic material is gold-germanium. Also drain 24 and source 26 is an ion implantation region having carrier conductivity of the desired conductivity type, preferably no. Including area. Both drain 24 and source 26 are self-aligned to gate 22. Ru. A metal interconnect 28 is deposited on top of both train 24 and source 26. , which serves as the electrical connection for the current conducting path in the transistor.
次に第２図を参照すると、本発明の方法の代表的な工程が示しである。Referring now to FIG. 2, representative steps of the method of the present invention are illustrated.
基板の表面下方の領域がイオン注入され、所望な導電型のキャリヤ濃度を含むチ ャネルを形成した後、約８００〜８５０℃の高温で７ニールされ、イオン注入領 域を活性化する。次いて、絶縁体の層が基板上に付着され、選択的にエッチ除去 されて残った層が代用ゲートどなる。代用ゲート絶縁材！４の被着；よ、任意の 標準的な付着技術で行える。Regions below the surface of the substrate are ion-implanted and filled with a chip containing a carrier concentration of the desired conductivity type. After forming the channel, it is annealed at a high temperature of about 800-850℃ for 7 hours to form the ion implantation area. Activate the area. A layer of insulator is then deposited onto the substrate and selectively etched away. The remaining layer is used as a substitute gate. Substitute gate insulation material! Adhesion of 4; yo, any Can be done using standard deposition techniques.
代用ゲートを形成した後、二酸化シリコン、窒化シリコン、ポリマー及びフォト レジストから成る群の中から選び得る誘電性材料なとの共形側壁Ｎを、基板全体 及び代用ゲート上に付着することによって側壁が代用ゲート上に形成される。吹 いて、トライエツチングを行い側壁を形成する。側壁材料は代用ゲート材料より はるかに速く、すなわち２０−１程度のエツチング速度て選択的にエッチ除去さ れるため、反応性イオンエツチングを優先的に用いるのが好ましい。反応性イオ ンエツチングの方法は、側壁の厚さを約０，０５〜０，３ミクロン、好ましくは １５００〜２０００オングストロームの厚さに減少させる。側壁の厚さが、ゲー トとチャネルの両端との間の距離を決める。After forming the substitute gate, silicon dioxide, silicon nitride, polymer and photo A conformal sidewall N of a dielectric material selected from the group consisting of resist and sidewalls are formed on the surrogate gate by depositing on the surrogate gate. Squirting Then, try etching is performed to form the side wall. Side wall material is from substitute gate material Selective etch removal is much faster, i.e., on the order of 20-1. Therefore, it is preferable to preferentially use reactive ion etching. reactive io The method of etching reduces the thickness of the sidewalls to approximately 0.05 to 0.3 microns, preferably Reduce thickness to 1500-2000 angstroms. The side wall thickness is Determine the distance between the port and the ends of the channel.
側壁の形成後、ｎ゛型の注人種をイオン注入することによってイオン注入が行わ れ、この間代用ゲートと側壁が代用ゲートの直下及び直近へのイオン注入を防ぐ マスクを与える。このイオン注入のプロセスが、不規則に広がるｎ゛領域側壁構 造下方の領域へとわずかに侵食して形成し、代用ゲートの長さより長いチャネル 長さを与える。After forming the sidewalls, ion implantation is performed by implanting n-type implanters. The substitute gate and sidewalls prevent ion implantation directly below and in the immediate vicinity of the substitute gate. Give a mask. This ion implantation process creates an irregularly spread n-region sidewall structure. A channel formed by slight erosion into the area below the structure and longer than the length of the surrogate gate. give length.
イオン注入後、トライエツチング好ましくは反応性イオンエツチングまたはプラ ズマエツチングによって側壁の除去を行い、代用ゲートを残す。After ion implantation, try etching, preferably reactive ion etching or plastic The side wall is removed by Zuma etching, leaving a substitute gate.
基板内からの蒸発を防ぐためキャップで構造全体を被覆する代わりに、構造を高 温で超過圧力のひ素環境内においてキャップレスのアニールを行う。このアニー ルは、約０．０１０〜約０．１０大気圧のひ素の超過圧力下で、約７５０〜１２ ００℃においてなされろ。またアニールは少なくともひ素を含む複合気体の環境 内で、約１０秒〜６０分間行うこともてきる。アニールは約２０分間行うのが好 ましい。アニール後、ポリマーとフォトレジストからなる群の中から選ばれたブ レーナ化材料が、基板表面と代用ゲート上二二共彩りとして悔される。このブレ ーナ化材料がエッチバックされ、代用ゲートを露出させろ。代用ゲートが露出さ れたら、緩衝フッ化水素酸を構造：こ施して、代用ゲートを除去する。これによ り、構造の頂部、構造の底部及び基板の表面間に所望の角度を有するブレ−ナ化 材料の構造が形成される。次いてアンダーカットを行い、約７５６〜９０゜好ま しくは８０°〜８５°の間の角度を形成ずろ。ゲートメタルは代用ゲートの後に 残ったスペース内に付着され、アンプ・−カットされたブレーナ化材料の形しこ 従うので、上記のアンダーカットは代用メタルの除去を容易にすると共に、後で 付着されるゲート材料の形状を限定する。ゲート材料の付着は、プラチナや金な と耐熱材料を含む多Ｎ構造の、基板の表面全体と共形の付着によって行われる。Instead of covering the entire structure with a cap to prevent evaporation from within the substrate, Capless annealing is performed in an overpressure arsenic environment at high temperatures. this annie under an overpressure of about 0.010 to about 0.10 atmospheres of arsenic, about 750 to 12 Be done at 00°C. Also, annealing is performed in an environment of a complex gas containing at least arsenic. It can be done for about 10 seconds to 60 minutes. It is preferable to anneal for about 20 minutes. Delicious. After annealing, a block selected from the group consisting of polymer and photoresist is Unfortunately, the rayonization material stains both the substrate surface and the substitute gate. This blur The dielectric material is etched back to expose the substitute gate. Substitute gate exposed Once completed, apply buffered hydrofluoric acid to remove the surrogate gate. This is it The planarization has a desired angle between the top of the structure, the bottom of the structure, and the surface of the substrate. A structure of material is formed. Next, make an undercut, preferably about 756 to 90 degrees. or form an angle between 80° and 85°. Gate metal after substitute gate A shape of amp-cut brainerized material is deposited and cut into the remaining space. Therefore, the undercut above facilitates the removal of the substitute metal and later Limit the shape of the gate material deposited. Adhesion of gate material is limited to platinum or gold. and a refractory material, conformal to the entire surface of the substrate.
その後ブレーナ化材料が、その上に付着されたゲート材料と一緒に引き剥され、 基板の頂部に付着されているゲートメタルだけを残す。次いてオーミック接点が 、代用ゲートによってマスクさ１１ずに残された領域上に付着される。そして相 互接続メタルがオーミンク接点上に付着され、トランジスタを流れる電気の導通 路を与える。更に追加の通常技術が施され、半導体デバイスＩ＼組み込むための トランジスタを完成する。The brainerized material is then peeled off along with the gate material deposited thereon; Leave only the gate metal attached to the top of the substrate. Next is the ohmic contact , is deposited on the area left unmasked by the substitute gate. And phase An interconnect metal is deposited on the ohmink contact to conduct electricity through the transistor. give a way Additionally, additional conventional techniques are applied to incorporate the semiconductor device I\. Complete the transistor.
以上発明を実施するための最良の杉態イ詳しく説明したが、この発明の関連分野 の当業者であれば、以下の請求の範囲によって限定される発明の実施に際して各 種の代替法及び実施例を考えることができよう。Although the best cedar condition for carrying out the invention has been explained in detail above, fields related to this invention A person skilled in the art will be able to carry out the invention as limited by the scope of the following claims. Alternative species and embodiments could be considered.
浄書（内容に変更なし） 浄Ｈ（内容に変更なし）。Engraving (no changes to the content) Clean H (no change in content).
特許庁長官 吉 １）文 毅 殿 １、事件の表示 ＰＣＴ／ＵＳ ８７１０１３５４２、発明の名称 自己整合性 ＭＥＳＦＥＴの製造方法３、補正をする者 事件との関係 出願人 国際調査報告Yoshi, Commissioner of the Patent Office 1) Takeshi Moon 1. Indication of case PCT/US 871013542, title of invention Self-consistency MESFET manufacturing method 3, person who makes the correction Relationship to the case: Applicant international search report
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US873,515 | 1986-06-12 | ||
| US06/873,515 US4745082A (en) | 1986-06-12 | 1986-06-12 | Method of making a self-aligned MESFET using a substitutional gate with side walls |
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| JPH01500550A true JPH01500550A (en) | 1989-02-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62503800A Pending JPH01500550A (en) | 1986-06-12 | 1987-06-10 | Method of manufacturing self-aligned MESFET |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4745082A (en) |
| JP (1) | JPH01500550A (en) |
| CA (1) | CA1276315C (en) |
| DE (1) | DE3790294T1 (en) |
| GB (1) | GB2199445B (en) |
| WO (1) | WO1987007765A1 (en) |
Families Citing this family (78)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4859618A (en) * | 1986-11-20 | 1989-08-22 | Sumitomo Electric Industries, Ltd. | Method of producing the gate electrode of a field effect transistor |
| JPS63276267A (en) * | 1987-05-08 | 1988-11-14 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5093280A (en) * | 1987-10-13 | 1992-03-03 | Northrop Corporation | Refractory metal ohmic contacts and method |
| JPH0787195B2 (en) * | 1987-10-22 | 1995-09-20 | 三菱電機株式会社 | Method of manufacturing Schottky gate field effect transistor |
| US4863879A (en) * | 1987-12-16 | 1989-09-05 | Ford Microelectronics, Inc. | Method of manufacturing self-aligned GaAs MESFET |
| JP2685149B2 (en) * | 1988-04-11 | 1997-12-03 | 住友電気工業株式会社 | Method for manufacturing field effect transistor |
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| US5374574A (en) * | 1993-11-23 | 1994-12-20 | Goldstar Electron Co., Ltd. | Method for the fabrication of transistor |
| US5374575A (en) * | 1993-11-23 | 1994-12-20 | Goldstar Electron Co., Ltd. | Method for fabricating MOS transistor |
| US6057219A (en) * | 1994-07-01 | 2000-05-02 | Motorola, Inc. | Method of forming an ohmic contact to a III-V semiconductor material |
| US5504039A (en) * | 1994-07-29 | 1996-04-02 | Motorola, Inc. | Method for making a self-aligned oxide gate cap |
| US5447874A (en) * | 1994-07-29 | 1995-09-05 | Grivna; Gordon | Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish |
| US5733806A (en) * | 1995-09-05 | 1998-03-31 | Motorola, Inc. | Method for forming a self-aligned semiconductor device |
| JP2870485B2 (en) * | 1996-06-03 | 1999-03-17 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US6030453A (en) * | 1997-03-04 | 2000-02-29 | Motorola, Inc. | III-V epitaxial wafer production |
| US6051486A (en) * | 1997-12-18 | 2000-04-18 | Advanced Miero Devices | Method and structure for replaceable gate electrode in insulated gate field effect transistors |
| US6297115B1 (en) | 1998-11-06 | 2001-10-02 | Advanced Micro Devices, Inc. | Cmos processs with low thermal budget |
| US5985726A (en) * | 1998-11-06 | 1999-11-16 | Advanced Micro Devices, Inc. | Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET |
| US6225173B1 (en) | 1998-11-06 | 2001-05-01 | Advanced Micro Devices, Inc. | Recessed channel structure for manufacturing shallow source/drain extensions |
| US6200869B1 (en) | 1998-11-06 | 2001-03-13 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions |
| US6265291B1 (en) | 1999-01-04 | 2001-07-24 | Advanced Micro Devices, Inc. | Circuit fabrication method which optimizes source/drain contact resistance |
| US6184097B1 (en) | 1999-02-22 | 2001-02-06 | Advanced Micro Devices, Inc. | Process for forming ultra-shallow source/drain extensions |
| US6271095B1 (en) | 1999-02-22 | 2001-08-07 | Advanced Micro Devices, Inc. | Locally confined deep pocket process for ULSI mosfets |
| US6225176B1 (en) | 1999-02-22 | 2001-05-01 | Advanced Micro Devices, Inc. | Step drain and source junction formation |
| US6492249B2 (en) | 1999-05-03 | 2002-12-10 | Advanced Micro Devices, Inc. | High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric |
| US6271132B1 (en) | 1999-05-03 | 2001-08-07 | Advanced Micro Devices, Inc. | Self-aligned source and drain extensions fabricated in a damascene contact and gate process |
| US6291278B1 (en) | 1999-05-03 | 2001-09-18 | Advanced Micro Devices, Inc. | Method of forming transistors with self aligned damascene gate contact |
| US6194748B1 (en) | 1999-05-03 | 2001-02-27 | Advanced Micro Devices, Inc. | MOSFET with suppressed gate-edge fringing field effect |
| US6265293B1 (en) | 1999-08-27 | 2001-07-24 | Advanced Micro Devices, Inc. | CMOS transistors fabricated in optimized RTA scheme |
| US6033963A (en) * | 1999-08-30 | 2000-03-07 | Taiwan Semiconductor Manufacturing Company | Method of forming a metal gate for CMOS devices using a replacement gate process |
| JP2001077108A (en) * | 1999-08-31 | 2001-03-23 | Nec Corp | Semiconductor device and manufacture of composite oxide thin film |
| US6391801B1 (en) | 1999-09-01 | 2002-05-21 | Micron Technology, Inc. | Method of forming a layer comprising tungsten oxide |
| US6403433B1 (en) | 1999-09-16 | 2002-06-11 | Advanced Micro Devices, Inc. | Source/drain doping technique for ultra-thin-body SOI MOS transistors |
| US6248637B1 (en) | 1999-09-24 | 2001-06-19 | Advanced Micro Devices, Inc. | Process for manufacturing MOS Transistors having elevated source and drain regions |
| US6579784B1 (en) | 1999-10-18 | 2003-06-17 | Taiwan Semiconductor Manufacturing Company | Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers |
| US6333244B1 (en) | 2000-01-26 | 2001-12-25 | Advanced Micro Devices, Inc. | CMOS fabrication process with differential rapid thermal anneal scheme |
| US6372589B1 (en) | 2000-04-19 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer |
| US6420218B1 (en) | 2000-04-24 | 2002-07-16 | Advanced Micro Devices, Inc. | Ultra-thin-body SOI MOS transistors having recessed source and drain regions |
| US6670651B1 (en) | 2000-05-04 | 2003-12-30 | Osemi, Inc. | Metal sulfide-oxide semiconductor transistor devices |
| US6936900B1 (en) * | 2000-05-04 | 2005-08-30 | Osemi, Inc. | Integrated transistor devices |
| US6445015B1 (en) | 2000-05-04 | 2002-09-03 | Osemi, Incorporated | Metal sulfide semiconductor transistor devices |
| US6451711B1 (en) * | 2000-05-04 | 2002-09-17 | Osemi, Incorporated | Epitaxial wafer apparatus |
| US6361874B1 (en) | 2000-06-20 | 2002-03-26 | Advanced Micro Devices, Inc. | Dual amorphization process optimized to reduce gate line over-melt |
| US6368947B1 (en) | 2000-06-20 | 2002-04-09 | Advanced Micro Devices, Inc. | Process utilizing a cap layer optimized to reduce gate line over-melt |
| US6399450B1 (en) | 2000-07-05 | 2002-06-04 | Advanced Micro Devices, Inc. | Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions |
| US6630386B1 (en) | 2000-07-18 | 2003-10-07 | Advanced Micro Devices, Inc | CMOS manufacturing process with self-amorphized source/drain junctions and extensions |
| US6521502B1 (en) | 2000-08-07 | 2003-02-18 | Advanced Micro Devices, Inc. | Solid phase epitaxy activation process for source/drain junction extensions and halo regions |
| US6472282B1 (en) | 2000-08-15 | 2002-10-29 | Advanced Micro Devices, Inc. | Self-amorphized regions for transistors |
| US6300203B1 (en) | 2000-10-05 | 2001-10-09 | Advanced Micro Devices, Inc. | Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
| US6559051B1 (en) | 2000-10-05 | 2003-05-06 | Advanced Micro Devices, Inc. | Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
| US6465334B1 (en) | 2000-10-05 | 2002-10-15 | Advanced Micro Devices, Inc. | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
| US6406950B1 (en) * | 2000-12-07 | 2002-06-18 | Advanced Micro Devices, Inc. | Definition of small damascene metal gates using reverse through approach |
| US6518113B1 (en) | 2001-02-06 | 2003-02-11 | Advanced Micro Devices, Inc. | Doping of thin amorphous silicon work function control layers of MOS gate electrodes |
| US6787424B1 (en) | 2001-02-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Fully depleted SOI transistor with elevated source and drain |
| US6403434B1 (en) | 2001-02-09 | 2002-06-11 | Advanced Micro Devices, Inc. | Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric |
| US6756277B1 (en) | 2001-02-09 | 2004-06-29 | Advanced Micro Devices, Inc. | Replacement gate process for transistors having elevated source and drain regions |
| US6495437B1 (en) | 2001-02-09 | 2002-12-17 | Advanced Micro Devices, Inc. | Low temperature process to locally form high-k gate dielectrics |
| US6551885B1 (en) | 2001-02-09 | 2003-04-22 | Advanced Micro Devices, Inc. | Low temperature process for a thin film transistor |
| US6509253B1 (en) | 2001-02-16 | 2003-01-21 | Advanced Micro Devices, Inc. | T-shaped gate electrode for reduced resistance |
| US6420776B1 (en) | 2001-03-01 | 2002-07-16 | Amkor Technology, Inc. | Structure including electronic components singulated using laser cutting |
| US20020132395A1 (en) * | 2001-03-16 | 2002-09-19 | International Business Machines Corporation | Body contact in SOI devices by electrically weakening the oxide under the body |
| US6989556B2 (en) * | 2002-06-06 | 2006-01-24 | Osemi, Inc. | Metal oxide compound semiconductor integrated transistor devices with a gate insulator structure |
| US7067439B2 (en) | 2002-06-14 | 2006-06-27 | Applied Materials, Inc. | ALD metal oxide deposition process using direct oxidation |
| US7187045B2 (en) * | 2002-07-16 | 2007-03-06 | Osemi, Inc. | Junction field effect metal oxide compound semiconductor integrated transistor devices |
| US6905923B1 (en) | 2003-07-15 | 2005-06-14 | Advanced Micro Devices, Inc. | Offset spacer process for forming N-type transistors |
| WO2005048318A2 (en) * | 2003-11-17 | 2005-05-26 | Osemi, Inc. | Nitride metal oxide semiconductor integrated transistor devices |
| US20080282983A1 (en) * | 2003-12-09 | 2008-11-20 | Braddock Iv Walter David | High Temperature Vacuum Evaporation Apparatus |
| US7312125B1 (en) | 2004-02-05 | 2007-12-25 | Advanced Micro Devices, Inc. | Fully depleted strained semiconductor on insulator transistor and method of making the same |
| US8119210B2 (en) | 2004-05-21 | 2012-02-21 | Applied Materials, Inc. | Formation of a silicon oxynitride layer on a high-k dielectric material |
| US7195999B2 (en) * | 2005-07-07 | 2007-03-27 | Micron Technology, Inc. | Metal-substituted transistor gates |
| US20070045752A1 (en) * | 2005-08-31 | 2007-03-01 | Leonard Forbes | Self aligned metal gates on high-K dielectrics |
| US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
| US7645710B2 (en) | 2006-03-09 | 2010-01-12 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
| US7678710B2 (en) * | 2006-03-09 | 2010-03-16 | Applied Materials, Inc. | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system |
| US7837838B2 (en) | 2006-03-09 | 2010-11-23 | Applied Materials, Inc. | Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus |
| JP5590886B2 (en) | 2006-09-26 | 2014-09-17 | アプライド マテリアルズ インコーポレイテッド | Fluorine plasma treatment for high-K gate stacks for defect passivation |
| US20080157073A1 (en) * | 2006-12-29 | 2008-07-03 | Walter David Braddock | Integrated Transistor Devices |
| US8383471B1 (en) | 2011-04-11 | 2013-02-26 | Hrl Laboratories, Llc | Self aligned sidewall gate GaN HEMT |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5896769A (en) * | 1981-12-04 | 1983-06-08 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS6177365A (en) * | 1984-09-21 | 1986-04-19 | Nec Corp | Manufacture of semiconductor device |
| JPS61163662A (en) * | 1985-01-14 | 1986-07-24 | Agency Of Ind Science & Technol | Manufacture of field-effect transistor |
| JPS61222177A (en) * | 1985-03-27 | 1986-10-02 | Sumitomo Electric Ind Ltd | Schottky gate field effect transistor and manufacture thereof |
| JPS629676A (en) * | 1985-07-05 | 1987-01-17 | Nec Corp | Manufacture of semiconductor device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55153377A (en) * | 1979-05-18 | 1980-11-29 | Matsushita Electronics Corp | Production of semiconductor device |
| JPS55163860A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58130575A (en) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | Manufacture of field effect transistor |
| US4561169A (en) * | 1982-07-30 | 1985-12-31 | Hitachi, Ltd. | Method of manufacturing semiconductor device utilizing multilayer mask |
| JPS5950567A (en) * | 1982-09-16 | 1984-03-23 | Hitachi Ltd | Manufacture of field effect transistor |
| US4505023A (en) * | 1982-09-29 | 1985-03-19 | The United States Of America As Represented By The Secretary Of The Navy | Method of making a planar INP insulated gate field transistor by a virtual self-aligned process |
| JPS59229876A (en) * | 1983-06-13 | 1984-12-24 | Toshiba Corp | Manufacture of schottky gate type field effect transistor |
| JPS6032364A (en) * | 1983-08-01 | 1985-02-19 | Toshiba Corp | Manufacture of semiconductor device |
| US4659119A (en) * | 1983-12-29 | 1987-04-21 | Dril-Quip, Inc. | Latching connector |
-
1986
- 1986-06-12 US US06/873,515 patent/US4745082A/en not_active Expired - Fee Related
-
1987
- 1987-06-10 WO PCT/US1987/001354 patent/WO1987007765A1/en active Application Filing
- 1987-06-10 DE DE19873790294 patent/DE3790294T1/de not_active Withdrawn
- 1987-06-10 GB GB8802340A patent/GB2199445B/en not_active Expired
- 1987-06-10 JP JP62503800A patent/JPH01500550A/en active Pending
- 1987-06-11 CA CA000539413A patent/CA1276315C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5896769A (en) * | 1981-12-04 | 1983-06-08 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPS6177365A (en) * | 1984-09-21 | 1986-04-19 | Nec Corp | Manufacture of semiconductor device |
| JPS61163662A (en) * | 1985-01-14 | 1986-07-24 | Agency Of Ind Science & Technol | Manufacture of field-effect transistor |
| JPS61222177A (en) * | 1985-03-27 | 1986-10-02 | Sumitomo Electric Ind Ltd | Schottky gate field effect transistor and manufacture thereof |
| JPS629676A (en) * | 1985-07-05 | 1987-01-17 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| US4745082A (en) | 1988-05-17 |
| GB8802340D0 (en) | 1988-03-02 |
| DE3790294T1 (en) | 1989-01-19 |
| WO1987007765A1 (en) | 1987-12-17 |
| GB2199445B (en) | 1990-04-04 |
| CA1276315C (en) | 1990-11-13 |
| GB2199445A (en) | 1988-07-06 |
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