JPS6381864A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To enable improving high-frequency characteristics and obtaining a sufficient spacer thickness required for forming a gate by side-etching to avoid the remaining of a lift off spacer layer for forming a gate electrode on an active layer. CONSTITUTION:The first insulating layer 11 as the lift off spacer layer for forming a gate electrode, e.g., an SiO2 layer is formed by CVD and the second insulating layer 12, e.g., a silicon nitride layer is laminated by plasma CVD. Then, a photo resist layer 13 is coated on the second insulating layer 12, a window which has the length of a gate is provided in a region where a gate electrode is to be formed on the photo resist layer 13, the silicon nitride layer exposed in the window is selectively etched by chemical dry etching which uses a CF4 gas and the SiO2 layer of the first insulating layer 11 on an active layer 102 from a source electrode 104 to a drain electrode 105 is side-etched by using, e.g., ammonium fluoride aqueous solution until perfectly removed from the active layer region. In this case, the etching is almost not carried out since the etching rate of the second insulating layer is approx. 1/10 against the etching rate of the first insulating layer. Then, a metal for the gate electrode is evaporated on all the surface and the gate electrode 14 is formed by a lift off method.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a field effect transistor,
It is particularly applicable to a method of manufacturing a planar field effect transistor that does not undergo deep etching.

(Prior Art) Among field effect transistors, GaAs Schottky gate field effect transistors (hereinafter abbreviated as GaAs MESFETs) have excellent high frequency characteristics and are therefore widely used in microwave communication equipment.

The mainstream structure of conventional GaAs MESFETs has been a so-called recess structure, which has a depth comparable to the thickness of the gate electrode metal. However, G manufactured with a recessed structure
Since aAs MESFETs require deep recess etching, it is difficult to precisely control the amount of etching, and there is a problem that device characteristics vary within or between wafers. For this reason, in recent years, planar GaAs MESFI that does not require deep recess etching has been developed.
The development of ET is progressing diligently. Planar GaAs
Since MESFET does not require deep recess etching, it is expected to have excellent device characteristics such as uniformity and reproducibility.

An example of a conventional method for manufacturing a planar GaAs MESFET will be described below with reference to FIGS. Form(
Figure 2 a).

Next, a source electrode 104 and a drain electrode 105 are formed on the n'' type ohmic contact formation layer 103 by a commonly used lift-off method, and then alloyed by heating (FIG. 2b).Next, , for example, a SiO□ layer of the lift-off spacer layer 106 for forming a gate electrode,
A photoresist layer 107 is laminated and formed, and this photoresist layer is patterned to form an opening in the area where the gate electrode is to be formed, and the SiO□ layer 10 exposed in the opening is formed.
6 is etched. In addition.

If the amount of side etching is large, the resist layer will sag and lift-off will not be possible. Therefore, in this case, the spacer layer cannot be completely removed from above the active layer by side etching (FIG. 2C). Next, a metal for forming a gate electrode, such as aluminum, is deposited on the entire surface,
A gate electrode 108 is formed by lift-off means, and an example of Au/Pt/T is formed as a bonding metal layer.
After depositing the i-layer 109, eight layers of, for example, a 5i02 layer 110 are formed as a passivation film by the CVD method,
A planar GaAs MESFET is obtained (Fig. 2d)
).

(Problems to be Solved by the Invention) The conventional manufacturing method of the planar type GaAs MESFET has the following problems.

First, since the gate length of GaAs MESFETs is submicron or smaller, the lift-off method, which can faithfully transfer the hole pattern of photoresist as a metal pattern onto the semiconductor substrate, is widely used to form such fine patterns. has been done.

To perform the lift-off method stably, the metal layer on the resist and the metal layer on the semiconductor substrate must be spatially separated. Therefore, in general, a spacer layer for lift-off is provided between the semiconductor substrate and the photoresist layer, a hole is formed in this photoresist layer, and then side etching is used to remove the metal on the photoresist layer when etching the spacer layer. This prevents contact between the layer and the metal layer on the semiconductor substrate. In forming the gate electrode of a GaAs MESFET having a recessed structure, the lift-off spacer layer utilizes the step difference in the n-type active layer caused by recess etching, so the lift-off spacer layer as described above is not required. However, in planar type GaAs MESFETs, at least 4000 to 5000
A gate metal layer thickness of 4000 to 500 mm is required as a spacer for lift-off of the gate. That is, if the lift-off spacer is not large enough, the gate shape may be distorted or lift-off may not be possible. Therefore, in the conventional manufacturing method, a thick spacer layer remains on the n-type active layer after forming the gate electrode. and.

There is a problem in that the presence of a thick insulating layer on the n-type active layer causes deterioration in the high frequency characteristics of the FET. This is thought to be due to the effect of stress on the thick insulating layer.

This deterioration in high frequency characteristics can be recovered by removing the thick insulating layer, so for example, CF, gas (Freon)
It is conceivable to completely remove the insulating film by a chemical dry etching method using gas or the like. but,
In this case, there is a problem that the aluminum layer of the gate metal layer is exposed to the CF4 plasma for a long time, and the high frequency characteristics deteriorate due to damage caused by the plasma.

Therefore, for the reasons stated above, planar GaAs MESF
It is extremely difficult to remove the spacer layer to form the gate electrode of ET, and planar GaAs MESFET
However, sufficient characteristics are not obtained.

This invention applies to the conventional planar GaAs MESFE as described above.
It is an object of the present invention to provide an improved manufacturing method in which the adverse effects of a spacer for gate electrode lift-off in the manufacturing method of T are reduced.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a field effect transistor according to the present invention includes forming a semiconductor active layer on a semi-insulating semiconductor substrate, forming a source electrode and a drain electrode on the semiconductor active layer, and then forming a source electrode and a drain electrode on the semiconductor active layer. a first insulating layer and a second insulating layer having a lower etching rate than the first insulating layer;
A resist layer is deposited on the second insulating layer, a window of a desired gate length is provided in the resist layer, and then the resist layer is used as a mask to form a resist layer on the second insulating layer. An opening is provided, and the first insulating layer between the source electrode and the drain electrode is completely removed through the opening, a metal layer for a gate electrode is deposited using the resist layer as a mask, and a gate electrode is formed by a lift-off method. It includes a process.

(Function) The above method for manufacturing the planar GaAs MESFET does not leave a lift-off spacer layer for forming the gate electrode on the active layer, so high frequency characteristics are improved and the spacer thickness necessary for forming the gate is improved. The reproducibility of the manufacturing process is also excellent.

(Example) An example of the present invention will be described below with reference to the drawings. In addition, in the description, parts that are the same as the conventional one are shown in one drawing with the same reference numerals as the conventional one, and some of the conventional steps and drawings are used and the explanation is omitted.

An n-type active layer 102 is formed on a GaAs substrate 101. n+ type ohmic contact forming layer 103. Source electrode 104. Following the steps illustrated in FIGS. 2a, b for forming the drain electrode 105, a first insulating layer 11, e.g.
D method is used to form about 3,000 layers, and then the second insulating layer 1 is formed.
2. For example, the silicon nitride layer is deposited by plasma CVD method by approximately 2
000 in stock (Fig. 1a). Next, a photoresist layer 13 is deposited on the second insulating layer 12, a gate length window is provided in the region where the gate electrode is to be formed, and the exposed silicon nitride layer is exposed to a chemical film using CF and gas. Selective etching is performed using a dry etching method, and then the SiO2 layer of the first insulating layer 11 on the active layer 102 from the source electrode 104 to the drain electrode 105 is completely etched from above the active layer region using, for example, an ammonium fluoride aqueous solution. Side etching is performed until the surface is completely removed (Figure 1b). At this time, the etching rate of the silicon nitride layer, which is the second insulating layer, with respect to the ammonium fluoride aqueous solution is about 1710 for the 5-layer 02 layer, which is the first insulating layer. After the silicon nitride layer is hardly etched, a gate electrode metal such as aluminum is deposited on the entire surface to a thickness of about 5,000 yen, and the gate electrode 14 is formed by a lift-off method.
This is coated with a metal layer for bonding, e.g. Au/Pt/
After forming the Ti layer 109, a thin insulating layer 1, for example, an S'i02 layer 15, is formed by CVO as a passivation layer.
A planar GaAs MESFET is obtained by the method (FIG. 1C).

Note that the above embodiment is a planar ion-implanted GaAs
Although MESFET has been explained, it goes without saying that it is effective even without an n+ ohmic liquid contact formation layer, and the insulating layer is not limited to a Si layer, a silicon nitride layer, and, for example, a phosphosilicate glass layer. (PSG)W, an aluminum oxide (AQ, o, ) layer may also be used. Furthermore, it is also effective when the active layer or the active layer and the ohmic contact forming layer are recessed and etched to a thickness of 500 Å or less before the gate electrode is deposited.

〔Effect of the invention〕

As described above, according to the present invention, since no lift-off spacer layer for forming the gate electrode remains on the active layer, not only the high frequency characteristics of the planar GaAs MESFET are improved, but also the lift-off spacer layer necessary for forming the gate electrode is improved. Since a sufficient spacer layer can be obtained, a method for manufacturing a field effect transistor with excellent reproducibility in the manufacturing process can be provided.

[Brief explanation of the drawing]

FIGS. 1A to 1C show a planar type Ga according to an embodiment of the present invention.
All are cross-sectional views showing the manufacturing method of As MESFET in order of process, and Figures 2a to 2d are planar type GaASMES.
Each of the drawings is a cross-sectional view showing a conventional method for manufacturing an FET in the order of steps. 101----GaAs substrate 102-----n-type active layer 103-----n+ pear-shaped ohmic contact forming layer 104
------- Source electrode 1os---------Drain electrode 11--------First insulating layer 12-----Second insulating layer 13----Photoresist Layer 14 ------- Gate electrode 15 ------- Sin, layer

Claims (1)

[Claims] A step of forming a semiconductor active layer on a semi-insulating semiconductor substrate, and forming a source electrode and a drain electrode on the semiconductor active layer, and then forming a first insulating layer and a second insulating layer having a lower etching rate than the first insulating layer. a step of depositing a resist layer on the second insulating layer, a step of depositing a resist layer on the second insulating layer, and a step of forming a window with a desired gate length in the resist layer, and then applying the resist layer as a mask to the second insulating layer. A step of forming an opening and then removing the entire first insulating layer between the source electrode and the drain electrode through the opening, and depositing a metal layer for the gate electrode using the resist layer as a mask and using a lift-off method. A method for manufacturing a field effect transistor including a step of forming a gate electrode.