KR960026926A - Formation method of T-type gate - Google Patents

Formation method of T-type gate Download PDF

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Publication number
KR960026926A
KR960026926A KR1019940036029A KR19940036029A KR960026926A KR 960026926 A KR960026926 A KR 960026926A KR 1019940036029 A KR1019940036029 A KR 1019940036029A KR 19940036029 A KR19940036029 A KR 19940036029A KR 960026926 A KR960026926 A KR 960026926A
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KR
South Korea
Prior art keywords
gate
insulating film
planarization
photoresist pattern
film
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KR1019940036029A
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Korean (ko)
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KR0163742B1 (en
Inventor
양전욱
오응기
이진희
박철순
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양승택
재단법인 한국전자통신연구소
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Priority to KR1019940036029A priority Critical patent/KR0163742B1/en
Publication of KR960026926A publication Critical patent/KR960026926A/en
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Publication of KR0163742B1 publication Critical patent/KR0163742B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

본 발명은 반도체 장치의 제조방법에 있어서, 개선된 T형 게이트를 형성하느 방법에 관한 것이다.The present invention relates to a method of forming an improved T-type gate in a method of manufacturing a semiconductor device.

본 발명에 의해 제작된 공중교각(airbridge) 형태의 T-게이트에 의하면, 게이트 금속이 화학적인 방법으로 증착된 절연막에 의해 접촉되기 때문에 종래의 포토레지스트와 게이트 금속 사이에서 나타날 수 있는 계면에 따른 측면방향의 Au 성장을 억제할 수 있으며, 금속선 간의 단락의 발생을 방지할 수 있기 때문에 금속선간의 간격을 줄일 수 있다.According to the airbridge type T-gate manufactured by the present invention, since the gate metal is contacted by an insulating film deposited by a chemical method, the side along the interface which may appear between the conventional photoresist and the gate metal The growth of Au in the direction can be suppressed, and the short circuit between the metal lines can be prevented, so that the gap between the metal lines can be reduced.

또한 공정을 안정화시킴과 아울러 단순화시킬 수 있기 때문에 수율을 향상시킬 수 있다.In addition, since the process can be stabilized and simplified, the yield can be improved.

Description

T형 게이트의 형성방법.Formation method of T-type gate.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 내지 제9도는 본 발명에 의한 T형 게이트의 형성방법을 각 단계별로 나타낸 공정 단면도로서, 제1도는 기판위에 미세한 포토레지스트 패턴의 형성공정을 나타낸 단면도, 제2도는 절연막 증착공정을 나타낸 단면도.1 to 9 are process cross-sectional views showing the method of forming a T-type gate according to the present invention at each stage, FIG. 1 is a cross-sectional view showing a process of forming a fine photoresist pattern on a substrate, and FIG. 2 is a dielectric film deposition process. Cross-section.

제3도는 평탄화막의 형성공정을 나타낸 단면도.3 is a cross-sectional view showing a step of forming a planarization film.

제4도는 절연막 노출을 위한 평탄화막의 식각공정을 도시한 단면도,4 is a cross-sectional view illustrating an etching process of a planarization film for exposing an insulating film;

제5도는 노출된 절연막의 습식식각 단계를 도시한 단면도.5 is a cross-sectional view showing a wet etching step of an exposed insulating film.

제6도는 미세 패턴의 포토레지스트막을 제거하고 이 부위를 리세스 식각하는 단계를 도시한 단면도.FIG. 6 is a cross-sectional view showing a step of removing a fine pattern photoresist film and recess etching the portion. FIG.

제7도는 평탄화막과 절연막을 마스크로 이용한 게이트 금속의 증착단계를 제8도는 평탄화막의 리프트-오프 단계를 나타낸 단면도,FIG. 7 is a cross-sectional view illustrating a step of depositing a gate metal using a planarization film and an insulating film as a mask, and FIG.

제9도는 절연막의 식각단계를 각각 나타낸 단면도이다.9 is a cross-sectional view illustrating an etching step of an insulating film, respectively.

Claims (3)

반도체 장치의 제조방법에 있어서, 반도체 기판상의 게이트영역에 해당하는 부위에 미세한 포토레지스트 패턴을 형성하는 공정; 상기 포토레지스트 패턴을 포함한 기판의 전면에 절연막을 증착하는 공정; 상기 절연막을 충분히 피복할 수 있도록 평탄화막을 도포하는 공정; 상기 게이트영역 상의 절연막을 노출시킬 수 있도록 상기 평탄화막을 건식식각하는 공정; 상기 포토레지스트 패턴 상부 및 측면 주위의 절연막을 식각하는 공정; 상기 공정에 의해 노출된 포토레지스트 패턴을 제거한 후, 노출된 반도체 기판을 리세스(recess) 식각하는 공정; 및 상기 잔류된 절연막과 평탄화마 패턴을 마스크로 이용하여 게이트 박막을 증착한 후, 상기 잔류된 절연막과 평탄화막 패턴을 제거하여 공중교각(airbridge) 형상의 게이트를 형성하는 공정으로 이루어진 것을 특징으로 하는 T형 게이트의 형성방법.A method of manufacturing a semiconductor device, comprising: forming a fine photoresist pattern at a portion corresponding to a gate region on a semiconductor substrate; Depositing an insulating film on the entire surface of the substrate including the photoresist pattern; Applying a planarization film to sufficiently cover the insulating film; Dry etching the planarization layer to expose the insulating layer on the gate region; Etching the insulating film around upper and side surfaces of the photoresist pattern; Removing the photoresist pattern exposed by the process and then etching the exposed semiconductor substrate; And depositing a gate thin film using the remaining insulating film and the planarization pattern as a mask, and then removing the remaining insulating film and the planarization pattern to form an airbridge-shaped gate. Formation method of T-type gate. 제1항에 있어서, 상기 평탄화막의 재질은 상기 포토레지스트 패턴과 다른 종류 및 다른 용매를 갖는 포토레지스트로 이루어진 것을 특징으로 하는 T형 게이트의 형성방법.The method of claim 1, wherein the planarization film is formed of a photoresist having a different type and a different solvent from the photoresist pattern. 제1항에 있어서, 상기 게이트 금속을 증착하는 공정이 방향성을 갖는(또는 경사증착이 가능한) 전자-빔 증착기(E-beam evaporator)에 의해 수행됨을 특징으로 하는 T형 게이트의 형성방법.The method of claim 1, wherein the depositing of the gate metal is performed by an directional (or capable of gradient deposition) of an E-beam evaporator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940036029A 1994-12-22 1994-12-22 Method for forming t-shape gate KR0163742B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940036029A KR0163742B1 (en) 1994-12-22 1994-12-22 Method for forming t-shape gate

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Application Number Priority Date Filing Date Title
KR1019940036029A KR0163742B1 (en) 1994-12-22 1994-12-22 Method for forming t-shape gate

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KR960026926A true KR960026926A (en) 1996-07-22
KR0163742B1 KR0163742B1 (en) 1998-12-01

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