KR100295669B1 - Fabricating method of dual gate oxide film - Google Patents
Fabricating method of dual gate oxide film Download PDFInfo
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- KR100295669B1 KR100295669B1 KR1019980053128A KR19980053128A KR100295669B1 KR 100295669 B1 KR100295669 B1 KR 100295669B1 KR 1019980053128 A KR1019980053128 A KR 1019980053128A KR 19980053128 A KR19980053128 A KR 19980053128A KR 100295669 B1 KR100295669 B1 KR 100295669B1
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- 230000009977 dual effect Effects 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000000356 contaminant Substances 0.000 abstract description 3
- 238000011109 contamination Methods 0.000 abstract description 2
- 230000000873 masking effect Effects 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 150000002739 metals Chemical class 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
본 발명은 듀얼 게이트산화막 제조방법에 관한 것으로, 종래에는 감광막이 게이트산화막과 직접적으로 접촉됨에 따라 감광막에 포함된 유기 오염물질들(특히 금속)로 인하여 게이트산화막의 신뢰성이 급격히 저하됨과 아울러 전세공정을 통해 게이트산화막과 직접적으로 접촉된 감광막을 제거함에 따라 게이트산화막이 플라즈마로 인해 손상을 입는 문제점이 있었다. 따라서, 본 발명은 제1,제2액티브영역에 두꺼운 산화막과 얇은 산화막의 듀얼 게이트산화막을 각기 형성하는 듀얼 게이트산화막 제조방법에 있어서, 상기 제1,제2액티브영역의 반도체기판 상부에 순차적으로 제1산화막과 마스크층을 형성하는 공정과; 상기 제2액티브영역의 마스크층 상부에 감광막 패턴을 형성하여 제1액티브영역의 마스크층을 제거하는 공정과; 상기 감광막 패턴을 제거한 후, 제1액티브영역의 제1산화막을 제거하는 공정과; 상기 제1산화막이 제거된 제1액티브영역 상부에 제2산화막을 제1산화막보다 두껍게 형성하는 공정과; 상기 제2액티브영역 상부에 형성된 마스크층을 제거하는 공정으로 이루어지는 듀얼 게이트산화막 제조방법을 통해 게이트산화막과 감광막이 직접적으로 접촉되는 것을 방지하여 감광막으로 인한 게이트산화막의 오염을 방지할 수 있게 되므로, 게이트산화막의 신뢰성을 향상시킬 수 있고 아울러 감광막의 제거시에 플라즈마로 인한 게이트산화막의 손상을 질화막의 마스킹을 통해 방지할 수 있는 효과가 있다.The present invention relates to a method of manufacturing a dual gate oxide film. In the related art, as the photoresist film is directly in contact with the gate oxide film, organic contaminants (especially metals) included in the photoresist film rapidly reduce the reliability of the gate oxide film and perform a charter process. As a result of removing the photoresist layer directly contacted with the gate oxide layer, the gate oxide layer may be damaged by the plasma. Accordingly, the present invention provides a dual gate oxide film manufacturing method for forming a dual gate oxide film of a thick oxide film and a thin oxide film in the first and second active regions, respectively, wherein the first and second active regions are sequentially formed on the semiconductor substrate of the first and second active regions. Forming an oxide film and a mask layer; Removing a mask layer of the first active region by forming a photoresist pattern on the mask layer of the second active region; Removing the photoresist pattern, and then removing the first oxide film of the first active region; Forming a second oxide film thicker than the first oxide film on the first active region from which the first oxide film is removed; Since the gate oxide film and the photosensitive film are prevented from directly contacting through the dual gate oxide film manufacturing method including removing the mask layer formed on the second active region, it is possible to prevent contamination of the gate oxide film due to the photosensitive film. The reliability of the oxide film can be improved and the damage of the gate oxide film due to the plasma can be prevented by masking the nitride film when the photoresist film is removed.
Description
본 발명은 듀얼 게이트산화막 제조방법에 관한 것으로, 특히 감광막(photoresist)과 게이트산화막의 직접적인 접촉에 따른 오염물질(contaminant)로 인해 게이트산화막의 신뢰성이 열화됨과 아울러 감광막의 제거시 게이트산화막이 플라즈마로 인해 손상을 입는 것을 방지하기에 적당하도록 한 듀얼 게이트산화막 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a dual gate oxide film. In particular, the reliability of the gate oxide film is degraded due to contaminants due to direct contact between the photoresist and the gate oxide film. The present invention relates to a method of manufacturing a dual gate oxide film, which is suitable for preventing damage.
종래의 듀얼 게이트산화막 제조방법을 도1a 내지 도1d의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A conventional method of manufacturing a dual gate oxide film will be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1D.
먼저, 도1a에 도시한 바와같이 두꺼운 게이트산화막이 형성될 제1액티브영역과 얇은 게이트산화막이 형성될 제2액티브영역의 반도체기판(1) 상부에 열산화공정을 통해 열산화막(2)을 형성하고, 그 열산화막(2)의 상부전면에 감광막을 도포한 후, 노광 및 현상하여 상기 제1액티브영역의 열산화막(2) 상부에만 감광막 패턴(PR1)을 형성한다.First, as shown in FIG. 1A, a thermal oxide film 2 is formed on a semiconductor substrate 1 on a first active region in which a thick gate oxide film is to be formed and a second active region in which a thin gate oxide film is to be formed. Then, after the photosensitive film is coated on the upper surface of the thermal oxide film 2, the photoresist film is exposed and developed to form the photosensitive film pattern PR1 only on the thermal oxide film 2 in the first active region.
그리고, 도1b에 도시한 바와같이 상기 감광막 패턴(PR1)을 적용하여 제2액티브영역의 열산화막(2)을 절반정도 습식식각한다.As shown in FIG. 1B, the thermal oxide film 2 of the second active region is wet-etched about half by applying the photoresist pattern PR1.
그리고, 도1c에 도시한 바와같이 상기 감광막 패턴(PR1)을 제거한 후, 제2액티브영역의 반도체기판(1)이 노출될 때까지 제1,제2액티브영역의 열산화막(2)을 세정한다.After removing the photoresist pattern PR1 as shown in FIG. 1C, the thermal oxide film 2 of the first and second active regions is cleaned until the semiconductor substrate 1 of the second active region is exposed. .
그리고, 도1d에 도시한 바와같이 상기 도1c의 결과물 상부전면에 열산화공정을 통해 열산화막(3)을 형성한다.As shown in FIG. 1D, a thermal oxide film 3 is formed on the upper surface of the resultant product of FIG. 1C through a thermal oxidation process.
따라서, 제1액티브영역에는 열산화막(2,3)이 적층된 70Å 정도의 두꺼운 게이트산화막이 형성되고, 제2액티브영역에는 열산화막(3)만이 형성된 50Å 정도의 얇은 게이트산화막이 형성된다.Accordingly, a thick gate oxide film having a thickness of about 70 ms is formed in the first active region, and a thin gate oxide film of about 50 ms is formed in the second active region, in which only the thermal oxide film 3 is formed.
그러나, 상기한 바와같은 종래의 게이트산화막 제조방법은 감광막이 게이트산화막과 직접적으로 접촉됨에 따라 감광막에 포함된 유기 오염물질들(특히 금속)로 인하여 게이트산화막의 신뢰성이 급격히 저하됨과 아울러 전세공정을 통해 게이트산화막과 직접적으로 접촉된 감광막을 제거함에 따라 게이트산화막이 플라즈마로 인해 손상을 입는 문제점들이 다수의 논문(일예로, Y.Shiramizu et al., Ext. Abst. Of the International Conference on Solid State Devices and Meterals, pp.362-364, 1996)들에 보고되고 있다.However, in the conventional method of manufacturing a gate oxide film as described above, as the photoresist film is in direct contact with the gate oxide film, the organic oxides (particularly, metals) included in the photoresist film rapidly reduce the reliability of the gate oxide film and also through a charter process. Problems in which gate oxides are damaged by plasma by removing the photoresist that is in direct contact with the gate oxides have been described in a number of papers (eg, Y. Shiramizu et al., Ext. Abst. Of the International Conference on Solid State Devices and Meterals, pp. 362-364, 1996).
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 감광막이 게이트산화막과 직접적으로 접촉되는 것을 방지하여 감광막과 전세용액에 포함된 유기 오염물질들로 인한 게이트산화막의 신뢰성저하를 방지함과 아울러 감광막의 제거시 플라즈마로 인한 게이트산화막의 손상을 방지할 수 있는 듀얼 게이트산화막 제조방법을 제공하는데 있다.The present invention has been devised to solve the above-mentioned problems, and an object of the present invention is to prevent the photoresist from coming into direct contact with the gate oxide film, thereby preventing the gate oxide film from organic contaminants contained in the photoresist film and the charter solution. The present invention provides a method of manufacturing a dual gate oxide film which can prevent the deterioration of reliability and prevent damage of the gate oxide film due to plasma when the photoresist film is removed.
도1은 종래의 듀얼 게이트산화막 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method of manufacturing a dual gate oxide film.
도2는 본 발명의 제1실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing a first embodiment of the present invention.
도3은 본 발명의 제2실시예를 보인 수순단면도.Figure 3 is a flow sectional view showing a second embodiment of the present invention.
도4는 본 발명의 제3실시예를 보인 수순단면도.Figure 4 is a cross-sectional view showing a third embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12,14,15:산화막11: semiconductor substrate 12, 14, 15: oxide film
13:질화막 PR11:감광막 패턴13: Nitride film PR11: Photosensitive film pattern
상기한 바와같은 본 발명의 목적을 달성하기 위한 듀얼 게이트산화막 제조방법의바람직한 제1실시예는 제1,제2액티브영역에 두꺼운 산화막과 얇은 산화막의 듀얼 게이트산화막을 각기 형성하는 듀얼 게이트산화막 제조방법에 있어서, 상기 제1,제2액티브영역의 반도체기판 상부에 순차적으로 제1산화막과 마스크층을 형성하는 공정과; 상기 제2액티브영역의 마스크층 상부에 감광막 패턴을 형성하여 제1액티브영역의 마스크층을 제거하는 공정과; 상기 감광막 패턴을 제거한 후, 제1액티브영역의 제1산화막을 제거하는 공정과; 상기 제1산화막이 제거된 제1액티브영역 상부에 제2산화막을 제1산화막보다 두껍게 형성하는 공정과; 상기 제2액티브영역 상부에 형성된 마스크층을 제거하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A preferred first embodiment of the dual gate oxide film production method for achieving the object of the present invention as described above is a dual gate oxide film production method for forming a dual gate oxide film of a thick oxide film and a thin oxide film in the first and second active regions, respectively. The method of claim 1, further comprising: sequentially forming a first oxide film and a mask layer on the semiconductor substrate of the first and second active regions; Removing a mask layer of the first active region by forming a photoresist pattern on the mask layer of the second active region; Removing the photoresist pattern, and then removing the first oxide film of the first active region; Forming a second oxide film thicker than the first oxide film on the first active region from which the first oxide film is removed; And removing the mask layer formed on the second active region.
그리고, 상기한 바와같은 본 발명의 목적을 달성하기 위한 듀얼 게이트산화막 제조방법의 바람직한 제2실시예는 제1,제2액티브영역에 두꺼운 산화막과 얇은 산화막의 듀얼 게이트산화막을 각기 형성하는 듀얼 게이트산화막 제조방법에 있어서, 상기 제1,제2액티브영역의 반도체기판 상부에 질화막을 형성하는 공정과; 상기 제2액티브영역의 질화막 상부에 감광막 패턴을 형성하여 제1액티브영역의 질화막을 제거하는 공정과; 상기 감광막 패턴을 제거한 후, 제1액티브영역의 반도체기판 상부에 제1산화막을 형성하는 공정과; 상기 제2액티브영역에 잔류하는 질화막을 제거하는 공정과; 상기 제1,제2액티브영역 상부에 제2산화막을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In addition, a second preferred embodiment of the method for manufacturing a dual gate oxide film for achieving the object of the present invention as described above is a dual gate oxide film for forming a dual gate oxide film of a thick oxide film and a thin oxide film in the first and second active regions, respectively. A manufacturing method, comprising: forming a nitride film on an upper portion of a semiconductor substrate of the first and second active regions; Removing the nitride film of the first active region by forming a photoresist pattern on the nitride film of the second active region; Removing the photoresist pattern, and then forming a first oxide film over the semiconductor substrate of the first active region; Removing the nitride film remaining in the second active region; And forming a second oxide film on the first and second active regions.
그리고, 상기한 상기한 바와같은 본 발명의 목적을 달성하기 위한 듀얼 게이트산화막 제조방법의 바람직한 제3실시예는 제1,제2액티브영역에 두꺼운 산화막과 얇은산화막의 듀얼 게이트산화막을 각기 형성하는 듀얼 게이트산화막 제조방법에 있어서, 상기 제1,제2액티브영역의 반도체기판 상부에 순차적으로 제1산화막과 질화막을 형성하는 공정과; 상기 제1액티브영역의 질화막 상부에 감광막 패턴을 형성하여 제2액티브영역의 질화막을 제거하는 공정과; 상기 감광막 패턴을 제거한 후, 제2액티브영역의 제1산화막을 식각하여 제1,제2액티브영역 상에 형성된 제1산화막의 두께를 차별화하는 공정과; 상기 질화막을 제거하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In addition, a third preferred embodiment of the method for manufacturing a dual gate oxide film for achieving the object of the present invention as described above is a dual forming a dual gate oxide film of a thick oxide film and a thin oxide film in the first and second active regions, respectively. A method of manufacturing a gate oxide film, comprising: sequentially forming a first oxide film and a nitride film on an upper surface of a semiconductor substrate of the first and second active regions; Removing a nitride film of the second active area by forming a photoresist pattern on the nitride film of the first active area; Removing the photoresist pattern, and etching the first oxide film of the second active region to differentiate the thickness of the first oxide film formed on the first and second active regions; It is characterized by comprising a step of removing the nitride film.
상기한 바와같은 본 발명에 의한 듀얼 게이트산화막 제조방법의 바람직한 제1실시예를 도2a 내지 도2h의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A first preferred embodiment of the method for manufacturing a dual gate oxide film according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2H.
먼저, 도2a에 도시한 바와같이 두꺼운 게이트산화막이 형성될 제1액티브영역과 얇은 게이트산화막이 형성될 제2액티브영역의 반도체기판(11) 상부에 산화막(12)을 50Å 정도의 두께로 형성한 후, 그 산화막(12)의 상부에 마스크층으로 질화막(13)을 증착한다. 이때, 마스크층으로 사용되는 질화막(13)은 얇을수록 반도체기판(11)의 손상을 줄일 수 있으나, 너무 얇으면 감광막과 게이트산화막이 직접적으로 접촉되는 것을 차단하는 마스크층으로의 역할을 할 수 없게 되므로 500Å 정도의 두께로 형성하는 것이 바람직하다.First, as shown in FIG. 2A, an oxide film 12 is formed on the semiconductor substrate 11 on the first active region where the thick gate oxide film is to be formed and the second active region where the thin gate oxide film is to be formed. Thereafter, the nitride film 13 is deposited as a mask layer on the oxide film 12. In this case, the thinner the nitride film 13 used as the mask layer can reduce the damage of the semiconductor substrate 11, but if too thin, the nitride film 13 cannot serve as a mask layer that blocks direct contact between the photoresist film and the gate oxide film. Therefore, it is preferable to form the thickness of about 500 kPa.
그리고, 도2b에 도시한 바와같이 상기 질화막(13)의 상부에 감광막을 도포한 후, 노광 및 현상하여 제2액티브영역 상부에 감광막 패턴(PR11)을 형성한다.As shown in FIG. 2B, a photosensitive film is coated on the nitride film 13, and then exposed and developed to form a photosensitive film pattern PR11 on the second active region.
그리고, 도2c에 도시한 바와같이 상기 감광막 패턴(PR11)을 적용하여 제1액티브영역의 질화막(13)을 제거한다.As shown in FIG. 2C, the photosensitive film pattern PR11 is applied to remove the nitride film 13 of the first active region.
그리고, 도2d에 도시한 바와같이 상기 감광막 패턴(PR11)을 제거한 후, 제1액티브영역의 산화막(12)을 제거하여 반도체기판(11)을 노출시킨다. 이때, 제2액티브영역의 산화막(12)은 질화막(13)을 통해 마스킹되므로 제거되지 않는다.After the photoresist pattern PR11 is removed as shown in FIG. 2D, the oxide film 12 of the first active region is removed to expose the semiconductor substrate 11. At this time, since the oxide film 12 of the second active region is masked through the nitride film 13, it is not removed.
그리고, 도2e에 도시한 바와같이 상기 산화막(12)이 제거된 제1액티브영역의 반도체기판(11) 상부에 산화막(14)을 70Å의 두께로 형성한다.As shown in FIG. 2E, an oxide film 14 is formed on the semiconductor substrate 11 in the first active region from which the oxide film 12 has been removed to a thickness of 70 占 퐉.
그리고, 도2f에 도시한 바와같이 상기 제2액티브영역의 질화막(12)을 제거한다.As shown in Fig. 2F, the nitride film 12 of the second active region is removed.
한편, 상기 산화막(12,14)을 통해 형성된 듀얼 게이트산화막의 성장두께에 대한 신뢰성을 향상시키기 위하여 도2g에 도시한 바와같이 상기 제1,제2액티브영역의 반도체기판(11) 상부에 형성된 산화막(14,12)을 산화막(12)이 완전히 제거될때까지 세정하여 제2액티브영역의 반도체기판(11)을 노출시키고, 도2h에 도시한 바와같이 상기 제1,제2액티브영역 상에 성장두께에 대한 신뢰성이 뛰어난 As를 이용한 산화공정을 수행하여 산화막(15)을 성장시키는 것도 고려된다.Meanwhile, in order to improve the reliability of the growth thickness of the dual gate oxide film formed through the oxide films 12 and 14, the oxide film formed on the semiconductor substrate 11 of the first and second active regions, as shown in FIG. 2G. 14 and 12 are cleaned until the oxide film 12 is completely removed to expose the semiconductor substrate 11 of the second active region, and the growth thickness on the first and second active regions as shown in FIG. 2H. It is also contemplated to grow the oxide film 15 by performing an oxidation process using As having excellent reliability.
한편, 상기한 바와같은 본 발명에 의한 듀얼 게이트산화막 제조방법의 바람직한 제2실시예를 도3a 내지 도3e의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.Meanwhile, a second preferred embodiment of the method for manufacturing a dual gate oxide film according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 3A to 3E.
먼저, 도3a에 도시한 바와같이 두꺼운 게이트산화막이 형성될 제1액티브영역과 얇은 게이트산화막이 형성될 제2액티브영역의 반도체기판(21)의 상부에 질화막(22)을 형성하고, 그 질화막(22)의 상부에 감광막을 도포한 후, 노광 및 현상하여 제2액티브영역 상의 질화막(22) 상부에 감광막 패턴(PR21)을 형성한다. 이때, 질화막(22)은 상기 본 발명의 제1실시예와 동일하게 500Å 정도의 두께로 형성하는 것이 바람직하다.First, as shown in FIG. 3A, a nitride film 22 is formed on the semiconductor substrate 21 of the first active region where the thick gate oxide film is to be formed and the second active region where the thin gate oxide film is to be formed, and the nitride film ( After the photoresist film is applied on the upper part of 22), the photoresist film is exposed and developed to form the photoresist pattern PR21 on the upper part of the nitride film 22 on the second active region. In this case, it is preferable that the nitride film 22 is formed to a thickness of about 500 GPa as in the first embodiment of the present invention.
그리고, 도3b에 도시한 바와같이 상기 감광막 패턴(PR21)을 적용하여 제1액티브영역의 질화막(22)을 제거하여 반도체기판(21)을 노출시킨 후, 감광막 패턴(PR21)을 제거한다.As shown in FIG. 3B, the photosensitive film pattern PR21 is applied to remove the nitride film 22 of the first active region to expose the semiconductor substrate 21, and then the photosensitive film pattern PR21 is removed.
그리고, 도3c에 도시한 바와같이 상기 노출된 제1액티브영역의 반도체기판(21) 상부에 산화막(23)을 형성한다. 이때, 제2액티브영역의 반도체기판(21) 상부는 질화막(22)에 의해 마스킹되므로 산화막(23)이 형성되지 않는다.As shown in FIG. 3C, an oxide film 23 is formed over the exposed semiconductor substrate 21 of the first active region. At this time, since the upper portion of the semiconductor substrate 21 of the second active region is masked by the nitride film 22, the oxide film 23 is not formed.
그리고, 도3d에 도시한 바와같이 상기 제2액티브영역의 질화막(22)을 제거한다.As shown in FIG. 3D, the nitride film 22 of the second active region is removed.
그리고, 도3e에 도시한 바와같이 상기 제1,제2액티브영역의 반도체기판(21) 상부에 산화막(24)을 형성한다.As shown in FIG. 3E, an oxide film 24 is formed over the semiconductor substrate 21 of the first and second active regions.
한편, 상기한 바와같은 본 발명에 의한 듀얼 게이트산화막 제조방법의 바람직한 제3실시예를 도4a 내지 도4d의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.Meanwhile, a third preferred embodiment of the method for manufacturing a dual gate oxide film according to the present invention as described above will be described in detail with reference to the cross-sectional views of FIGS. 4A to 4D.
먼저, 도4a에 도시한 바와같이 두꺼운 게이트산화막이 형성될 제1액티브영역과 얇은 게이트산화막이 형성될 제2액티브영역의 반도체기판(31) 상부에 산화막(32)과 질화막(33)을 순차적으로 형성하고, 그 질화막(33)의 상부에 감광막을 도포한 후, 노광 및 현상하여 제1액티브영역상의 질화막(33) 상부에 감광막 패턴(PR31)을 형성한다. 이때, 산화막(32)은 70Å 정도의 두께로 형성하고, 질화막(33)은 상기 본 발명의 제1실시예와 동일하게 500Å 정도의 두께로 형성하는 것이 바람직하다.First, as shown in FIG. 4A, the oxide film 32 and the nitride film 33 are sequentially formed on the semiconductor substrate 31 of the first active region where the thick gate oxide film is to be formed and the second active region where the thin gate oxide film is to be formed. After the photoresist film is formed on the nitride film 33, the photoresist film is exposed and developed to form the photoresist pattern PR31 on the nitride film 33 on the first active region. At this time, it is preferable that the oxide film 32 is formed to a thickness of about 70 GPa, and the nitride film 33 is formed to a thickness of about 500 GPa as in the first embodiment of the present invention.
그리고, 도4b에 도시한 바와같이 상기 감광막 패턴(PR31)을 적용하여 제2액티브영역의 질화막(33)을 제거하여 산화막(32)을 노출시킨 후, 감광막 패턴(PR31)을 제거한다.As shown in FIG. 4B, the photoresist pattern PR31 is applied to remove the nitride layer 33 of the second active region to expose the oxide layer 32, and then the photoresist pattern PR31 is removed.
그리고, 도4c에 도시한 바와같이 상기 노출된 제2액티브영역의 산화막(32)을 식각하여 제1,제2액티브영역 상에 형성된 산화막(32)의 두께를 차별화한다. 이때, 제2액티브영역에 잔류하는 산화막(32)이 50Å 정도의 두께가 되도록 식각하는 것이 바람직하다.As shown in FIG. 4C, the exposed oxide film 32 of the second active region is etched to differentiate the thickness of the oxide film 32 formed on the first and second active regions. At this time, it is preferable to etch the oxide film 32 remaining in the second active region to have a thickness of about 50 GPa.
그리고, 도4d에 도시한 바와같이 상기 제1액티브영역의 질화막(33)을 제거한다.As shown in FIG. 4D, the nitride film 33 of the first active region is removed.
상기한 바와같은 본 발명에 의한 듀얼 게이트산화막 제조방법의 바람직한 실시예들은 제1액티브영역에 형성되는 두꺼운 게이트산화막이 70Å 정도가 되도록 하고, 제2액티브영역에 형성되는 얇은 게이트산화막이 50Å 정도가 되도록 하는 것이 바람직하다.Preferred embodiments of the method for manufacturing a dual gate oxide film according to the present invention as described above are such that the thick gate oxide film formed in the first active region is about 70 GPa and the thin gate oxide film formed in the second active region is about 50 GPa. It is desirable to.
상기한 바와같은 본 발명에 의한 듀얼 게이트산화막 제조방법은 게이트산화막과 감광막이 직접적으로 접촉되는 것을 방지하여 감광막으로 인한 게이트산화막의 오염을 방지할 수 있게 되므로, 게이트산화막의 신뢰성을 향상시킬 수 있고 아울러 감광막의 제거시에 플라즈마로 인한 게이트산화막의 손상을 질화막의 마스킹을 통해 방지할 수 있는 효과가 있다.The method of manufacturing a dual gate oxide film according to the present invention as described above prevents the gate oxide film from directly contacting the photoresist film, thereby preventing contamination of the gate oxide film due to the photoresist film, thereby improving the reliability of the gate oxide film. When the photoresist film is removed, damage to the gate oxide film due to plasma can be prevented through masking the nitride film.
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|---|---|---|---|---|
| KR100364599B1 (en) * | 2001-02-13 | 2002-12-16 | 삼성전자 주식회사 | Method for fabricating semiconductor device |
| KR100356824B1 (en) * | 2001-01-04 | 2002-10-18 | 주식회사 하이닉스반도체 | Method of fabricating a semiconductor device |
| KR100803979B1 (en) * | 2002-05-29 | 2008-02-15 | 주식회사 포스코 | Device for supplying filler protecting cap in ladle |
| KR100691943B1 (en) * | 2003-12-11 | 2007-03-09 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
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1998
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| KR20000038221A (en) | 2000-07-05 |
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