KR100783636B1 - Method for forming contact of semiconductor device - Google Patents

Method for forming contact of semiconductor device Download PDF

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KR100783636B1
KR100783636B1 KR1020010088961A KR20010088961A KR100783636B1 KR 100783636 B1 KR100783636 B1 KR 100783636B1 KR 1020010088961 A KR1020010088961 A KR 1020010088961A KR 20010088961 A KR20010088961 A KR 20010088961A KR 100783636 B1 KR100783636 B1 KR 100783636B1
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forming
trench
contact
nitride film
semiconductor device
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KR1020010088961A
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Korean (ko)
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KR20030058505A (en
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이형동
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 본 발명에 따른 반도체소자의 콘택 형성방법은, 반도체기판내에 활성영역과 비활성영역을 한정하는 트렌치를 형성하는 단계; 상기 트렌치내에 트렌치소자분리막을 형성하는 단계; 상기 트렌치소자분리막을 전면 식각하여 상기 트렌치내에 측벽을 형성하는 단계; 상기 측벽에 질화막스페이서를 형성하는 단계; 상기 전체 구조의 상면에 층간절연막을 형성하는 단계; 상기 층간절연막 및 질화막스페이서내에 상기 반도체기판의 활성 영역을 노출시키는 콘택홀을 형성하는 단계; 및 상기 콘택홀내에 콘택플러그를 형성하는 단계를 포함하여 구성된다.The present invention relates to a method of forming a contact of a semiconductor device, the method of forming a contact of a semiconductor device according to the present invention comprises the steps of: forming a trench defining an active region and an inactive region in a semiconductor substrate; Forming a trench isolation layer in the trench; Etching the trench isolation layer to form a sidewall in the trench; Forming a nitride film spacer on the sidewalls; Forming an interlayer insulating film on an upper surface of the entire structure; Forming a contact hole in the interlayer insulating film and the nitride film spacer to expose an active region of the semiconductor substrate; And forming a contact plug in the contact hole.

Description

반도체소자의 콘택 형성방법{Method for forming contact of semiconductor device} Method for forming contact of semiconductor device

도 1 내지 도 3은 종래기술에 따른 반도체소자의 콘택 형성방법을 설명하기 위한 공정별 단면도.1 to 3 is a cross-sectional view for each process for explaining a method for forming a contact of a semiconductor device according to the prior art.

도 4 내지 도 6은 본 발명에 따른 반도체소자의 콘택 형성방법을 설명하기 위한 공정별 단면도.4 to 6 are cross-sectional views for each process for explaining a method for forming a contact of a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

21 : 반도체기판 25a : 트렌치소자분리막 21 semiconductor substrate 25a trench isolation film

27 : 게이트전극 29 : 스페이서27: gate electrode 29: spacer

31 : 질화막 31a : 질화막스페이서31 nitride film 31a nitride film spacer

33 : 층간절연막 35 : 콘택홀33: interlayer insulating film 35: contact hole

37 : 콘택플러그 37: Contact Plug

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 반도체소자의 제조시에 트렌치소자분리영역과 활성영영에 형성되는 콘택의 랜딩마진을 확 보할 수 있는 반도체소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a semiconductor device capable of securing a landing margin of a contact formed in a trench isolation region and an active region during fabrication of the semiconductor device. .

종래기술에 따른 반도체소자의 콘택 형성방법을 도 1 내지 3을 참조하여 설명하면 다음과 같다.A method of forming a contact of a semiconductor device according to the prior art will now be described with reference to FIGS.

도 1 내지 도 3은 종래기술에 따른 반도체소자의 콘택 형성방법을 설명하기 위한 공정별 단면도이다.1 to 3 are cross-sectional views of processes for describing a method for forming a contact of a semiconductor device according to the related art.

종래기술에 따른 반도체소자의 콘택 형성방법은, 도 1에 도시된 바와같이, 반도체기판(1)내에 활성영역과 비활성영역을 한정하는 트렌치(미도시)를 형성한후 상기 트렌치(미도시)를 포함한 반도체기판(1)상에 절연막(미도시)을 증착한다.In the method for forming a contact of a semiconductor device according to the related art, as shown in FIG. 1, the trench (not shown) is formed after forming a trench (not shown) defining an active region and an inactive region in the semiconductor substrate 1. An insulating film (not shown) is deposited on the semiconductor substrate 1 included therein.

그다음, 상기 절연막(미도시)을 상기 트렌치(미도시)내에만 남도록 전면식각하여 트렌치소자분리막(5)을 형성한다.Next, the trench isolation layer 5 is formed by etching the entire surface of the insulating layer (not shown) so as to remain only in the trench (not shown).

이어서, 반도체기판(1)의 활성영역상에 게이트전극(7)을 형성한후 측면에 스페이서(9)를 형성하고, 스페이서(9)의 측면아래의 반도체기판(1)내에 소오스 및 드레인(미도시)을 형성하여 소자를 제조한다.Subsequently, after the gate electrode 7 is formed on the active region of the semiconductor substrate 1, the spacer 9 is formed on the side surface, and the source and drain (not shown) are formed in the semiconductor substrate 1 under the side surface of the spacer 9. To fabricate the device.

그다음, 전체 결과물상에 질화막(11)을 증착한후 상기 질화막(11)내에 상기 반도체기판의 활성영역을 노출시키는 콘택홀(13)을 형성한다. Then, after the nitride film 11 is deposited on the entire product, a contact hole 13 is formed in the nitride film 11 to expose the active region of the semiconductor substrate.

이어서, 상기 콘택홀(13)을 포함한 전체 결과물상에 도전층(미도시)을 증착한후 이를 전면식각하여 상기 콘택홀(13)내에 콘택플러그(15)을 형성한다. Subsequently, a conductive layer (not shown) is deposited on the entire product including the contact hole 13 and then etched to form a contact plug 15 in the contact hole 13.

그러나, 상기 종래기술에 의하면, 트렌치 소자분리막 및 트랜지스터를 형성한후 콘택을 형성하고자 하는 구조 전면에 질화막을 증착하여 콘택 미스얼라인을 방지하는 방법을 사용하였는데, 이 방법을 사용하면 질화막에 의한 스트레스를 소자가 받을 수 있다.However, according to the related art, a method of preventing contact misalignment by forming a trench isolation layer and a transistor and then depositing a nitride film over the entire structure to form a contact is used. Can be received by the device.

그리고, 후속 공정을 진행하기 위한 키(key) 형성 때문에 마스크층을 추가해서 키 면적(key area)의 질화막을 제거해 주었다.In addition, a mask layer was added to remove the nitride film of the key area because of key formation for the subsequent process.

또한, 질화막 스트레스로 인해 질화막의 두께에 제한을 받기 때문에 질화막이 얇을 경우, 콘택장벽 역할을 제대로 못하게 되어, 도 3에서의 "A"와 같이, 트렌치내의 소자분리막(Fox)이 공격(attack)을 받는 현상이 발생하기도 한다.In addition, when the nitride film is thin due to the nitride film stress, the nitride film is thin, so that it does not function properly as a contact barrier. As shown in FIG. 3A, the device isolation film Fox in the trench is attacked. Receiving phenomenon may occur.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 질화막이 트렌치측벽에 스페이서 형태로 남게 하여 콘택 랜딩마진을 높이므로써 별도의 키 마진(key mask) 공정이 필요없고, 스페이서 두께도 두껍게 제어가 가능하므로 콘택 오정렬 마진을 더 확보할 수 있는 반도체소자의 콘택 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, by increasing the contact landing margin by leaving the nitride film in the form of a spacer on the side wall of the trench, there is no need for a separate key mask process, spacer thickness It is an object of the present invention to provide a method for forming a contact of a semiconductor device, which can provide a thicker control and further secure a contact misalignment margin.

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 콘택 형성방법은, 반도체기판내에 활성영역과 비활성영역을 한정하는 트렌치를 형성하는 단계; 상기 트렌치내에 트렌치소자분리막을 형성하는 단계; 상기 트렌치소자분리막을 전면 식각하여 상기 트렌치내에 측벽을 형성하는 단계; 상기 측벽에 질화막스페이서를 형성하는 단계; 상기 전체 구조의 상면에 층간절연막을 형성하는 단계; 상기 층간절연막 및 질화막스페이서내에 상기 반도체기판의 활성영역을 노출시키는 콘택홀을 형성하는 단계; 및 상기 콘택홀내에 콘택플러그를 형성하는 단계를 포함하여 구성 되는 것을 특징으로한다.According to another aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, the method including: forming a trench in the semiconductor substrate to define an active region and an inactive region; Forming a trench isolation layer in the trench; Etching the trench isolation layer to form a sidewall in the trench; Forming a nitride film spacer on the sidewalls; Forming an interlayer insulating film on an upper surface of the entire structure; Forming a contact hole in the interlayer insulating film and the nitride film spacer to expose an active region of the semiconductor substrate; And forming a contact plug in the contact hole.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 콘택 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 4 내지 도 6은 본 발명에 따른 반도체소자의 콘택 형성방법을 설명하기 위한 공정단면도이다.4 to 6 are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 콘택 형성방법은, 도 4에 도시된 바와같이, 먼저 반도체기판(21)내에 활성영역과 비활성영역을 한정하는 트렌치(미도시)를 형성한후 상기 트렌치(미도시)를 포함한 반도체기판(21)상에 절연막(미도시)을 증착한다.In the method for forming a contact of a semiconductor device according to the present invention, as shown in FIG. 4, first, a trench (not shown) defining an active region and an inactive region is formed in the semiconductor substrate 21, and then the trench (not shown). An insulating film (not shown) is deposited on the semiconductor substrate 21 including.

그다음, 상기 절연막(미도시)을 상기 트렌치(미도시)내에만 남도록 전면식각하여 트렌치소자분리막(25a)을 형성한다.Next, the trench isolation layer 25a is formed by etching the entire surface of the insulating layer (not shown) so as to remain only in the trench (not shown).

이어서, 반도체기판(21)의 활성영역상에 게이트전극(27)을 형성한후 측면에 스페이서(29)를 형성하고, 스페이서(29)의 측면아래의 반도체기판(21)내에 소오스 및 드레인(미도시)을 형성하여 소자를 제조한다.Subsequently, after the gate electrode 27 is formed on the active region of the semiconductor substrate 21, the spacer 29 is formed on the side surface, and the source and drain (not shown) are formed in the semiconductor substrate 21 under the side surface of the spacer 29. To fabricate the device.

그다음, 도면에는 도시하지 않았지만, 소자 제조후 상기 트렌치 소자분리막 (25a)을 전면 식각하여 상기 트렌치소자분리막(25a)을 일정 두께만큼 제거하여 측벽 (미도시) 을 형성한다. Next, although not shown in the drawing, after the fabrication of the device, the trench isolation layer 25a is etched entirely to remove the trench isolation layer 25a by a predetermined thickness to form sidewalls (not shown).

이어서, 도 5에 도시된 바와같이, 일정 두께만큼 제거된 트렌치소자분리막 (25a)을 포함한 전체 결과물상에 질화막(31)을 증착한후 상기 질화막(31)을 전면식 각 하여 트렌치소자분리막(25a)의 측벽에 질화막스페이서(31a)을 형성한다.Subsequently, as illustrated in FIG. 5, after the nitride film 31 is deposited on the entire product including the trench device isolation film 25a removed by a predetermined thickness, the nitride device 31 is etched and the trench device isolation film 25a is etched. The nitride film spacers 31a are formed on the sidewalls of the substrate.

그다음, 상기 전체 구조의 상면에 층간절연막(33)을 증착한후 이를 선택적으로 패터닝하여 상기 반도체기판(21)의 활성영역을 노출시키는 콘택홀(35)을 형성한다. 이때, 상기 콘택홀(35)은 상기 질화막스페이서(31a)에 의해 오정렬 마진을 확보할 수 있어 오정렬에 의한 트렌치 소자분리막 측벽 공격(attack)을 방지할 수 있다.Next, an interlayer insulating layer 33 is deposited on the upper surface of the entire structure, and then selectively patterned to form a contact hole 35 exposing an active region of the semiconductor substrate 21. In this case, the contact hole 35 may secure a misalignment margin by the nitride film spacer 31a, thereby preventing sidewall attack of the trench isolation layer due to misalignment.

이어서, 상기 콘택홀(35)을 포함한 전체 결과물상에 도전층(미도시)을 증착한후 이를 전면식각하여 상기 콘택홀(35)내에 콘택플러그(37)을 형성하고 이어 후속공정을 진행한다. Subsequently, a conductive layer (not shown) is deposited on the entire product including the contact hole 35 and then etched to form a contact plug 37 in the contact hole 35, and then a subsequent process is performed.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 콘택 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the method for forming a contact of a semiconductor device according to the present invention has the following effects.

본 발명에 따른 반도체소자의 콘택 형성방법에 의하면, 반도체기판의 활성영역에 형성된 콘택은 질화막 스페이서에 의해 오정렬 마진을 갖게 되어 안정적인 공정진행이 가능하다. 즉, 콘택홀의 오정렬 마진을 확보할 수 있어 오정렬에 의한 트렌치 소자분리막 측벽 공격(attack)을 방지할 수 있다.According to the method for forming a contact of a semiconductor device according to the present invention, the contact formed in the active region of the semiconductor substrate has a misalignment margin by the nitride film spacer, thereby allowing stable process progression. That is, the misalignment margin of the contact hole can be secured, thereby preventing the trench isolation layer sidewall attack caused by the misalignment.

또한, 콘택을 형성하기 위해 형성하는 질화막을 트렌치소자분리막 측벽에만 남도록 하므로써, 질화막이 전면에 증착되어 있는 기존의 기술에 비해 질화막 스트레스를 줄일 수 있다.In addition, since the nitride film formed to form the contact remains only on the sidewalls of the trench isolation layer, the nitride film stress can be reduced as compared with the conventional technology in which the nitride film is deposited on the entire surface.

그리고, 질화막 증착 두께를 조절하여 스페이서 두께 조절이 가능하므로 오 정렬 마진의 제어가 용이하다.In addition, since the thickness of the spacer may be adjusted by adjusting the thickness of the nitride film deposition, the misalignment margin is easily controlled.

더욱이, 후속공정을 위해 키면적(key area)를 개구시켜 주었던 키오픈 마스크, 식각공정, PR 제거공정 등을 없앨 수 있어 공정 단순화 차원에서 이득이 있다.In addition, it is possible to eliminate key open masks, etching processes, PR removal processes, etc., which have opened key areas for subsequent processes, which is advantageous in terms of process simplification.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (2)

반도체기판내에 활성영역과 비활성영역을 한정하는 트렌치를 형성하는 단계;Forming a trench in the semiconductor substrate, the trench defining an active region and an inactive region; 상기 트렌치내에 트렌치소자분리막을 형성하는 단계;Forming a trench isolation layer in the trench; 상기 트렌치소자분리막을 전면 식각하여 상기 트렌치내에 측벽을 형성하는 단계;Etching the trench isolation layer to form a sidewall in the trench; 상기 측벽에 질화막스페이서를 형성하는 단계;Forming a nitride film spacer on the sidewalls; 상기 전체 구조의 상면에 층간절연막을 형성하는 단계; Forming an interlayer insulating film on an upper surface of the entire structure; 상기 층간절연막 및 질화막스페이서내에 상기 반도체기판의 활성영역을 노출시키는 콘택홀을 형성하는 단계; 및Forming a contact hole in the interlayer insulating film and the nitride film spacer to expose an active region of the semiconductor substrate; And 상기 콘택홀내에 콘택플러그를 형성하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 콘택 형성방법.And forming a contact plug in the contact hole. 제1항에 있어서, 상기 트렌치의 측벽에 스페이서를 형성하는 단계는, 먼저 전면식각된 트렌치소자분리막을 포함한 전체 구조상에 질화막을 증착한후 상기 질화막을 상기 트렌치의 측벽에만 남도록 전면식각하여 스페이서를 형성하는 것을 특징으로하는 반도체소자의 콘택 형성방법.The method of claim 1, wherein the forming of the spacer on the sidewalls of the trench comprises first depositing a nitride film on the entire structure including the front-etched trench isolation layer, and then etching the nitride film on the sidewall of the trench to form a spacer. A contact forming method of a semiconductor device, characterized in that.
KR1020010088961A 2001-12-31 2001-12-31 Method for forming contact of semiconductor device KR100783636B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980012244A (en) * 1996-07-19 1998-04-30 김광호 Method for manufacturing semiconductor device
KR19990010199A (en) * 1997-07-15 1999-02-05 윤종용 Trench element isolation formation method of semiconductor device
KR20000044279A (en) * 1998-12-30 2000-07-15 윤종용 Apparatus for controlling memorandum function of cellular phone
KR20000076468A (en) * 1999-02-05 2000-12-26 포만 제프리 엘 Expansion unit for information processing system, information processing system mountable on expansion unit, and presence management method of information processing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980012244A (en) * 1996-07-19 1998-04-30 김광호 Method for manufacturing semiconductor device
KR19990010199A (en) * 1997-07-15 1999-02-05 윤종용 Trench element isolation formation method of semiconductor device
KR20000044279A (en) * 1998-12-30 2000-07-15 윤종용 Apparatus for controlling memorandum function of cellular phone
KR20000076468A (en) * 1999-02-05 2000-12-26 포만 제프리 엘 Expansion unit for information processing system, information processing system mountable on expansion unit, and presence management method of information processing system

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