KR0157975B1 - Stack capacitor fabrication method - Google Patents
Stack capacitor fabrication method Download PDFInfo
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- KR0157975B1 KR0157975B1 KR1019890009235A KR890009235A KR0157975B1 KR 0157975 B1 KR0157975 B1 KR 0157975B1 KR 1019890009235 A KR1019890009235 A KR 1019890009235A KR 890009235 A KR890009235 A KR 890009235A KR 0157975 B1 KR0157975 B1 KR 0157975B1
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- layer
- poly
- depositing
- lto
- capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
내용없음.None.
Description
제1a도 내지 제1d도는 종래의 캐패시터 제조공정을 나타낸 도면.1a to 1d is a view showing a conventional capacitor manufacturing process.
제2a도 내지 제2g도는 본 발명의 캐패시터 제조공정을 나타낸 도면.2a to 2g is a view showing a capacitor manufacturing process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
9 : 질화층 17 : 제2폴리-Ⅱ층9: nitride layer 17: second poly-II layer
11 : 제1매립접촉부 13 : 제1폴리-Ⅱ층11: first buried contact portion 13: first poly-Ⅱ layer
14 : LTO 15 : 제2매립접촉부14: LTO 15: Second buried contact
18 : 유전체층 19 : 폴리-Ⅲ층18 dielectric layer 19 poly-III layer
본 발명은 반도체 제조공정중 캐패시터 제조방법에 관한 것으로 특히 고성능 소자에 적당하도록 집적회로의 스택트(stacted)캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor during a semiconductor manufacturing process, and more particularly, to a method of manufacturing a stacked capacitor of an integrated circuit to be suitable for high performance devices.
종래의 제조공정은 제1a도 내지 제1d도에서 보는 바와 같이 게이트와 스토리지(storage)노드의 절연을 위해 저온산화(LTO) 증착(제1a도)을 하고, 활성영역과 스토리지 노드를 연결하기 위한 매립접촉부(3)를 형성하도록 에칭을 한다(제1b도). 이어서, 적층노드가 될 폴라-Ⅱ(4)를 증착하여, 그 영역을 정의하고(제1c도), 캐패시터를 형성하기 위한 유전재료(5) 증착후 캐패시터의 전극판이 될 폴리-Ⅲ(6)를 증착하여 형성된다.Conventional fabrication processes include low temperature oxidation (LTO) deposition (FIG. 1A) for isolation of gate and storage nodes, as shown in FIGS. 1A-1D, and connection of active regions and storage nodes. Etching is performed to form the buried contact portion 3 (FIG. 1B). Next, the poly-III (6), which is to be the electrode plate of the capacitor, is deposited after depositing the polar-II (4) to be a stacked node, defining its region (Fig. 1C), and forming the capacitor. It is formed by depositing.
본 직접회로의 집적도를 높이는데 있어서 캐패시터의 면적을 넓히는 것은 필수적인데, 종래 제조 공정에 있어서 필드 산화물상에 형성되는 캐패시터가 이에 인접한 캐패시터와 접촉되지 않도록 하여야 하기 때문에 면적을 넓히는데 문제점이 있다.In order to increase the integration density of the integrated circuit, it is essential to increase the area of the capacitor. However, in the conventional manufacturing process, the capacitor formed on the field oxide should not be in contact with the capacitor adjacent thereto.
따라서 상기기술된 종래의 문제점을 해결하기위한 스택트 캐패시터 제조방법을 제공하는데 본 발명의 목적이 있다.Accordingly, it is an object of the present invention to provide a stack capacitor manufacturing method for solving the above-described conventional problems.
본 발명이 제공하는 방법을 첨부한 도면 제2도를 참조하여 설명한다.A method provided by the present invention will be described with reference to FIG. 2.
먼저, 제2a도와 같이 필드산화층(2)이 형성된 반도체상에 활성 영역과 스토리지 노드간 절연을 위한 LTO대신에 Si3N4의 질화층(9)을 증착시킨다. 그리고 제2b도와 같이 포토레지스트(12)를 도포하여 참조부호 11과 같이 제1의 매립접촉부(11)를 에칭하여 정의한다. 이때 모든 셀에 대해 정의하지 않고 동도면과 같이 격셀단위로 필드산화층 사이에 상기 접촉부(11)를 형성시킨다. 이어서 제2c도와 같이 제2b도의 PR층을 제거하고 그 위에 스토리지노드로 사용될 제1의 폴리-Ⅱ(13)을 증착한 후, 매립접촉부가 형성되지 아니한 셀부분에까지 상기 제1의 폴리-Ⅱ층을 잔유케하고(즉, 필드 산화층 대부분을 상기 제1의 폴리-Ⅱ층이 덮는다), 매립접촉부가 형성되지 않은 부분만 정의한다.First, as shown in FIG. 2A, a nitride layer 9 of Si 3 N 4 is deposited on the semiconductor on which the field oxide layer 2 is formed, instead of the LTO for insulation between the active region and the storage node. As shown in FIG. 2B, the photoresist 12 is coated to define the first buried contact portion 11 as shown in reference numeral 11. At this time, the contact portion 11 is formed between the field oxide layers in every cell unit as shown in FIG. Subsequently, as shown in FIG. 2C, the PR layer of FIG. 2B is removed and the first poly-II (13) to be used as a storage node is deposited thereon, and then the first poly-II layer is added to the cell portion where the buried contact is not formed. (I.e., the first poly-II layer covers most of the field oxide layer) and defines only the portion where the buried contact is not formed.
이 형성체위에 제2d도와 같이 LTO(14)를 증착한 후, 매립접촉부가 형성되지 아니한 영역의 셀부분에 대해서도 제2의 매립접촉부(15)를 형성한다. 이어서 제2e도와 같이 제2의 폴리-Ⅱ(17)을 증착한 후, 이 증착된 폴리-Ⅱ가 필드산화층 대부분을 덮을 수 있도록 정의한다. 그리고, 제2f도와 같이, 습식엣치를 사용하여 제2e도의 LTO(14)도 스트립시켜 제거한다. 그리고 최종적으로, 제2g도와 같이 유전체층(18) 및 전극판이 될 폴리-Ⅲ(19)을 증착하여 본 발명의 집적회로의 스택트 캐패시터가 제조형성된다.After the LTO 14 is deposited on the formed body as shown in FIG. 2D, the second buried contact portion 15 is also formed in the cell portion in the region where the buried contact portion is not formed. Subsequently, the second poly-II (17) is deposited as shown in FIG. 2E, and then the deposited poly-II is defined to cover most of the field oxide layer. As shown in Fig. 2f, the LTO 14 of Fig. 2e is also stripped and removed using a wet etch. Finally, as shown in FIG. 2G, the dielectric layer 18 and the poly-III 19 to be the electrode plate are deposited to form a stacked capacitor of the integrated circuit of the present invention.
이미 서술한 종래에서 보듯이 필스 산화층 윗부분의 폴리-Ⅱ층이 인접한 셀의 폴리-Ⅱ층과 접촉되고 이 부분의 폴리-Ⅱ가 필드산화층 일부만 덮으므로 이로 인해 면적 형성이 협소하나, 본 발명에서는 인접셀의 폴리-Ⅱ층을 부유시켜 하나의 캐패시터의 폴리-Ⅱ층이 필드 산화층 대부분을 덮게 되므로 캐패시터 면적이 증대된다.As shown in the related art, the poly-II layer on the top of the oxide layer is in contact with the poly-II layer of the adjacent cell and the area of the poly-II layer covers only a part of the field oxide layer. By floating the poly-II layer of the cell, the poly-II layer of one capacitor covers most of the field oxide layer, thereby increasing the capacitor area.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890009235A KR0157975B1 (en) | 1989-06-30 | 1989-06-30 | Stack capacitor fabrication method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890009235A KR0157975B1 (en) | 1989-06-30 | 1989-06-30 | Stack capacitor fabrication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910001931A KR910001931A (en) | 1991-01-31 |
| KR0157975B1 true KR0157975B1 (en) | 1998-12-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019890009235A KR0157975B1 (en) | 1989-06-30 | 1989-06-30 | Stack capacitor fabrication method |
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| Country | Link |
|---|---|
| KR (1) | KR0157975B1 (en) |
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1989
- 1989-06-30 KR KR1019890009235A patent/KR0157975B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR910001931A (en) | 1991-01-31 |
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