CN1112288A - Method for manufacturing T-shaped grid on surface of semiconductor - Google Patents
Method for manufacturing T-shaped grid on surface of semiconductor Download PDFInfo
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- CN1112288A CN1112288A CN 95101600 CN95101600A CN1112288A CN 1112288 A CN1112288 A CN 1112288A CN 95101600 CN95101600 CN 95101600 CN 95101600 A CN95101600 A CN 95101600A CN 1112288 A CN1112288 A CN 1112288A
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- gate electrode
- ground floor
- shape gate
- groove hole
- floor material
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 12
- 239000011810 insulating material Substances 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- 235000012239 silicon dioxide Nutrition 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 238000004377 microelectronic Methods 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 2
- 230000003287 optical effect Effects 0.000 abstract description 2
- 239000012790 adhesive layer Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 238000001015 X-ray lithography Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000002164 ion-beam lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000007039 two-step reaction Methods 0.000 description 1
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Abstract
The invention discloses a method for manufacturing a T-shaped gate electrode on the surface of a semiconductor, which is suitable for the production of microelectronic devices such as HEMT and the like. The method includes the steps of digging a groove on an adhesive layer on the surface of a semiconductor according to the top width of a T-shaped electrode, forming a dielectric side wall in the groove by deposition and directional etching methods, depositing metal, and stripping the adhesive layer and the metal layer outside a gate region to leave a final T-shaped gate electrode. The invention can process the pattern with wider T-shaped top size to obtain thinner electrode bottom surface. It can be processed with a slightly wider lithographic dimension to achieve a gate length approaching the optical limit.
Description
The present invention relates to a kind of method that in the middle of production high mobility transistor (HEMT) and metal-semiconductor field effect transistor microelectronic components such as (MESFET), adopts at semiconductor surface manufacturing T shape gate electrode.
In the middle of the development of microelectronic components such as existing HEMT and MESFET, for characteristics such as the frequency that improves them and noise factors, it is long to require to shorten grid as possible on the one hand, reduce the electric capacity between grid and source, the leakage, make every effort to reduce resistance and grid source resistance on the other hand again, the gate electrode structure that is called " T shape grid " or " Mushroom Gate " (following general designation " T shape grid " structure) of prior art exploitation, above-mentioned development requirement produces in order to adapt to just.
Have the method for making T shape gate electrode at semiconductor surface now, as previously proposing by people such as P.Chao, at the two-layer or three layers of glue-line that the electron beam sensitive degree is differed of semiconductor surface coating, narrow cavity at the bottom of the generation top width after electron beam exposure develops, just form T shape gate electrode (" Electron Beam Fabrication of GaAs Low-Noise MESFET Using a New Trilayer Resist Technique " after removing whole glue-lines through depositing metal and with lift-off technology again at semiconductor surface, IEEE Transactions on Electron Devices, Vol.ED-32, No.6, Jun.1985, pp1042-1046).Obviously, this technology only is applicable to the technology of electron beam graphics processing.The employing tri-layer masking system that U.S. Pat 5155053 proposes produces narrow cavity at the bottom of the top width in conjunction with isotropism and anisotropic two-step reaction ion etching, subsequently equally again through depositing metal and lift-off mask formation T shape gate electrode.It must adopt the meticulous design size at the narrow end of T shape gate electrode in the glue mask pattern processing against corrosion of end face.Although this patent is claimed the figure manufacturing process that this technology is suitable for and is comprised broad range such as focused ion beam, electron beam, light beam and X ray, yet, if adopt means of photolithography processing, owing to be subjected to the constraint of litho pattern size, the limit that makes the bottom width of T shape gate electrode be difficult to approach 1/2 optical wavelength.Although in the figure process technology that microelectronics is produced so far, means such as focused ion beam, electron beam and X ray have clear superiority aspect fineness, but because their cost costliness and operating efficiency are low, limited their extensive use, particularly influence their a large amount of being applied to and carry out direct figure processing in the microelectronic product manufacturing, photoetching technique was both cheap and easy and simple to handle, was still the means that at present a large amount of microelectronic products (comprising many high-performance new products) are still needed and relied in directly figure is processed.Continue the ultimate precision that utilizes photoetching technique and try hard to realize it, make microelectronic product can keep lower cost and higher production efficiency, can obtain satisfied performance again, be still the target that the present stage people are pursued.
Purpose of the present invention is exactly in order to realize above-mentioned pursuit, will adopt the bottom width of the narrower T shape gate electrode of figure processing dimension realization of broad in microelectronic components such as HEMT and MESFET are made, the figure processing dimension of allowing with photoetching technique realizes than meticulousr T shape gate electrode bottom width.
Realize that the technical measures that purpose of the present invention is taked are, the step that method comprised that the present invention makes T shape gate electrode at semiconductor surface is: 1. sprawl the ground floor material at semiconductor surface, its thickness is no more than the predetermined altitude of T shape gate electrode; 2. form in the ground floor material that 1. step is sprawled according to the preliminary dimension of T shape gate electrode end face and dig through holostrome or dig the groove hole of staying the part bed thickness; 3. at deposit second layer insulating material on the ground floor material and in the groove hole that is 2. forming through step; 4. with the anisotropic etching method along removing perpendicular to the direction of semiconductor surface at the ground floor material surface and at the second layer insulating material of groove hole bottom deposit, stay through step ground floor material and the inwall groove hole that attaches second layer insulating material 2.; 5. the semiconductor surface at T shape gate electrode formation position is exposed at the bottom of making the ground floor material attenuate of staying outside the groove hole and making the groove hole; 6. depositing conductive material inside and outside the groove hole; 7. peel off whole ground floor materials and at the electric conducting material of its surface deposition from semiconductor surface.
Method of the present invention is to carry out figure processing and grooving by the end face design size of T shape gate electrode broad in 2. in step, and through step 7. after, owing to there is insulative sidewall to fill, make that what form at semiconductor surface is the T shape grid that has than the meticulousr bottom surface of end face size.Can be applicable to multiple figure process technologies such as focused ion beam, electron beam, X ray and optical lithography on the methodological principle of the present invention, and all have and to make the meticulousr effect of T shape gate electrode bottom more used figure processing dimension self, but if adopt optical lithography techniques, in the size range that optical lithography techniques is allowed, carry out figure processing, can make the bottom width of T shape grid approach the ultimate precision of optics, this is low cost, high efficiency for realizing, be again microelectronic component production, have more Special Significance with superior performance.
Below in conjunction with drawings and Examples the method that the present invention makes T shape gate electrode at semiconductor surface is further described in detail.
Fig. 1 to Fig. 8 is one embodiment of the present invention is made T shape gate electrode at semiconductor surface a generalized section step by step.
Fig. 9 to Figure 16 is another embodiment of the present invention makes T shape gate electrode at semiconductor surface a generalized section step by step.
The initial step that Fig. 1 illustrates one embodiment of the present invention is at Semiconductor substrate (1) surface (2) coating one deck photoresist (3), Semiconductor substrate (1) is that the GaAs sheet of making the HEMT microelectronic component is specialized in processing through molecular beam epitaxy, about 0.6 micron of the thickness of photoresist (3) is equivalent to the design height of T shape gate electrode.Fig. 2 illustrates and uses the photoetching process graphics processing subsequently, go up the groove hole (3a) that produces the break-through holostrome at photoresist layer (3), about 0.5 micron of the width of cave entrance in groove hole (3a), the top width design load that is equivalent to T shape gate electrode, Fig. 3 shows through use plasma reinforced chemical vapor deposition method (PECVD) deposit SiO under 150 ℃ of temperature
2The back covers the SiO of about 0.3 micron thickness of one deck in photoresist layer (3) and bottom, groove hole (3a)
2Layer (4) attaches the SiO of about 0.15 micron thickness at groove hole (3a) inwall
2(4a).Fig. 4 illustrate through with the reactive ion etching technology of carbon tetrafluoride gas to SiO
2Layer carries out after the anisotropic etching, all is deposited on the photoresist (3) and the SiO of bottom surface, groove hole (3a) in the direction removal perpendicular to semiconductor substrate surface (2)
2Layer (4) only stays the SiO that is attached to about 0.15 micron thickness of groove hole (3a) inwall
2Layer (4a).Fig. 5 illustrates through dry etching photoresist (3) is thinned to about 0.2 micron, and the bondline thickness of removal is greater than 0.2 micron T shape gate electrode end face design thickness.Fig. 6 illustrates with wet etching and removes the low resistance ohmic contact layer on base semiconductor substrate surface, groove hole (3a) (2) and form shallow slot grid region (5).Fig. 7 illustrates titanium and the gold layer (6) that adopts evaporation technique to cover 0.2 micron of one deck on whole surface.Fig. 8 illustrates through removing photoresist and peel off grid region metal in addition, the about 0.2 micron T shape gate electrode (6a) of bottom width that stays on the surface, shallow slot grid region (5) of Semiconductor substrate (1) with stripping solution being molten.
The step of used Semiconductor substrate of another embodiment of the present invention (1) and initial coating photoresist (3) is identical with last embodiment, also as shown in Figure 1, subsequently as shown in Figure 9 through using the photoetching graphics processing, on photoresist layer (3), dig out the about 0.4 micron groove hole (3a ') of the degree of depth of not break-through, the width of cave entrance in groove hole (3a ') also is the design load of 0.5 micron T shape gate electrode top width, and Figure 10 illustrates the SiO that then goes up about 0.3 micron thickness of deposit under 150 ℃ of temperature with the PECVD technology at whole photoresist layers (3)
2Layer (4) attaches the SiO of about 0.15 micron thickness at groove hole (3a ') inwall
2(4a ').Figure 11 illustrate through with the reactive ion etching technology of carbon tetrafluoride gas to SiO
2Layer (4) carries out after the anisotropic etching, at the SiO that goes perpendicular to the direction of substrate surface (2) on the clean glue-line (3)
2(4), only stay and be attached to the about 0.15 micron SiO of groove hole (3a ') inwall
2(4a ').Figure 12 illustrates with dry etching and removes the glue-line of bottom, clean groove hole (3a ') and make the outer glue-line (3) in groove hole (3a ') be thinned to 0.3 micron.Figure 13 illustrates the low resistance ohmic contact layer of removing base semiconductor surface, groove hole (3a ') (2) with wet etching, stays shallow slot grid region (5).Figure 14 illustrates titanium and the gold layer (6) that adopts evaporation technique to cover 0.2 micron of one deck on whole surface.Figure 15 illustrates through removing photoresist (3) and peel off grid region metal in addition with stripper being molten, stays the about 0.2 micron T shape gate electrode (6a ') of bottom width on the surface, shallow slot grid region (5) of Semiconductor substrate (1).
Two embodiment of the present invention can be respectively with the version of Fig. 8 and Figure 15 final form as semiconductor surface T shape gate electrode, also can remove the SiO that in manufacture process, forms as required
2Sidewall (4a, 4a ') becomes final structure form shown in Figure 16.
Claims (8)
1, a kind of method at semiconductor surface manufacturing T shape gate electrode is characterized in that the manufacturing step that it comprises has:
1. sprawl the ground floor material at described semiconductor surface, its thickness is no more than the predetermined altitude of described T shape gate electrode;
2. form in the ground floor material according to the predetermined end face width of described T shape gate electrode and dig through holostrome or dig the groove hole of staying the part bed thickness;
3. at deposit second layer insulating material on the ground floor material and in formed groove hole;
4. with the anisotropic etching method along removing perpendicular to the direction of described semiconductor surface at the ground floor material surface and at the second layer insulating material of groove hole bottom deposit, the second layer insulating material on the sidewall of reserved slit hole;
5. make the ground floor material attenuate outside the groove hole, and the predetermined semiconductor surface that forms the position of described T shape gate electrode exposes at the bottom of making the groove hole;
6. depositing conductive material inside and outside the groove hole;
7. peel off whole ground floor materials and at the electric conducting material of ground floor material surface deposit from described semiconductor surface.
2, according to the method for the described manufacturing of claim 1 T shape gate electrode, it is characterized by, 2. described step forms the groove hole of digging through holostrome for the predetermined end face width according to described T shape gate electrode in the ground floor material.
3, according to the method for the described manufacturing of claim 1 T shape gate electrode, it is characterized by, 2. described step digs the groove hole of staying the part bed thickness for the predetermined end face width according to described T shape gate electrode forms in the ground floor material.
4, according to the method for the described manufacturing of claim 1 T shape gate electrode, it is characterized by, described semiconductor is that the semiconductor wafer of making High Electron Mobility Transistor is specialized in processing through molecular beam epitaxy, and 5. described step comprises thin step:
ⅰ) make in ground floor material attenuate outside the described groove hole and the described groove of the Ex-all hole and keep or residual described ground floor material;
ⅱ) the low resistance ohmic contact layer of described semiconductor wafer surface in the described groove of the removal hole.
5, according to the method for the described manufacturing of claim 1 T shape gate electrode, it is characterized by, the described ground floor material of sprawling in 1. in step is a photoresist, and described to form the groove hole in step in 2. be with photoetching technique formation groove hole.
6, according to the described method of making T shape gate electrode of claim 1, it is characterized by, described step 3. in deposit second layer insulating material be with chemical vapor deposition method deposit silicon dioxide, it is described that to remove second layer insulating material with the anisotropic etching method in step in 4. be that the reactive ion anisotropic etching technology of usefulness carbon tetrafluoride gas is removed silicon dioxide layer.
7, according to the method for the described manufacturing of claim 1 T shape gate electrode, it is characterized by, described step 5. in depositing conductive material be usefulness evaporation technique deposit titanium and gold.
8, according to the method for claim 4 with 5 described manufacturing T shape gate electrodes, it is characterized by, described at described step thin step ⅰ 5.) in attenuate and Ex-all ground floor material be with dry etching technology attenuate and the described photoresist layer of Ex-all, described at described step thin step ⅱ 5.) in removal low resistance ohmic contact layer carry out with the wet etching technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 95101600 CN1112288A (en) | 1995-02-21 | 1995-02-21 | Method for manufacturing T-shaped grid on surface of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 95101600 CN1112288A (en) | 1995-02-21 | 1995-02-21 | Method for manufacturing T-shaped grid on surface of semiconductor |
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| Publication Number | Publication Date |
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| CN1112288A true CN1112288A (en) | 1995-11-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 95101600 Pending CN1112288A (en) | 1995-02-21 | 1995-02-21 | Method for manufacturing T-shaped grid on surface of semiconductor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1048354C (en) * | 1996-05-03 | 2000-01-12 | 电子工业部第十三研究所 | T shape grid making method for semiconductor device |
| CN1110065C (en) * | 2000-04-05 | 2003-05-28 | 信息产业部电子第十三研究所 | Method for automatically aligning grid cap to grid foot of T-shaped grid of smeicondctor device |
| CN109935630A (en) * | 2017-12-15 | 2019-06-25 | 苏州能讯高能半导体有限公司 | Semiconductor devices and its manufacturing method |
| CN112509912A (en) * | 2021-02-03 | 2021-03-16 | 成都市克莱微波科技有限公司 | Preparation method of semiconductor device |
-
1995
- 1995-02-21 CN CN 95101600 patent/CN1112288A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1048354C (en) * | 1996-05-03 | 2000-01-12 | 电子工业部第十三研究所 | T shape grid making method for semiconductor device |
| CN1110065C (en) * | 2000-04-05 | 2003-05-28 | 信息产业部电子第十三研究所 | Method for automatically aligning grid cap to grid foot of T-shaped grid of smeicondctor device |
| CN109935630A (en) * | 2017-12-15 | 2019-06-25 | 苏州能讯高能半导体有限公司 | Semiconductor devices and its manufacturing method |
| CN112509912A (en) * | 2021-02-03 | 2021-03-16 | 成都市克莱微波科技有限公司 | Preparation method of semiconductor device |
| CN112509912B (en) * | 2021-02-03 | 2021-04-30 | 成都市克莱微波科技有限公司 | Preparation method of semiconductor device |
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