JPS62299033A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a gate resistance and a flinging capacitance between a gate and a source by employing a multilayer resist structure. CONSTITUTION:An organic or inorganic insulating layer 2, 1st resist layer 3, an intermediate layer 4 made of metal such as silicon oxide and 2nd resist layer 5 are successively formed on a semiconductor substrate 1. Etching is performed with a pattern formed by exposing and developing the 2nd resist layer 5 to form a predetermined pattern in the intermediate layer 4 and, further, an aperture is formed in the 1st resist layer 3 to expose the organic or inorganic insulating layer 2 and the semiconductor substrate 1 surface. Then the semicon ductor substrate 1 surface is etched or subjected to a surface treatment and coated with 3rd resist layer 6 and one side of the part above the 1st resist layer 3 is removed and, at the same time, an electrode metal layer 7 is formed on the exposed semiconductor substrate 1, the organic or inorganic insulating layer 2 and the intermediate layer 4 by a coating method with orientation applied from the above. Further, the unnecessary part of the electrode metal layer 7, intermediate layer 4, 1st resist layer 3 and organic or inorganic insulat ing layer 2 are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device made of a compound semiconductor.

[Conventional technology]

In recent years, the performance of semiconductor devices has improved, and the Ka band (26,5
~40G II z) and U band (40~60GHz)
Semiconductor devices that operate under such conditions have appeared, and the constraints on parameters parasitic to semiconductor devices have become stricter. In particular, in recent years, reducing the gate length has been gaining popularity in order to reduce noise, but on the other hand, reducing the gate length increases the gate resistance, which is an obstacle to reducing the noise.

In order to simplify the explanation, gallium arsenide (GaAs) will be used as a semiconductor, and an MES and an FET with a Schottky gate structure will be used as semiconductor devices.

J.M. Moran and Maydan, Journal of Vacuum Science and Technology, published in 1979.
As shown in Figures 3 (a) to (c) on page 1620 of 5 Science and Technology), GaAs MES-
This shows the manufacturing method of the gate part of the FET. Figure 3<a>
As shown in FIG. 1, a resin layer 12 is coated sufficiently thickly on a Ga substrate 11, and then a coatable SiO□ intermediate layer 13 is provided.
Furthermore, a resist layer 14 is provided thereon. Next, as shown in FIG. 3(b), the resist layer 14 is exposed to light, and a predetermined pattern 3 is formed on the intermediate layer 13 by etching.
Furthermore, after removing the resin layer 12 by etching so that the opening size is larger than the pattern of the intermediate layer 13,
The exposed Ga layer 11 is etched and the Ga layer 11 is etched.
Person J from the normal direction of the board 11? Deposit layer 15. Next, as shown in FIG. 3(c), by removing the resin layer, a gate electrode can be formed.

[Problem that the invention seeks to solve]

With the above-mentioned conventional technology, it is possible to form a gate with a gate length of 0.2 μm, which is high in the height direction and has low resistance. Gate metal adheres to the intermediate layer opening, and as the gate length is shortened, it becomes impossible to reduce the gate resistance.

The applicant has considered ways to improve these problems, and has
MES-FE with (gamma) shaped gate electrode
T was developed and filed as Japanese Patent Application No. 60-061331. Since the upper part of the gate electrode can protrude only on one side, it is possible to reduce the gate parasitic resistance, which has been a problem in the past, and to reduce the fringing capacitance between the gate and the source. However, with conventional manufacturing methods, it is difficult to form a gate electrode that protrudes only on one side, and it is difficult to further reduce the distance between the source and the gate, making it impossible to significantly reduce the fringing capacitance.

The purpose of the present invention is to eliminate such drawbacks of the prior art,
While maintaining the above-mentioned advantages of the conventional technology, the gate resistance is reduced, the fringing capacitance between the gate and the source is reduced, and a gate electrode with a fine gate length of 0.25 μm or less is formed, resulting in high frequency characteristics. An object of the present invention is to provide a method for manufacturing a semiconductor device made of a compound semiconductor, which has improved properties.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes sequentially forming an organic or inorganic insulating layer, a first resist layer, a thin intermediate layer of silicon oxide, silicon nitride, polycrystalline silicon, or a metal such as aluminum on a semiconductor substrate, and forming a thin intermediate layer of a metal such as silicon oxide or silicon nitride or polycrystalline silicon or aluminum. exposing and developing the second resist layer to form a pattern having openings, etching using the pattern to form a predetermined pattern in the intermediate layer, and further etching. a step of opening the first resist layer to expose the organic or inorganic insulating layer, and further etching to expose the surface of the semiconductor substrate; a step of etching or surface-treating the exposed surface of the semiconductor substrate; A process of applying a resist layer, exposing and developing the third and first resist layers, and removing the area above the first resist layer forming a pattern on one side, and a directional deposition method from above. A step of depositing an electrode metal layer on the exposed semiconductor substrate, an organic or inorganic insulating layer, and an intermediate layer, removing unnecessary electrode metal layers, and then depositing an electrode metal layer on the exposed semiconductor substrate, an organic or inorganic insulating layer, and an intermediate layer; The method includes a step of removing an insulating layer.

[Effect]

The method for manufacturing a semiconductor device of the present invention uses a multilayer resist structure to reduce the influence of steps etc. on gate formation in the previous process, and improves the etching or surface treatment region on the surface of the semiconductor substrate and the dimension where the semiconductor surface and gate electrode contact each other. By determining the (gate length), removing one side of the resist layer by exposure and development, and directional deposition of metal, it is possible to have a (gamma)-shaped cross section, with the upper part of the electrode protruding only on one side. The feature is that it is possible.

Thus, according to the present invention, gate parasitic resistance and gate-source fringing capacitance, which are particularly problematic, can be reduced.
Moreover, a semiconductor device having a gate length of 0.2 μm or less can be obtained.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1A to 1F are cross-sectional views of a gate portion of a device shown in order of steps to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.

In this example, for convenience of explanation, GaAs-MES・F
ET will be explained.

First, as shown in FIG. 2(a), a resin layer 2 (for example, photoresist coated and baked in nitrogen gas at 250° C. for 1 hour) with a thickness of 1000 mm is placed on a semiconductor GaAs substrate 1. and then a first resist layer 3 with a thickness of 1 μm.
(e.g. PMMA), then a thickness of about 1000
A coatable SiO□ layer 4 (for example, a silicon compound dissolved in an organic solvent such as alcohol, spin-coated and baked) is provided as an intermediate layer, and a second layer for patterning is formed on it. Resist layer 5 (for example, PMM
A) will be provided.

Next, as shown in FIG. 2(b), the resist layer 5 is exposed and developed to form an elongated pattern with a width of 0.25 μm, and using the resist pattern as a mask, carbon tetrafluoride (
By performing reactive sputter etching using a mixed gas of CF4) gas and hydrogen (112> gas), 5i0
The second layer 4 is etched, and then the resist layer 3 and the resin layer 2 are etched using a reactive etching method using oxygen gas, and the resist layer 5 is etched away at the same time.

In the dry etching using oxygen gas used in etching the resist layer 3 and resin layer 2, the 5i02 layer 4 is hardly etched.

Next, as shown in FIG. 2(c), a third resist 6 (for example, Photoresist AZ-2400 manufactured by Shipley) is coated on the entire surface of the intermediate layer 4, and the third resist 6 is coated so as not to include the openings at the edges. The resist layer 6 is exposed and developed to expose the intermediate layer 4, and the intermediate layer 4 is removed by reactive gas or plasma etching using a mixed gas of CF4 gas and H2 gas,
Further development removes the resist layer 3, resulting in the first resist layer 3 on one side, in this case on the right.
Intermediate layer 4 is removed. Next, grooves are formed on the previously exposed semiconductor surface by wet etching or dry etching, or surface treatment is performed.

Next, as shown in FIG. 2(d), an Ag layer 7 is vertically deposited on the entire surface from the upper surface (the thickness is arbitrary, but it is thinner than the first resist layer 3; in this case, it is 1 μm or less).

Next, as shown in FIG. 2(e), a fourth resist layer 8 (for example, AZ-14 manufactured by Photoresist Shipray Co., Ltd.) is applied over the entire surface.
00-17), exposed to light, and
After exposing the G layer 7, the Ag layer 7 is removed by etching with phosphoric acid at 60°C.

Next, as shown in FIG. 2(,f), the third resist layer 6 is removed with 0□ gas, the intermediate layer 4 is removed with a mixed gas of CF4 and i12, and then reactive etching with 02 gas and plasma are performed. By etching, the first and third resist layers 3.6 and the resin layer 2 are removed, and at the same time, the unnecessary portion of the gate metal layer 7 is also removed, resulting in the gate portion of the GaAs MES-FET as shown in the figure. A cross-sectional structure is obtained.

The MES/FET of this example obtained through the above steps has a structure in which the gate electrode 7 is formed on the GaAs substrate 1 in a "(gamma)" shape in cross section, and the gate electrode protrudes only on one side. Note that the part where the Ag layer of the gate electrode and the GaAs substrate 1 are in contact has a horizontal-Sotky junction.
This purpose can be achieved by forming the source electrode on the left side of the gate electrode. Note that in the description of the above embodiments, specific materials and thicknesses were mentioned. This is for convenience of explanation; for example, the gate metal does not have to be two-layer 7, but can be a metal or a multilayer structure that has key characteristics with respect to the semiconductor substrate and good shot 1. Further, the thickness of the first resist layer 3 may be controlled to be thicker than the layer 7 serving as the gate metal. Moreover, even if the intermediate layer 4 does not have coating property 5i02,
It may be a thin metal film, and in this case, coating property 5i02 can be used for the resin layer 2 instead of the resin.

Furthermore, if an oblique evaporation method is used when depositing the ^e layer 7 (FIG. 2d), it is possible to further reduce the gate length.

〔Effect of the invention〕

As explained in detail above, according to the present invention, with the above structure, even with a short gate length (0.2 μm or less), it is possible to not only suppress an increase in gate resistance, but also to prevent an increase in gate resistance. The fringing capacitance between electrodes can be reduced, and as a result, it is possible to manufacture a semiconductor device made of a compound semiconductor that has excellent gain, low noise characteristics, and high output characteristics, which are important as high frequency characteristics.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are vertical cross-sectional views of the gate portion of a device shown in order of process to explain one embodiment of the present invention, and FIGS.・MES-FE
FIG. 4 is a vertical cross-sectional view of a gate portion shown in order of steps to explain the method for manufacturing T. FIG. 1.11... Ga substrate, 2.12... Resin layer,
3... Second resist layer, 4, 13... Intermediate layer (Si
O□), 5... second resist layer, 6... third resist layer, 7°15... AN layer, 8... fourth resist layer, 14... resist layer. $ I Figure 5, Correction pair Q

Claims (1)

[Claims] An organic or inorganic insulating layer, a first resist layer, a thin intermediate layer of silicon oxide or silicon nitride or a metal such as polycrystalline silicon or aluminum, and a second layer are formed on the semiconductor substrate in sequence.
exposing and developing the second resist layer to form a pattern having openings, etching using the pattern to form a predetermined pattern in the intermediate layer, and further etching. a step of opening the first resist layer to expose the organic or inorganic insulating layer, and further etching to expose the surface of the semiconductor substrate; a step of etching or surface-treating the exposed surface of the semiconductor substrate; A process of applying a resist layer, exposing and developing the third and first resist layers, and removing the area above the first resist layer forming a pattern on one side, and applying a directional deposition method from above to form an electrode. A step of depositing a metal layer on the exposed semiconductor substrate, an organic or inorganic insulating layer, and an intermediate layer, removing an unnecessary electrode metal layer, and then depositing the intermediate layer, the first resist layer, and the organic or inorganic insulating layer. 1. A method for manufacturing a semiconductor device, comprising the step of removing a layer.