KR20000074002A - method for fabricating a T-gate - Google Patents
method for fabricating a T-gate Download PDFInfo
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- KR20000074002A KR20000074002A KR1019990017646A KR19990017646A KR20000074002A KR 20000074002 A KR20000074002 A KR 20000074002A KR 1019990017646 A KR1019990017646 A KR 1019990017646A KR 19990017646 A KR19990017646 A KR 19990017646A KR 20000074002 A KR20000074002 A KR 20000074002A
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- gate
- gate electrode
- electrode material
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000007772 electrode material Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 21
- 238000010894 electron beam technology Methods 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 description 22
- 239000007769 metal material Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
본 발명은 티(T)형 게이트에 관한 것으로, 특히 고주파 대역에서 사용되는 FET(Field Effect Transistor)의 티형 게이트 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tee (T) type gate, and more particularly, to a method for manufacturing a tee type gate of a field effect transistor (FET) used in a high frequency band.
일반적으로, 높은 주파수에서 동작하는 FET는 게이트 길이를 줄임으로써 이득의 향상을 꾀할 수 있고, 단면적을 넓힘으로써 전달되는 전력의 손실을 줄일 수 있는데, 이러한 요건들을 충족시켜 주는 것이 바로 티(T)자형 게이트이다.In general, FETs operating at high frequencies can improve the gain by reducing the gate length and reduce the loss of power delivered by widening the cross-sectional area, which meets these requirements. It is a gate.
이와 같은 종래의 티형 게이트 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, such a conventional tee-type gate manufacturing method is as follows.
도 1a 내지 도 1c는 종래 기술에 따른 티형 게이트 제조 공정을 보여주는 공정단면도이다.1A to 1C are cross-sectional views illustrating a process of manufacturing a tee gate according to the related art.
종래의 티형 게이트 제조방법은 도 1a에 도시된 바와 같이, 기판(1)상에 감도가 다른 제 1, 제 2 포토레지스트(2,3)를 차례로 형성하고, 전자빔 라이팅(E-Beam Writting) 기술을 이용하여 게이트 전극을 형성할 영역에 전자빔(E-beam)을 조사하면 제 1, 제 2 포토레지스트(2,3)의 감도가 다르기 때문에 티형 게이트 전극이 증착될 수 있도록 공간(4)이 생성된다.In the conventional tee-type gate manufacturing method, as shown in FIG. 1A, first and second photoresists 2 and 3 having different sensitivitys are sequentially formed on the substrate 1, and an electron beam writing technique is performed. When the E-beam is irradiated to the region where the gate electrode is to be formed using the light emitting device, since the sensitivity of the first and second photoresists 2 and 3 is different, the space 4 is created so that the tee gate electrode can be deposited. do.
즉, 제 2 포토레지스트(3)은 넓은 폭으로 패터닝되고, 제 1 포토레지스트(2)는 좁은 폭으로 패터닝된다.That is, the second photoresist 3 is patterned to a wide width, and the first photoresist 2 is patterned to a narrow width.
이어, 도 1b에 도시된 바와 같이, 공간(4)을 포함한 전면에 게이트 금속(5,6)을 증착한다.Subsequently, as shown in FIG. 1B, gate metals 5 and 6 are deposited on the entire surface including the space 4.
이때, 패터닝된 제 1, 제 2 포토레지스트(2,3)가 큰 단차를 갖기 때문에 공간(4)과 제 2 포토레지스트(3) 위에서 불연속적으로 게이트 금속(5,6)이 형성된다.At this time, since the patterned first and second photoresists 2 and 3 have a large step, gate metals 5 and 6 are discontinuously formed on the space 4 and the second photoresist 3.
그리고, 도 1c에 도시된 바와 같이 리프트-오프(lift-off) 공정으로 제 1, 제 2 포토레지스트(2,3) 및 그 위에 형성된 게이트 금속(6)을 제거하여 티형 게이트 전극을 형성한다.As shown in FIG. 1C, the first and second photoresist 2 and 3 and the gate metal 6 formed thereon are removed by a lift-off process to form a tee type gate electrode.
이상에서 설명한 바와 같은 종래의 티형 게이트 제조방법에 있어서는 다음과 같은 문제점이 있었다.The conventional tee-type gate manufacturing method as described above has the following problems.
첫째, 완성된 티형 게이트 전극을 보면 게이트의 지붕 가운데 부분이 푹 패인 것을 알 수 있는데, 이러한 부분은 소자의 주파수 특성에 악영향을 미치게 된다.First, the completed tee gate electrode shows that the central part of the roof of the gate is completely covered, which adversely affects the frequency characteristics of the device.
둘째, 티형 게이트 전극의 제조를 위해 값이 비싼 전자빔 라이팅 기술을 사용하므로 제조 비용이 상승한다.Secondly, the use of expensive electron beam writing techniques for the manufacture of the tee gate electrode increases the manufacturing cost.
본 발명은 이러한 문제들을 해결하기 위한 것으로 티형 게이트 지붕의 표면을 평평하게 하여 주파수 특성이 향상될 수 있는 티형 게이트 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for manufacturing a tee gate, in which a frequency characteristic can be improved by flattening the surface of the tee gate roof.
본 발명의 다른 목적은 전자빔 라이팅 기술을 이용하지 않음으로써 제조 비용을 낮출 수 있는 티형 게이트 제조방법을 제공하는데 있다.Another object of the present invention is to provide a tee-type gate manufacturing method which can lower manufacturing costs by not using electron beam writing technology.
도 1a 내지 도 1c는 종래 기술에 따른 티형 게이트 제조 공정을 보여주는 공정단면도1A to 1C are cross-sectional views illustrating a tee gate manufacturing process according to the related art.
도 2a 내지 도 2j는 본 발명에 따른 티형 게이트 제조공정을 보여주는 공정 단면도2A to 2J are cross-sectional views illustrating a tee-type gate manufacturing process according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11 : 기판 12 : 포토레지스트11 substrate 12 photoresist
13 : 게이트 패턴 영역 14 : 제 1 질화막13 gate pattern region 14 first nitride film
15,19,21 : 공간 16 : 금속막15, 19, 21: space 16: metal film
17,18 : 제 1 게이트 전극물질 20 : 제 2 질화막17,18: first gate electrode material 20: second nitride film
22,23 : 제 2 게이트 전극물질22,23: second gate electrode material
상기와 같은 목적을 달성하기 위한 본 발명에 따른 티형 게이트 제조방법은 게이트 패턴 영역이 노출되도록 기판상에 제 1 물질을 형성하는 단계와, 게이트 패턴 영역의 중앙부분만이 노출되도록 제 1 물질 표면 및 측면에 제 2 물질을 형성하는 단계와, 노출된 중앙부분의 기판상에 제 1 게이트 전극물질을 형성하고 제 2 물질을 제거하는 단계와, 제 1 게이트 전극물질의 표면이 노출되도록 제 1 게이트 전극물질과 제 1 물질 사이에 제 3 물질을 형성하는 단계와, 제 1 게이트 전극물질과 전기적으로 연결되도록 제 1 게이트 전극물질 및 제 3 물질상에 제 2 게이트 전극물질을 형성하는 단계로 이루어지는데 그 특징이 있다.In order to achieve the above object, a tee-type gate manufacturing method according to the present invention includes forming a first material on a substrate to expose a gate pattern region, a surface of the first material such that only a central portion of the gate pattern region is exposed, and Forming a second material on the side, forming a first gate electrode material on the exposed central substrate and removing the second material, and exposing the surface of the first gate electrode material to expose the first gate electrode Forming a third material between the material and the first material, and forming a second gate electrode material on the first gate electrode material and the third material to be electrically connected with the first gate electrode material. There is a characteristic.
본 발명의 다른 특징은 게이트 패턴 영역이 노출되도록 기판상에 제 1 물질을 형성하는 단계를 통해 티형 게이트 상부의 길이를 결정하고, 노출된 게이트 패턴 영역을 포함한 전면에 절연막을 형성하는 단계와 절연막상에 금속막을 형성하는 단계와 금속막을 마스크로 절연막을 제거하여 노출된 게이트 패턴 영역의 중앙부분을 노출시키는 단계를 통해 티형 게이트 상부의 길이를 결정하는데 있다.Another aspect of the present invention is to determine the length of the top of the tee-type gate by forming a first material on the substrate to expose the gate pattern region, and to form an insulating film on the entire surface including the exposed gate pattern region The length of the upper portion of the tee-type gate is determined by forming a metal film on the substrate and exposing the center portion of the exposed gate pattern region by removing the insulating film using the metal film as a mask.
본 발명의 또 다른 특징은 포토레지스트를 이용하여 티형 게이트 상부의 길이를 결정하고 절연막을 이용하여 티형 게이트 하부의 길이를 결정하여 티형 게이트를 제작함으로써, 전자빔 라이팅 기술을 사용하는 종래에 비해 제조 비용을 크게 낮추는데 있다.Another feature of the present invention is to determine the length of the top of the tee-type gate using a photoresist and to form the tee-type gate by determining the length of the bottom of the tee-type gate using an insulating film, thereby reducing the manufacturing cost compared to the conventional using the electron beam writing technology It's in a big way.
본 발명의 또 다른 특징은 티형 게이트를 제작할 때, 종래와 같이 한 번의 공정으로 티형 게이트를 제작하지 않고 티형 게이트의 하부 및 상부를 각기 다른 공정으로 분리하여 제작함으로써, 티형 게이트의 표면을 평평하게 하여 주파수 특성을 향상시키는데 있다.Another feature of the present invention is that when manufacturing the tee-type gate, the surface of the tee-type gate is made flat by separating the lower and upper portions of the tee-type gate by different processes without manufacturing the tee-type gate in one process as in the prior art. To improve the frequency characteristics.
본 발명의 다른 목적, 특징 및 잇점들은 첨부한 도면을 참조한 실시예들의 상세한 설명을 통해 명백해질 것이다.Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.
상기와 같은 특징을 갖는 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, preferred embodiments of the present invention having the features as described above are as follows.
도 2a 내지 도 2j는 본 발명에 따른 티형 게이트 제조공정을 보여주는 공정 단면도이다.2A to 2J are cross-sectional views illustrating a process of manufacturing a tee gate according to the present invention.
먼저, 도 2a에 도시된 바와 같이 기판(11)상에 포토레지스트(photoresist)(12)를 형성하고, 포토레지스트(12)를 노광 및 현상하여 약 1㎛ 정도의 게이트 길이를 갖는 게이트 패턴 영역(13)을 노출시킨다.First, as shown in FIG. 2A, a photoresist 12 is formed on the substrate 11, and the photoresist 12 is exposed and developed to form a gate pattern region having a gate length of about 1 μm. 13).
이어, 도 2b에 도시된 바와 같이 게이트 패턴 영역(13)을 포함한 전면에 제 1 질화막(SiN4)(14)을 증착한다.Next, as illustrated in FIG. 2B, a first nitride film (SiN 4 ) 14 is deposited on the entire surface including the gate pattern region 13.
여기서, 제 1 질화막(14)은 포토레지스트(12)에 변형이 생기지 않는 온도로 증착하고, 그의 수평 부분과 수직 부분의 증착 비율을 잘 고려하여 증착한다.Here, the first nitride film 14 is deposited at a temperature at which deformation does not occur in the photoresist 12, and is deposited in consideration of the deposition ratios of the horizontal and vertical portions thereof.
이때의 두께는 약 4500Å 정도가 적합하고, 제 1 질화막(14)을 증착할 때 생기는 공간(15)은 약 0.1㎛로 조절한다.At this time, the thickness of about 4500 kPa is suitable, and the space 15 generated when the first nitride film 14 is deposited is adjusted to about 0.1 mu m.
또한, 제 1 질화막(14) 대신에 산화막(SiO2)이나 기타 유전막을 사용할 수도 있다.In addition, an oxide film (SiO 2 ) or other dielectric film may be used instead of the first nitride film 14.
그리고, 도 2c에 도시된 바와 같이 공간(15) 부분의 제 1 질화막(14)상에는 형성되지 않도록 제 1 질화막(14)상에 금속막(16)을 비스듬하게 비등방적으로 증착한다.As shown in FIG. 2C, the metal film 16 is obliquely and anisotropically deposited on the first nitride film 14 so as not to be formed on the first nitride film 14 in the space 15.
여기서, 사용되는 금속막(16)은 Cr, W, Au, Ti, NiCr, Al 등 여러 가지가 가능하며, 금속막(16)의 두께는 약 500Å 정도가 적합하다.Here, the metal film 16 to be used may be various, such as Cr, W, Au, Ti, NiCr, Al, the thickness of the metal film 16 is preferably about 500 kPa.
다음으로 도 2d에 도시된 바와 같이 금속막(16)을 마스크로 제 1 질화막(14)을 비등방적으로 에칭한다.Next, as shown in FIG. 2D, the first nitride film 14 is anisotropically etched using the metal film 16 as a mask.
에칭을 하고 나면, 공간(15)은 질화막(14)이 에칭된 깊이만큼 깊어지며, 그 길이는 약 0.1㎛를 그대로 유지한다.After etching, the space 15 is deepened by the depth at which the nitride film 14 is etched, and the length thereof remains about 0.1 mu m.
이처럼 제 1 질화막(14)을 에칭을 한 후, 도시되지는 않았지만 소오스와 드레인 사이에 원하는 값의 전류가 흐르도록 하기 위해 기판(11)을 살짝 에칭하여 준다.After etching the first nitride film 14 as described above, the substrate 11 is slightly etched to allow a current having a desired value to flow between the source and the drain, although not shown.
이어, 도 2e에 도시된 바와 같이 전류값을 적당히 조절한 후에 공간(15)을 포함한 전면에 제 1 게이트 금속물질(17,18)을 증착한다.Subsequently, as shown in FIG. 2E, the first gate metal materials 17 and 18 are deposited on the entire surface including the space 15 after the current value is appropriately adjusted.
여기서, 공간(15)내에 증착되는 제 1 게이트 금속물질(17)의 두께는 포토레지스트(12)의 두께보다 작아야 한다.Here, the thickness of the first gate metal material 17 deposited in the space 15 should be smaller than the thickness of the photoresist 12.
즉, 제 1 게이트 금속물질(17,18)의 두께는 약 2200Å 정도로 조절한다.That is, the thickness of the first gate metal materials 17 and 18 is adjusted to about 2200 kPa.
또한, 제 1 게이트 금속물질(17,18)은 금(Au)을 사용하고, 제 1 게이트 금속물질(17)과 기판(11)과의 접착(adhesion)을 좋게 하기 위해 적어도 한층 이상으로 증착하는 것이 좋다.In addition, the first gate metal material 17 and 18 may be formed of gold (Au), and may be deposited on at least one or more layers to improve adhesion between the first gate metal material 17 and the substrate 11. It is good.
그리고, 도 2f에 도시된 바와 같이 리프트-오프(lift-off) 공정으로 제 1 질화막(14) 및 그 상부에 형성된 금속막(16), 제 1 게이트 전극물질(18)을 제거한다.As shown in FIG. 2F, the first nitride film 14, the metal film 16 and the first gate electrode material 18 formed thereon are removed by a lift-off process.
즉, 포토레지스트(12)를 에칭하지 않는 희석된 HF용액을 이용하여 제 1 질화막(14)을 에칭하면, 제 1 질화막(14) 상부에 형성된 금속막(16) 및 제 1 게이트 전극물질(18)은 리프트-오프되어 떨어져 나가고, 제 1 게이트 전극물질(17)과 포토레지스트(12)만 남으면서 제 1 게이트 전극물질(17) 위에 새로운 공간(19)이 생긴다.That is, when the first nitride film 14 is etched using a diluted HF solution that does not etch the photoresist 12, the metal film 16 and the first gate electrode material 18 formed on the first nitride film 14 are etched. ) Is lifted off and away, creating a new space 19 over the first gate electrode material 17 with only the first gate electrode material 17 and the photoresist 12 remaining.
이어, 도 2g에 도시된 바와 같이 제 1 게이트 전극물질(17)을 포함한 전면에 제 2 질화막(20)을 증착한다.Next, as illustrated in FIG. 2G, a second nitride film 20 is deposited on the entire surface including the first gate electrode material 17.
여기서, 제 2 질화막(20)은 제 1 질화막(14)과 마찬가지로 포토레지스트(12)에 변형이 생기지 않는 온도로 증착하고, 그의 수평 부분과 수직 부분의 증착 비율을 잘 고려하여 증착한다.Here, like the first nitride film 14, the second nitride film 20 is deposited at a temperature at which deformation does not occur in the photoresist 12, and is deposited in consideration of the deposition ratios of the horizontal and vertical portions thereof.
이때의 두께는 약 3500Å 정도가 적합하며, 증착시 주의해야 할 점은 제 2 질화막(20)을 증착할 때 생기는 공간(21)이 제 1 게이트 전극물질(17)의 게이트 길이와 같거나 작아야 한다는 점이다.At this time, the thickness is about 3500Å is suitable, and care must be taken in depositing that the space 21 generated when depositing the second nitride film 20 should be equal to or smaller than the gate length of the first gate electrode material 17. Is the point.
또한, 제 2 질화막(20) 대신에 산화막(SiO2)이나 기타 유전막을 사용할 수도 있다.In addition, an oxide film (SiO 2 ) or another dielectric film may be used instead of the second nitride film 20.
그리고, 도 2h에 도시된 바와 같이 제 1 게이트 전극물질(17)의 표면이 드러날 때까지 제 2 질화막(20)을 에칭한다.As shown in FIG. 2H, the second nitride film 20 is etched until the surface of the first gate electrode material 17 is exposed.
그러면 제 2 질화막(20)을 증착할 때 생기는 공간(21)이 더 넓고 깊어진다.Then, the space 21 generated when the second nitride film 20 is deposited becomes wider and deeper.
그 다음으로, 도 2i에 도시된 바와 같이 제 1 게이트 전극물질(17)을 포함한 전면에 제 2 게이트 전극물질(22,23)을 증착한다.Next, as illustrated in FIG. 2I, second gate electrode materials 22 and 23 are deposited on the entire surface including the first gate electrode material 17.
여기서, 제 2 게이트 금속물질(22,23)은 금(Au)을 사용하고, 제 2 게이트 금속물질(22)과 제 1 게이트 전극물질(17)과의 접착(adhesion) 및 전력 전달 특성을 좋게 하기 위해 적어도 한층 이상으로 증착하는 것이 좋다.Here, the second gate metal materials 22 and 23 use gold (Au), and the adhesion and power transfer characteristics of the second gate metal material 22 and the first gate electrode material 17 are improved. In order to do so, it is preferable to deposit at least one layer.
마지막으로, 도 2j에 도시된 바와 같이 리프트-오프 공정으로 포토레지스트(12) 및 그 위의 제 2 게이트 전극물질(23)을 제거하고, 남아있는 제 2 질화막(20)을 에칭하면 표면이 깨끗한 티형 게이트가 완성된다.Finally, the photoresist 12 and the second gate electrode material 23 thereon are removed by a lift-off process as shown in FIG. 2J, and the remaining second nitride film 20 is etched to clean the surface. The tee gate is completed.
이상에서 설명한 바와 같은 본 발명의 티형 게이트 제조방법에 있어서는 다음과 같은 효과가 있다.In the tee-type gate manufacturing method of the present invention as described above has the following effects.
첫째, 티형 게이트의 표면이 평평하고 깨끗하게 형성되므로 주파수 특성을 향상시킬 수 있다.First, since the surface of the tee gate is formed flat and clean, the frequency characteristic can be improved.
둘째, 종래와 같이 전자빔 라이팅 기술을 사용하지 않고도 깨끗한 티형 게이트를 제작할 수 있으므로 제조 비용을 크게 낮출 수 있다.Second, since it is possible to manufacture a clean tee-type gate without using the electron beam writing technology as in the prior art it can significantly reduce the manufacturing cost.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
Claims (6)
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|---|---|---|---|
| KR1019990017646A KR20000074002A (en) | 1999-05-17 | 1999-05-17 | method for fabricating a T-gate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20150072003A (en) * | 2013-12-19 | 2015-06-29 | 한국전자통신연구원 | Method for Forming Gate Electrode and Semiconductor Device Having Gate Electrode Obtained by the Method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20150072003A (en) * | 2013-12-19 | 2015-06-29 | 한국전자통신연구원 | Method for Forming Gate Electrode and Semiconductor Device Having Gate Electrode Obtained by the Method |
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