JPH06132312A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To form a gate metal in excellent reproducibility in an asynmmetrical position in a recess. CONSTITUTION:A mask layer 2 is formed assuming the end of the mask layer 2 as the prospective gate metal formation part so as to pattern a gate forming resist B4 in the end striding-over aperture form. Next, the mask layer 2 and a semiconductor wafer 1 are etched away to evaporate a gate metal 5 for removing the surface part thereof 5 by lift-off step etc. Through these procedures, one side only of the mask layer 2 can be etched away thereby enabling the gate metal 5 in the recess to be approached to one side while selfmatchingly positioning the gate metal 5 to the recess 6 for notably enhancing the reproducibility of the relative positioning step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a recess and a gate metal in a semiconductor device having a recess structure.

[0002]

2. Description of the Related Art An example of a conventional method for forming a recess and a gate metal in a semiconductor device of this type is shown in FIGS.
Shown in.

FIG. 3 shows a method called a self-alignment method, in which a recess and a gate metal are formed as follows. First, an insulating film 2 (for example, an oxide film) is formed on the semiconductor wafer 1, and a gate forming resist B4 is patterned thereon as shown in FIG. Next, the insulating film 2 is over-etched to open wider than the opening of the resist B4. The semiconductor wafer 1 is further etched by using the insulating film 2 as a mask to form the recess 6, and then the gate metal 5 is vapor-deposited (FIG. (D)).

Finally, excess gate metal 5 is removed by a lift-off process or the like (FIG. 7E).

This method is called a self-align method because the recess 6 and the gate metal 5 are aligned in a self-aligned manner.

FIG. 4 shows a method called an alignment method.
The recess and gate metal is formed as follows. First, a recess forming resist A3 is patterned on the semiconductor wafer 1 (FIG. (A)), and the semiconductor wafer 1 is etched (FIG. (B)). Next, after removing the resist A3, the gate forming resist B4 is patterned as shown in FIG. The gate metal 5 is vapor-deposited and lifted off to form the gate metal 5 in the recess 6 (Fig. (E)). This method is called an alignment method because it is necessary to align the recess 6 when patterning the gate forming resist B4.

[0007]

However, the above-described conventional method of forming the recess 6 and the gate metal 5 has the following drawbacks with respect to the relative positional relationship between the recess 6 and the gate metal 5.

In order to improve the performance of the semiconductor device, it is necessary to position the gate metal 5 in the recess 6 on one side and form it with high positional accuracy. That is, it is necessary to make l ₁ > l ₂ and l ₂ = constant for l ₁ and l ₂ in FIG. 4 (e). In contrast to this need, the method of FIG. 3 results in l ₁ = l ₂ and the method of FIG. 4 does not make l ₂ constant (the recess 6 and the gate metal 5 need to be aligned, but the alignment reproducibility is The current situation is at most ± 0.1μ
m (2σ)).

[0009]

[Means for Solving the Problems] On a semiconductor wafer,
A mask layer having a different etching characteristic from that of a semiconductor wafer is formed having an end portion at a substantially gate metal formation planned position,
Patterning a resist having an opening corresponding to the gate metal by exposing the end portion in the opening, and opening the end portion of the mask layer wider than the opening of the resist by overetching the mask layer using the resist as a mask, A semiconductor wafer is etched using the resist and the mask layer as a mask to form a recess, and a gate metal is formed using the resist as a mask.

[0010]

According to the above manufacturing method, the recess and the gate metal are aligned in a self-aligned manner, so that the relative positional relationship between them can be formed with good reproducibility, and the insulating film is etched only on one side. It is possible to form the gate metal in the inside by shifting it to one side, so that high performance of the semiconductor device can be achieved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is an enlarged sectional view of an essential part of an embodiment of the present invention. In the figure, first, for example, Ga having an active layer
A mask layer 2 made of an insulating film such as SiO ₂ is formed on a semiconductor wafer 1 made of As, and is partially removed by etching, leaving the drain side with the gate metal formation planned position as an end ((b) diagram). ). Then, a gate forming resist B4 which is opened so as to straddle the etching end is patterned (FIG. 7C). Further, the mask layer 2 is etched (Fig. (D)), the semiconductor wafer 1 is etched to form the recess 6, and then the gate metal 5 is deposited ((e)).
Figure). Finally, the excess gate metal 5 is removed by lift-off processing or the like (FIG. (F)).

According to this embodiment, since the mask layer 2 is etched only on one side, the position of the gate metal 5 in the recess 6 can be shifted to one side, and the position of the gate metal 5 with respect to the recess 6 is self-aligned. Since they are determined in a consistent manner, the reproducibility of the relative positional relationship is very good.

In this embodiment, SiO ₂ is used for the mask layer, but the semiconductor material has different etching characteristics, that is, the semiconductor material is not etched but only the mask layer is etched, and vice versa. However, any material can be used as long as the mask layer can be found while satisfying the condition that the mask layer is not etched.

For example, metal may be removed by etching later.

However, the insulating film is convenient because it can be left as it is.

The only possible problem is the patterning position accuracy of the gate forming resist B4 with respect to the etching end portion of the insulating film 2. However, as shown in FIG. Misalignment is allowed.

[0018]

As described above, according to the present invention, by partially forming a mask layer on one side of a portion where a recess is to be formed, the position of the gate metal formed in the recess is asymmetric in the recess. It is possible to arrange the semiconductor device at a desired position with good reproducibility, and it is possible to achieve high performance of the semiconductor device.

[Brief description of drawings]

FIG. 1 is an enlarged sectional view of an essential part showing an embodiment of a semiconductor device manufacturing method of the present invention.

FIG. 2 is an enlarged cross-sectional view of the vicinity of the recess gate when a misalignment occurs in the semiconductor device manufacturing method of the present invention.

FIG. 3 is an enlarged sectional view of an essential part showing a conventional semiconductor device manufacturing method (self-alignment method).

FIG. 4 is an enlarged sectional view of an essential part showing a conventional semiconductor device manufacturing method (alignment method).

[Explanation of symbols]

1 semiconductor wafer 2 mask layer (SiO ₂ ) 3 resist A 4 resist B (for gate formation) 5 gate metal 6 recess

Claims (3)

[Claims] 1. A semiconductor wafer is formed with a mask layer having etching characteristics different from those of the semiconductor wafer, having an end portion at a position where a gate metal is to be formed, and exposing the end portion into an opening to correspond to the gate metal. Patterning a resist having an opening to form a mask, the mask layer is over-etched using the resist as a mask to open the end of the mask layer wider than the opening of the resist, and the semiconductor wafer is etched using the resist and the mask layer as a mask. Forming a recess, and forming a gate metal by using the resist as a mask. 2. A method of manufacturing a semiconductor device, wherein the mask layer is an insulating film. 3. A step of partially forming an insulating film on a semiconductor wafer, a step of patterning a resist having an opening at a boundary between a portion where the insulating film is formed and a portion where the insulating film is not formed on the semiconductor wafer, and the resist. And a step of forming a recess by over-etching the semiconductor wafer through the opening, and a step of forming a gate metal by masking the resist in the recess.