KR100252888B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100252888B1
KR100252888B1 KR1019970066246A KR19970066246A KR100252888B1 KR 100252888 B1 KR100252888 B1 KR 100252888B1 KR 1019970066246 A KR1019970066246 A KR 1019970066246A KR 19970066246 A KR19970066246 A KR 19970066246A KR 100252888 B1 KR100252888 B1 KR 100252888B1
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South Korea
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wiring layer
contact hole
film
forming
layer
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KR1019970066246A
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Korean (ko)
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KR19990047731A (en
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윤창준
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to allow the formation of a through contact hole in a self-aligned manner without a lithography process. CONSTITUTION: In the method, the first metal layer(12a) is formed on a semiconductor substrate(11), and an insulating layer(13) is formed thereon. The insulating layer(13) and the first metal layer(12a) are then selectively patterned, and a sidewall spacer is formed on lateral sides of the patterned layers(13,12a). Next, an oxide layer(15) is grown from a portion of the substrate(11) between the adjacent sidewall spacers to an upper peripheral portion of the insulating layer(13). The insulating layer(13) is then selectively etched by using the oxide layer(15) as a mask, so that the through contact hole(16) is formed in a self-aligned manner. Next, the second metal layer is wholly formed over the oxide layer(15) and then patterned to make contact with the first metal layer(12a) by the through contact hole(16).

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로 특히, 스루콘택홀을 리소그래피공정없이 셀프-얼라인으로 형성할 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of forming a through contact hole in a self-aligned manner without a lithography process.

이하에서, 첨부된 도면을 참조하여 종래 반도체소자의 제조방법을 설명하기로 한다.Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1h는 종래 반도체소자의 제조공정 단면도이다.1A to 1H are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device.

먼저, 도 1a에 나타낸 바와 같이, 반도체기판(1)상에 배선층(2)과 배선층(2)상에 제 1 산화막(3)을 형성한다.First, as shown in FIG. 1A, the first oxide film 3 is formed on the wiring layer 2 and the wiring layer 2 on the semiconductor substrate 1.

도 1b에 나타낸 바와 같이, 상기 제 1 산화막(3) 및 배선층(2)을 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 일정간격으로 배선층 패턴(2a)을 형성한다. 이어서, 상기 배선층 패턴(2a)을 포함한 기판 전면에 제 2 산화막(4)을 형성한다.As shown in FIG. 1B, the first oxide film 3 and the wiring layer 2 are selectively patterned (photolithography process + etching process) to form the wiring layer pattern 2a at a predetermined interval. Subsequently, a second oxide film 4 is formed on the entire substrate including the wiring layer pattern 2a.

도 1c에 나타낸 바와 같이, 상기 제 2 산화막(4)을 에치백하여 상기 배선층 패턴(2a)의 측면에 측벽 스페이서(4a)를 형성한다.As shown in Fig. 1C, the second oxide film 4 is etched back to form sidewall spacers 4a on the side surfaces of the wiring layer patterns 2a.

도 1d에 나타낸 바와 같이, 상기 배선층 패턴(2a)을 포함한 상기 기판 전면에 제 3 산화막(5)을 형성한다음 상기 제 3 산화막(5)상에 감광막(PR1)을 도포한다. 이어서, 노광 및 현상공정으로 스루콘택홀 영역을 정의하여 스루콘택홀 영역의 상기 감광막(PR1)을 패터닝한다. 그다음, 패터닝된 상기 감광막(PR1)을 마스크로 이용한 식각공정으로 스루콘택홀 영역의 상기 제 3 산화막(5)을 선택적으로 제거하여 제 1 산화막(3)의 상측면을 노출시킨다.As shown in FIG. 1D, a third oxide film 5 is formed on the entire surface of the substrate including the wiring layer pattern 2a, and then a photosensitive film PR 1 is coated on the third oxide film 5. Subsequently, the photoresist film PR 1 of the through contact hole region is patterned by defining a through contact hole region by an exposure and development process. Next, the third oxide film 5 in the through contact hole region is selectively removed by an etching process using the patterned photoresist film PR 1 as a mask to expose the upper surface of the first oxide film 3.

도 1e에 나타낸 바와 같이, 상기 감광막(PR1)을 마스크로 이용한 식각공정으로 스루콘택홀영역의 상기 제 1 산화막(3)을 제거하여 스루콘택홀(6)을 형성한다.As shown in FIG. 1E, the first oxide film 3 in the through contact hole region is removed by an etching process using the photoresist film PR 1 as a mask to form a through contact hole 6.

도 1f에 나타낸 바와 같이, 상기 감광막(PR1)을 제거한다.As shown in FIG. 1F, the photosensitive film PR 1 is removed.

도 1g에 나타낸 바와 같이, 상기 스루콘택홀(6)을 포함한 제 3 산화막(5) 전면에 제 2 배선층(7)을 형성한다음 제 2 배선층(7)상에 감광막(PR2)을 도포한다. 이어서, 노광 및 현상공정으로 상기 제 1 배선층 패턴(2a)과 동일 위치에 남도록 상기 감광막(PR2)을 패터닝한다.As shown in FIG. 1G, the second wiring layer 7 is formed on the entire surface of the third oxide film 5 including the through contact hole 6, and then the photosensitive film PR 2 is coated on the second wiring layer 7. . Subsequently, the photosensitive film PR 2 is patterned so as to remain at the same position as the first wiring layer pattern 2a by an exposure and development process.

도 1h에 나타낸 바와 같이, 패터닝된 상기 감광막(PR2)을 마스크로 이용한 식각공정으로 상기 제 2 배선층(7)을 패터닝하여 제 2 배선층 패턴(7a)을 형성한다. 이어서, 상기 감광막(PR2)을 제거한다.As shown in FIG. 1H, the second wiring layer 7 is patterned to form a second wiring layer pattern 7a by an etching process using the patterned photosensitive film PR 2 as a mask. Subsequently, the photosensitive film PR 2 is removed.

종래 반도체소자의 제조방법에 있어서는 하부 배선층과 상부 배선층을 콘택시키기 위하여 그 계면의 산화막을 제거하여 스루콘택홀을 형성하는 공정이 필요한데 그와 같은 공정은 감광막에 대한 노광 및 현상공정인 리소그래피공정과 감광막 패턴을 마스크로 이용한 식각공정이 추가되므로 공정이 복잡하여 생산성 및 수율이 저하되는 문제점이 있다.In the conventional method of manufacturing a semiconductor device, a step of forming a through contact hole by removing an oxide film at an interface thereof in order to contact a lower wiring layer and an upper wiring layer is required. Since the etching process using the pattern as a mask is added, the process is complicated, and there is a problem in that productivity and yield are reduced.

본 발명은 상기한 바와 같은 종래 반도체소자 제조방법의 문제점을 해결하기 위하여 안출한 것으로, 스루콘택홀을 리소그래피공정없이 셀프-얼라인으로 형성할 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional semiconductor device manufacturing method as described above, and an object thereof is to provide a method for manufacturing a semiconductor device capable of forming a through contact hole in a self-aligned manner without a lithography process. .

도 1a 내지 도 1h는 종래 반도체소자의 제조공정 단면도1A to 1H are cross-sectional views of a manufacturing process of a conventional semiconductor device.

도 2a 내지 도 2g는 본 발명 반도체소자의 제조공정 단면도2A to 2G are cross-sectional views of a manufacturing process of the semiconductor device according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

11 : 기판 12a : 제 1 배선층 패턴11 substrate 12a first wiring layer pattern

13 : 제 1 절연막 14a : 측벽 스페이서13: 1st insulating film 14a: side wall spacer

15 : 산화막 16 : 스루콘택홀15: oxide film 16: through contact hole

17a : 제 2 배선층 패턴17a: second wiring layer pattern

본 발명에 따른 반도체소자의 제조방법은 기판상에 제 1 배선층을 형성하는 단계, 상기 제 1 배선층상에 제 1 절연막을 형성하는 단계, 상기 제 1 절연막 및 제 1 배선층을 선택적으로 패터닝하여 제 1 배선층 패턴을 형성하는 단계, 상기 제 1 배선층 패턴의 측면에 측벽 스페이서를 형성하는 단계, 상기 측벽 스페이서 사이의 상기 반도체기판 및 상기 반도체기판의 양측면에 인접한 상기 제 1 절연막의 중앙부를 제외한 상기 제 1 절연막상에 제 2 절연막을 형성하는 단계, 상기 제 2 절연막을 마스크로 이용한 식각공정으로 상기 제 1 절연막을 선택적으로 제거하여 스루콘택홀을 형성하는 단계, 상기 스루콘택홀을 포함한 기판 전면에 제 2 배선층을 형성하는 단계, 상기 제 2 배선층을 상기 제 1 배선층 패턴과 동일 위치에만 남도록 패터닝하는 단계를 포함한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a first wiring layer on a substrate, forming a first insulating film on the first wiring layer, and selectively patterning the first insulating film and the first wiring layer to form a first Forming a wiring layer pattern, forming sidewall spacers on side surfaces of the first wiring layer pattern, the first insulation except for a central portion of the semiconductor substrate between the sidewall spacers and the first insulating layer adjacent to both sides of the semiconductor substrate; Forming a second insulating film on the film, selectively removing the first insulating film by an etching process using the second insulating film as a mask to form a through contact hole, and a second wiring layer on the entire surface of the substrate including the through contact hole Forming a second wiring layer so that the second wiring layer remains only at the same position as the first wiring layer pattern; The.

이와 같은 본 발명 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명 반도체소자의 제조공정 단면도이다.2A to 2G are cross-sectional views illustrating a manufacturing process of the semiconductor device of the present invention.

먼저, 도 2a에 나타낸 바와 같이, 반도체기판(11)상에 배선층(12)과 배선층(12)상에 제 1 절연막(13)을 형성한다. 이때, 상기 제 1 절연막(13)은 고내열성 및 절연특성이 우수한 물질로 형성하며, 바람직하게는 질화막으로 형성한다.First, as shown in FIG. 2A, the first insulating film 13 is formed on the wiring layer 12 and the wiring layer 12 on the semiconductor substrate 11. At this time, the first insulating film 13 is formed of a material having high heat resistance and excellent insulating properties, and preferably formed of a nitride film.

도 2b에 나타낸 바와 같이, 상기 제 1 절연막(13) 및 배선층(12)을 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 일정간격으로 배선층 패턴(12a)을 형성한다. 이어서, 상기 배선층 패턴(12a)을 포함한 기판 전면에 제 2 절연막(14)을 형성한다. 이때, 상기 제 2 절연막(14)은 질화막으로 형성한다.As shown in FIG. 2B, the first insulating film 13 and the wiring layer 12 are selectively patterned (photolithography process + etching process) to form the wiring layer pattern 12a at a predetermined interval. Subsequently, the second insulating film 14 is formed on the entire surface of the substrate including the wiring layer pattern 12a. In this case, the second insulating film 14 is formed of a nitride film.

도 2c에 나타낸 바와 같이, 상기 제 2 절연막(14)을 에치백하여 상기 배선층 패턴(12a)의 측면에 측벽 스페이서(14a)를 형성한다.As shown in FIG. 2C, the sidewall spacer 14a is formed on the side surface of the wiring layer pattern 12a by etching back the second insulating film 14.

도 2d에 나타낸 바와 같이, 상기 반도체기판(11)을 산화시켜 상기 측벽 스페이서(14a)사이의 반도체기판(11)상측 및 노출된 반도체기판(11) 상측면에 인접한 상기 제 1 절연막(13)의 상측면에 산화막(15)을 형성한다. 이때, 상기 제 1 절연막(13)의 중앙부에는 산화막(15)이 형성되지 않도록 한다. 즉, 동일한 조건으로 상기 반도체기판(11)에서 산화막(15)을 성장시키면 전면에서 균일한 산화막(15)을 형성하는 것이 가능하므로 제 1 절연막(13)의 중앙부분까지 산화막(15)이 성장되기전 산화막(15)성장공정을 멈추면 셀프-얼라인으로 스루 콘택홀이 형성될 부분에는 산화막(15)을 형성하지 않을 수 있는 것이다.As shown in FIG. 2D, the semiconductor substrate 11 is oxidized to oxidize the first insulating layer 13 adjacent to the upper side of the semiconductor substrate 11 between the sidewall spacers 14a and the upper side of the exposed semiconductor substrate 11. An oxide film 15 is formed on the upper side. At this time, the oxide film 15 is not formed in the central portion of the first insulating film 13. That is, when the oxide film 15 is grown on the semiconductor substrate 11 under the same conditions, it is possible to form a uniform oxide film 15 on the entire surface, so that the oxide film 15 is grown to the center portion of the first insulating film 13. When the growth process of the oxide film 15 is stopped, the oxide film 15 may not be formed in a portion where the through contact hole is to be formed by self-alignment.

도 2e에 나타낸 바와 같이, 상기 산화막(15)을 마스크로 이용한 식각공정으로 상기 제 1 절연막(13)을 선택적으로 제거하여 스루콘택홀(16)을 형성한다. 즉, 스루콘택홀(16)이 셀프-얼라인으로 형성되는 것이다.As illustrated in FIG. 2E, the first insulating layer 13 is selectively removed by an etching process using the oxide layer 15 as a mask to form the through contact hole 16. In other words, the through contact hole 16 is formed in a self-aligned manner.

도 2f에 나타낸 바와 같이, 상기 스루콘택홀(16)을 포함한 산화막(15) 전면에 제 2 배선층(17)을 형성한다음 제 2 배선층(17)상에 감광막(PR11)을 도포한다. 이어서, 노광 및 현상공정으로 상기 제 1 배선층 패턴(12a)과 동일 위치에 남도록 상기 감광막(PR11)을 패터닝한다.As shown in FIG. 2F, the second wiring layer 17 is formed on the entire surface of the oxide film 15 including the through contact hole 16, and then the photosensitive film PR 11 is coated on the second wiring layer 17. Subsequently, the photosensitive film PR 11 is patterned so as to remain at the same position as the first wiring layer pattern 12a by exposure and development.

도 2g에 나타낸 바와 같이, 패터닝된 상기 감광막(PR11)을 마스크로 이용한 식각공정으로 상기 제 2 배선층(17)을 패터닝하여 제 2 배선층 패턴(17a)을 형성한다. 이어서, 상기 감광막(PR11)을 제거한다.As illustrated in FIG. 2G, the second wiring layer 17 is patterned to form a second wiring layer pattern 17a by an etching process using the patterned photosensitive film PR 11 as a mask. Subsequently, the photosensitive film PR 11 is removed.

본 발명에 따른 반도체소자의 제조방법에 있어서는 스루콘택홀을 형성할 때 반도체기판에서부터 성장된 산화막을 이용하여 스루콘택홀영역 이외의 영역을 마스킹한다음 성장된 산화막을 마스크로 이용한 식각공정으로 제 1 배선층 패턴 상측에 형성된 제 1 절연막을 선택적으로 제거하여 스루콘택홀을 형성하므로 리소그래피공정이나 제 1 절연막 상측의 산화막에 대한 식각공정이 생략되면서도 셀프-얼라인에 의한 스루콘택홀 형성이 가능하여 반도체소자의 생산성 및 수율을 향상시킬 수 있다.In the method of manufacturing a semiconductor device according to the present invention, when forming a through contact hole, a region other than the through contact hole region is masked using an oxide film grown from a semiconductor substrate, and then the etching process using the grown oxide film as a mask is performed. The through contact hole is formed by selectively removing the first insulating film formed on the upper wiring layer pattern, so that the through contact hole can be formed by self-alignment while eliminating the lithography process or the etching process for the oxide film on the upper first insulating film. It can improve the productivity and yield.

Claims (3)

기판상에 제 1 배선층을 형성하는 단계;Forming a first wiring layer on the substrate; 상기 제 1 배선층상에 제 1 절연막을 형성하는 단계;Forming a first insulating film on the first wiring layer; 상기 제 1 절연막 및 제 1 배선층을 선택적으로 패터닝하여 제 1 배선층 패턴을 형성하는 단계;Selectively patterning the first insulating layer and the first wiring layer to form a first wiring layer pattern; 상기 제 1 배선층 패턴의 측면에 측벽 스페이서를 형성하는 단계;Forming sidewall spacers on side surfaces of the first wiring layer patterns; 상기 측벽 스페이서 사이의 상기 반도체기판 및 상기 반도체기판의 양측면에 인접한 상기 제 1 절연막의 중앙부를 제외한 상기 제 1 절연막상에 제 2 절연막을 형성하는 단계;Forming a second insulating film on the first insulating film except for a central portion of the semiconductor film between the sidewall spacer and the first insulating film adjacent to both sides of the semiconductor substrate; 상기 제 2 절연막을 마스크로 이용한 식각공정으로 상기 제 1 절연막을 선택적으로 제거하여 스루콘택홀을 형성하는 단계;Forming a through contact hole by selectively removing the first insulating layer by an etching process using the second insulating layer as a mask; 상기 스루콘택홀을 포함한 기판 전면에 제 2 배선층을 형성하는 단계;Forming a second wiring layer on an entire surface of the substrate including the through contact hole; 상기 제 2 배선층을 상기 제 1 배선층 패턴과 동일 위치에만 남도록 패터닝하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.And patterning the second wiring layer so as to remain only at the same position as the first wiring layer pattern. 제 1 항에 있어서, 상기 제 1 절연막과 측벽 스페이서는 질화막으로 형성함을 특징으로 하는 반도체소자의 제조방법.2. The method of claim 1, wherein the first insulating film and the sidewall spacers are formed of a nitride film. 제 1 항에 있어서, 상기 제 2 절연막은 상기 반도체기판을 산화하여 형성함을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the second insulating layer is formed by oxidizing the semiconductor substrate.
KR1019970066246A 1997-12-05 1997-12-05 Method for fabricating semiconductor device KR100252888B1 (en)

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