KR100268898B1 - Method for forming contact hole of semiconductor device - Google Patents

Method for forming contact hole of semiconductor device Download PDF

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KR100268898B1
KR100268898B1 KR1019970057983A KR19970057983A KR100268898B1 KR 100268898 B1 KR100268898 B1 KR 100268898B1 KR 1019970057983 A KR1019970057983 A KR 1019970057983A KR 19970057983 A KR19970057983 A KR 19970057983A KR 100268898 B1 KR100268898 B1 KR 100268898B1
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contact hole
forming
semiconductor device
insulation film
photoresist
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KR1019970057983A
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Korean (ko)
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KR19990038316A (en
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김태정
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided, which is appropriate for a contact requiring a high aspect ratio by forming a contact hole of a vertical cylindrical structure. CONSTITUTION: An insulation film(22) is formed on a semiconductor substrate(21) and a photoresist(23) is deposited on the insulation film. Then, the photoresist is patterned with an exposure and developing process. An effective surface area of the insulation film corresponding to a part to be etched in a following process is increased by performing an Ar sputtering process using the patterned photoresist as a mask. And, a contact hole(24), where an upper part width is equal to a lower part width, is formed by removing the insulation film so that a part of the substrate is revealed using the patterned photoresist as a mask. Therefore, the contact hole has a vertical structure during a dry etching process because the effective surface area of the insulation film is increased.

Description

반도체 소자의 콘택홀 형성 방법{METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE}Contact hole formation method of a semiconductor device {METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 큰 종횡비(High Aspect Ratio)에 적당한 반도체 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device suitable for high aspect ratio.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 콘택홀 형성 방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact hole in a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1b는 종래의 반도체 소자의 콘택홀 형성 방법을 나타낸 공정단면도이다.1A to 1B are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

먼저, 도 1a에 도시한 바와 같이 반도체 기판(11)상에 절연막(12)을 형성하고, 상기 절연막(12)상에 포토레지스트(Photo Resist)(13)를 도포한 후, 노광 및 현상공정으로 포토레지스트(13)를 패터닝(Patterning)한다.First, as shown in FIG. 1A, an insulating film 12 is formed on a semiconductor substrate 11, a photoresist 13 is coated on the insulating film 12, and then exposed and developed. The photoresist 13 is patterned.

도 1b에 도시한 바와 같이 상기 패터닝된 포토레지스트(13)를 마스크로 이용하여 상기 반도체 기판(11)의 표면이 소정부분 노출되도록 상기 절연막(12)을 선택적으로 제거하여 콘택홀(14)을 형성한다.As shown in FIG. 1B, the insulating layer 12 is selectively removed to form a contact hole 14 by using the patterned photoresist 13 as a mask to expose a portion of the surface of the semiconductor substrate 11. do.

여기서 상기 콘택홀(14)은 상부의 폭(a)과 하부의 폭(b)이 차이를 갖는데 상부의 폭이 하부의 폭 보다 넓게 형성된다.Here, the contact hole 14 has a width (a) of the upper portion and a width (b) of the lower portion of the upper width is formed wider than the width of the lower portion.

그러나 이와 같은 종래의 반도체 소자의 콘택홀 형성방법에 있어서 상부의 폭과 하부의 폭이 다른 콘택홀이 형성됨으로써 큰 종횡비가 요구되는 콘택 공정시 적합하지 않다는 문제점이 있었다.However, in the conventional method of forming a contact hole of a semiconductor device, there is a problem in that contact holes having different widths at upper and lower widths are not suitable for a contact process requiring a large aspect ratio.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 콘택홀을 수직(Vertical)한 실린더(Cylinder) 구조로 형성하여 큰 종횡비가 요구되는 콘택에 적합한 반도체 소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a contact hole in a semiconductor device suitable for a contact in which a large aspect ratio is required by forming a contact hole in a vertical cylinder structure. There is this.

도 1a 내지 도 1b는 종래의 반도체 소자의 콘택홀 형성 방법을 나타낸 공정단면도1A through 1B are cross-sectional views illustrating a method of forming a contact hole in a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 콘택홀 형성 방법을 나타낸 공정단면도2A to 2C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 절연막21 semiconductor substrate 22 insulating film

23 : 포토레지스트 24 : 콘택홀23: photoresist 24: contact hole

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택홀 형성방법은 반도체 기판상에 절연막을 형성하는 단계와, 상기 절연막의 표면에 콘택홀 형성영역을 정의하는 단계와, 상기 콘택홀 형성영역으로 정의된 절연막의 표면을 요철 형태로 형성하는 단계와, 그리고 상기 콘택홀 형성영역으로 정의된 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, forming an insulating film on a semiconductor substrate, defining a contact hole forming region on a surface of the insulating film, and forming the contact hole. And forming a contact hole by forming a surface of the insulating film defined as a region in an uneven shape, and selectively removing the insulating film defined as the contact hole forming region.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 콘택홀 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.

도 2a에 도시한 바와 같이 반도체 기판(21)상에 절연막(22)을 형성하고, 상기 절연막(22)상에 포토레지스트(Photo Resist)(23)를 도포한 후, 노광 및 현상공정으로 포토레지스트(23)를 패터닝(Patterning)한다.As shown in FIG. 2A, an insulating film 22 is formed on the semiconductor substrate 21, a photoresist 23 is applied on the insulating film 22, and then the photoresist is exposed and developed. Pattern (23).

도 2b에 도시한 바와 같이 상기 패터닝된 포토레지스트(23)를 마스크로 이용하여 아르곤(Ar) 스퍼터링(Sputterning) 공정을 수행하여 이후 공정에서 식각될 부분에 해당되는 절연막(22)의 유효 표면적을 증가시킨다.As shown in FIG. 2B, an argon (Ar) sputtering process is performed using the patterned photoresist 23 as a mask to increase the effective surface area of the insulating film 22 corresponding to the portion to be etched in a subsequent process. Let's do it.

즉, 상기 포토레지스트(23)가 제거되어 표면이 노출된 절연막(22)의 표면이 아르곤 스퍼터링 공정에 의해서 요철(凹凸)모양으로 굴곡을 갖음으로서 유효 표면적이 증가된다.That is, the effective surface area is increased by the surface of the insulating film 22 having the photoresist 23 removed and the surface exposed to be bent in an irregular shape by an argon sputtering process.

도 2c에 도시한 바와 같이 상기 패터닝된 포토레지스트(23)를 마스크로 이용하여 상기 반도체 기판(21)의 표면이 소정부분 노출되도록 상기 절연막(22)을 선택적으로 제거하여 상부의 폭과 하부의 폭이 동일한 콘택홀(24)을 형성한다.As shown in FIG. 2C, by using the patterned photoresist 23 as a mask, the insulating layer 22 is selectively removed so that the surface of the semiconductor substrate 21 is exposed to a predetermined portion. This same contact hole 24 is formed.

여기서 상기 절연막(22)의 유효 표면적이 증가함으로서 메인 공정인 건식식각 공정시 종래 보다는 수직한 구조를 갖는 콘택홀(24)을 형성한다.In this case, the effective surface area of the insulating layer 22 is increased to form a contact hole 24 having a vertical structure than in the conventional dry etching process.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택홀 형성방법에 있어서 아르곤 스퍼터링을 건식식각 전에 콘택홀 형성부분에 수행함으로써 수직한 프로파일을 갖는 콘택홀을 형성할 수 있는 효과가 있다.As described above, in the method for forming a contact hole in a semiconductor device according to the present invention, argon sputtering is performed on the contact hole forming portion before dry etching, thereby forming a contact hole having a vertical profile.

Claims (2)

반도체 기판상에 절연막을 형성하는 단계;Forming an insulating film on the semiconductor substrate; 상기 절연막의 표면에 콘택홀 형성영역을 정의하는 단계;Defining a contact hole forming region on a surface of the insulating film; 상기 콘택홀 형성영역으로 정의된 절연막의 표면을 요철 형태로 형성하는 단계; 그리고Forming a surface of the insulating layer defined by the contact hole forming region in a concave-convex shape; And 상기 콘택홀 형성영역으로 정의된 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 콘택홀 형성방법.Forming a contact hole by selectively removing the insulating layer defined as the contact hole forming region. 제 1 항에 있어서, 상기 콘택홀 형성영역이 정의된 절연막의 표면을 요철 형태로 형성하는 방법은 상기 콘택홀 형성영역이 노출되도록 절연막상의 일부에 마스크층을 형성하고, 상기 마스크층을 마스크로 이용하여 아르곤 스퍼터링 공정을 실시하여 형성하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.The method of claim 1, wherein a surface of the insulating film in which the contact hole forming region is defined is formed in a concave-convex shape by forming a mask layer on a portion of the insulating film so that the contact hole forming region is exposed, and using the mask layer as a mask. And argon sputtering to form a contact hole.
KR1019970057983A 1997-11-04 1997-11-04 Method for forming contact hole of semiconductor device KR100268898B1 (en)

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