JPH0427129A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To shorten the length of a gate, reduce gate resistance, and hence improve mechanical strength by forming a semiconductor/Shotokky connection on a first insulation film on the side of a source electrode on a semiconductor, and coating the metal which constitutes the source electrode. CONSTITUTION:An SiO2 film 22 is formed on a semiconductor substrate 21. A Deep-UV group photoresist 23 and a UV group photoresist film 24 are applied to the substrate. The UV group photoresist film 24 is exposed based on a photoengraving process technique where a contact exposure system is applied so that an opening section 24' may be formed. The Deep-UV group photoresist film 23 is exposed and developed where the opening section 24' of the UV group photoresist film is used as a mask. A demolished SiO2 film 22 is subjected to anisotropic etching based on a reactive ion etching process. An opening section whose width is equivalent to that of the UV group photoresist layer 24 is formed on the SiO2 film 22 so that the surface of the semiconductor substrate 21 may be exposed. The gate metals are deposited successively on the semiconductor substrate 21. The UV group photoresist film 24, and the Deep-UV group photoresist film 23 are eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field 1] The present invention relates to a method for manufacturing a field-effect transistor,
In particular, it relates to a method of forming a gate electrode portion.

[Prior Art J] FIG. 2 shows the structure of a Schottky barrier field effect transistor (hereinafter abbreviated as FET) used in a high frequency circuit. A source electrode 2 and a drain electrode β are provided on a semiconductor substrate 1, and a gate electrode 4 is provided between these electrodes.

Conventionally, a method as shown in FIG. 3 has been used to form the gate electrode portion of such an FET.

That is, as shown in FIG. 3(a), an insulating film 5 serving as a spacer is formed on the surface of the semiconductor substrate 1, and a photoresist film 6 is coated on the entire surface, and then a photolithography technique using a contact exposure method is applied. The photoresist at the gate electrode portion is removed to form an opening 6'.

Thereafter, as shown in FIG. 3(b), the insulating film 5 is made wider than the width of the opening 6' in the photoresist film (
(to create an undercut).

Next, metal is deposited onto the surface of the semiconductor substrate 1 in a direction perpendicular to the surface of the semiconductor substrate 1 to form a multilayer gate metal made of a high melting point metal. Finally, the photoresist film 6 is removed (using a lift-off technique), leaving the gate metal that will become the gate electrode 4 shown in FIG. 3(c) on the semiconductor substrate 1.

In order to improve the characteristics of such FETs, the length of the gate electrode in the direction of the source and drain electrodes (Qg, hereinafter abbreviated as gate length) is shortened, and the mutual conductance (gm)
It is important to simultaneously increase the resistance value of the gate electrode (hereinafter abbreviated as gate resistance).

[Problems to be Solved by the Invention] In order to shorten the gate length using photolithography, it has been conventional practice to make the photoresist film as thick as or thinner than the gate length. However, this method has the following problems.

That is, when the photoresist film becomes thin, the photoresist film is deformed by radiant heat generated when depositing the gate metal. For example, as shown in FIG. 4, the photoresist film 6 is warped at the opening. A gate metal 10.1 consisting of a three-layer structure is formed on such a photoresist-6.
1.12, second and third layer metals 11' and 12' are deposited on both ends of the first layer metal 10" in the opening, respectively.
is attached. This not only increases the effective gate length but also adversely affects reliability such as heat resistance of gate electrode characteristics.

In addition, in order to shorten the gate length, there is a method of depositing gate metal on the surface of the semiconductor substrate from an oblique direction (rather than from a direction perpendicular to the surface of the semiconductor substrate) (oblique vapor deposition method).
It has been known.

However, in this case, the mechanical strength of the gate electrode decreases, and the reliability and manufacturing yield of the FET decreases.

On the other hand, when the gate length is shortened, the cross-sectional area of the gate electrode decreases, so the gate resistance increases.

Therefore, the mutual conductance (gm) improves, but
Conversely, high frequency characteristics may deteriorate.

The present invention provides a method for forming a gate electrode that maximizes the advantage of improved characteristics by shortening the gate length, has low gate resistance, and has high mechanical strength.

[Means and effects for solving the problem] In order to solve the above problems, the method for manufacturing a field effect transistor according to the present invention includes: a first step of forming a first insulating film on a semiconductor; a second step of forming a second insulating film on the insulating film; a third step of forming a photoresist film with openings in a predetermined region on the second insulating film; a fourth step of removing the insulating film and forming an opening wider than the width of the opening in the photoresist film; forming an opening narrower than the second insulating film in the first insulating film in the predetermined region; a fifth step of exposing the semiconductor; a sixth step of forming a Schottky junction with the semiconductor on the exposed semiconductor and on the first insulating film on the source electrode side, and covering the exposed semiconductor with a metal constituting the gate electrode; This includes:

More preferably, a second insulating film is a second photoresist film having different photosensitivity from those of the photoresist film, and in the fourth step, the opening is formed in the second photoresist film. It is formed by exposure to light and development.

Further, the sixth step is performed by oblique vapor deposition, and the fifth step is performed by oblique vapor deposition.
It is desirable that a portion of the semiconductor surface exposed in the process on the drain electrode side is not covered with the metal constituting the gate electrode.

With the above configuration, in the sixth step, by forming a part of the gate electrode so as to cover only the first insulating film on the source electrode side, the contact area of the gate electrode can be formed without increasing the gate length. In addition, the capacitance between the gate and drain electrodes, which affects the high frequency characteristics of the FET, does not increase.

In addition, when forming the gate electrode by oblique vapor deposition, the gate electrode can be formed with a gate length shorter than the opening length of the photoresist film formed in the third step.

On the other hand, since the gate resistance is determined by the opening length of the second insulating film, it is lower than the resistance value of the electrode formed by the conventional method.
A reduction in gate resistance and a reduction in gate length can be achieved at the same time.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a detailed illustration of the invention.

As shown in Figure 1(a), GaAs containing N-type impurities
A chemical vapor deposition method (CVD method) is applied onto any semiconductor substrate 21.
Thus, a Sin film 22 is formed to a thickness of about 0.1 μm. On top of that, a deep-UV photoresist film 23 that is sensitive to far ultraviolet rays but not to ultraviolet rays is coated to a thickness of approximately 0.7 μm, and further a UV photoresist film that is sensitized to ultraviolet light to a thickness of 0.5 μm. Apply 24.

Next, using photolithography technology using a contact exposure method, U
The V-based photoresist film 24 is exposed to light to form an opening 24' with a width of 0.5 μm, as shown in FIG. 1(b).

Furthermore, the Deep-UV photoresist film 23 is exposed to UV light.
Exposure and development are performed using the opening 24' of the photoresist film as a mask. At this time, as shown in FIG. 1(C), U
Exposure and development conditions were set so that the opening 23'' of the deep-UV photoresist film 23 had an undercut of 0.3 μm with respect to the V-based photoresist film 24 (the width of the opening 23' was l, 1 μm). Determine.

Next, as shown in FIG. 1(d), Sin.

The film 22 is anisotropically etched by reactive ion etching using CF, +O, and a mixed gas.

Since this etching is anisotropic, the width of the opening in the UV photoresist film 24 is about the same as that of the opening in the film 2.
2 to expose the surface of the semiconductor substrate 21.

Next, as shown in FIG. 1(e), Ti500A, Pt
Gate metal consisting of 100 OA and 3000 Au is sequentially deposited on the semiconductor substrate 21 at an angle of about 10 degrees. Finally, UV photoresist film 24 and Deep
- By removing the UV photoresist M23 (lift-off technique), a gate electrode 25 with a gate length of approximately 0.3 μm is formed.

After that, S is used to form drain and source electrodes.
In, the film 22 is opened and a metal layer suitable for ohmic contact is formed on the exposed semiconductor substrate 21 (not shown).

The FET manufactured by the process described above can obtain a desired short gate length by adjusting the angle of oblique deposition, and at the same time,
Since a part of the gate electrode can be formed on the insulating film, the cross section I of the gate electrode can be formed without losing mechanical strength.
It is possible to widen J'1 and reduce gate resistance. Furthermore, there is no increase in the effective gate length or deterioration in reliability due to deformation of the photoresist film. therefore,
FETs having good high frequency characteristics with good reproducibility can be manufactured.

Note that an insulating film such as a silicon nitride film is used instead of the deep-UV photoresist film 23, and this insulating film is under-etched instead of exposing and developing the deep-UV photoresist film 23. You can also do that.

Further, the drain electrode and the source electrode can also be formed before forming the gate electrode.

[Effects of the Invention] As explained above, the method for manufacturing a field effect transistor according to the present invention includes the steps of: forming a first insulating film on a semiconductor; forming a second insulating film on the first insulating film; a second step of forming an insulating film; a third step of forming a photoresist film with an opening in a predetermined region on the second insulating film; removing the second insulating film in the predetermined region, and removing the photoresist film in the predetermined region; a fourth step of forming an opening wider than the width of the opening in the resist film;
a fifth step of forming an opening narrower than the second insulating film in the first insulating film in the predetermined region and exposing the semiconductor; on the exposed semiconductor and on the first insulating film on the source electrode side; The method includes a sixth step of forming a Schottky junction with the semiconductor and covering the metal constituting the gate electrode.

Therefore, it is possible to create a gate electrode with good reproducibility, which has a short gate length narrower than the width of an opening formed by photolithography, a large cross-sectional area, and strong mechanical strength. It becomes possible to manufacture a field effect transistor with excellent high frequency characteristics.

[Brief explanation of drawings]

FIGS. 1(a) to (c) are cross-sectional views for explaining one embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of a field effect transistor according to the prior art, and FIG. FIG. 4 is a cross-sectional view showing the manufacturing process of a field effect transistor according to the prior art. FIG. 4 is a cross-sectional view showing deformation of a photoresist film according to the prior art. In the figure, 21...Semiconductor substrate, 22...S i ON film, 2
3...Deep-UV photoresist film 24...
UV photoresist film 25...gate electrode. Figures (a) (d) Figure 4 Figure 4 Amendment to Procedures (Method) Date of March 1990

Claims (1)

[Claims] (1) A method for manufacturing a field effect transistor including a source electrode, a drain electrode, and a gate electrode on a semiconductor, including: a first step of forming a first insulating film on the semiconductor; the first insulating film; a second step of forming a second insulating film on the second insulating film; a third step of forming a photoresist film with an opening in a predetermined region on the second insulating film; a fourth step of removing the photoresist film and forming an opening wider than the opening width of the photoresist film; forming an opening narrower than the second insulating film in the first insulating film in the predetermined region; a fifth step of exposing; a sixth step of forming a Schottky junction with the semiconductor on the exposed semiconductor and the first insulating film on the source electrode side, and covering the metal constituting the gate electrode; A method of manufacturing a field effect transistor including.