JPS6237972A - Metal-electrode forming method - Google Patents

Metal-electrode forming method

Info

Publication number
JPS6237972A
JPS6237972A JP17795985A JP17795985A JPS6237972A JP S6237972 A JPS6237972 A JP S6237972A JP 17795985 A JP17795985 A JP 17795985A JP 17795985 A JP17795985 A JP 17795985A JP S6237972 A JPS6237972 A JP S6237972A
Authority
JP
Japan
Prior art keywords
resist
opening
forming
electrode
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17795985A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamashita
山下 普
Yoshihiro Todokoro
義博 戸所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17795985A priority Critical patent/JPS6237972A/en
Publication of JPS6237972A publication Critical patent/JPS6237972A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a low resistance electrode, whose pattern width is controlled highly accurately, by forming an opening part, whose cross section is of an inverted trapezoidal-shape, in an insulating film on a substrate, forming an etched recess part in the substrate through the opening part, and thereafter depositing and forming an electrode metal in the opening part. CONSTITUTION:An insulating film 9 of SiO2 is grown on a substrate 8 comprising a GaAs active layer. Then a gate pattern is formed with polymethyl methacrylate resist 10. The film 9 is etched with the mixed liquid of HF and NH4F. An opening part, whose cross section is of an inverted trapezoidal-shape, is formed. The width of the lower surface side of the opening is the same as that of the opening pattern of the resist 10. After the opening of the resist 10 is expanded, the substrate 8 undergoes isotropic etching, and an etched recess part is formed. Then, an Al film 11 is evaporated. Finally the resist 10 is removed, and a low gate resistance electrode 12, which is supported by the inverted trapezoidal-shaped opening part, is formed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、金属電極形成方法、特にショットキー障壁形
ゲート構造電界効果トランジスタ(以下、MESFET
と略称する)における低ゲート抵抗電極の形成に有効な
金属電極形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming metal electrodes, particularly to a Schottky barrier gate structure field effect transistor (hereinafter referred to as MESFET).
The present invention relates to a method for forming a metal electrode that is effective for forming a low gate resistance electrode.

27、 従来の技術 従来、この種の低ゲート抵抗電極形成方法は、第2図a
 −eの工程順断面図に示すような構成であった。すな
わち、従来例を順次説明すると、第2図aに示すように
、GaAs活性層1上に低感度ポジ形レジスト2、その
上に高感度ポジ形レジスト3を塗布し、第2図すに示す
ように、電子ビーム4を用いてゲートパターンを露光す
る。第2図Cに示すように、現像によって開口断面丁字
形のレジスト開口部5を得る。ここで、下方のレジスト
2に比べ、上方のレジスト3のパターン幅が広くなるの
は、上方のレジスト3が高感度であるため溶解速度が下
方のレジスト2に比べ大きくなるからである。次に、第
2図dのように、ゲート電極用の金属6を蒸着し、最後
に、第2図eに示すように、レジスト2,3を除去して
リフトオフにより丁字形の断面形状をもつ低ゲート抵抗
電極7を得る。
27. Conventional technology Conventionally, this type of low gate resistance electrode formation method is shown in Fig. 2a.
The structure was as shown in the step-by-step sectional view of -e. That is, to explain the conventional example sequentially, as shown in FIG. 2a, a low-sensitivity positive resist 2 is coated on the GaAs active layer 1, and a high-sensitivity positive resist 3 is applied thereon. The gate pattern is exposed using the electron beam 4 as shown in FIG. As shown in FIG. 2C, a resist opening 5 having a T-shaped cross section is obtained by development. Here, the reason why the pattern width of the upper resist 3 is wider than that of the lower resist 2 is because the upper resist 3 has a high sensitivity and therefore has a higher dissolution rate than the lower resist 2. Next, as shown in FIG. 2d, a metal 6 for the gate electrode is deposited, and finally, as shown in FIG. 2e, the resists 2 and 3 are removed and lifted off to form a T-shaped cross-sectional shape. A low gate resistance electrode 7 is obtained.

発明が解決しようとする問題点 このような従来の構成では、ゲート電極の径大な上面側
電極幅および径小々下面側電極幅のパターン幅制御が難
しいという問題点があった。その理由は、レジストの開
口部断面形状が丁字形となる2種類のレジストの組み合
せと、露光、現像の制御が難しいからである。さらに、
リフトオフが難しいという問題点もあった。そのために
、再現よくゲート電極を形成することができなかった。
Problems to be Solved by the Invention In such a conventional configuration, there is a problem in that it is difficult to control the pattern width of the large-diameter upper surface electrode width and the small-diameter lower surface electrode width of the gate electrode. The reason for this is that it is difficult to combine two types of resists such that the resist opening has a T-shaped cross-sectional shape, and that it is difficult to control exposure and development. moreover,
There was also the problem that lift-off was difficult. Therefore, it was not possible to form a gate electrode with good reproducibility.

また、形成したゲート電極は、上面部が下面部より大き
い構造であるために物理的強度が不足しており、ゲート
電極が破損し易いという問題点があった。本発明は、こ
のような問題点を解決するもので、高精度のパターン幅
制御が可能々再現性のよい物理的強度が充分な低ゲート
抵抗電極の製作を目的としている。
Furthermore, since the formed gate electrode has a structure in which the upper surface portion is larger than the lower surface portion, physical strength is insufficient, and there is a problem in that the gate electrode is easily damaged. The present invention solves these problems, and aims to manufacture a low gate resistance electrode with sufficient physical strength, which allows highly accurate pattern width control, and has good reproducibility.

問題点を解決するだめの手段 この問題点を解決するために、本発明は、半導体基板上
の絶縁膜に、レジストマスクを介して、断面逆台形の開
口部を形成する工程、前記半導体基板に、前記開口を通
じて、食刻凹部を形成する工程、全面に電極用金属を蒸
着形成する工程、前記レジストマスクと共に同上の前記
電極用金属をリフトオフによって除去し、金属電極を前
記半導体基板の食刻四部および前記絶縁膜の断面逆台形
開口部に被覆形成する工程をそなえた金属電極形成方法
である。
Means for Solving the Problem In order to solve this problem, the present invention provides a step of forming an opening with an inverted trapezoidal cross section in an insulating film on a semiconductor substrate through a resist mask, , forming an etched recess through the opening, forming an electrode metal on the entire surface by vapor deposition, removing the electrode metal together with the resist mask by lift-off, and removing the metal electrode from the four etched portions of the semiconductor substrate. and a method for forming a metal electrode, comprising the step of forming a coating on an opening with an inverted trapezoidal cross section of the insulating film.

作  用 この構成により、高精度のパターン幅制御が可能であり
、再現性がよく、しかも充分な物理的強度を持つ低ゲー
ト抵抗電極を形成することができる0 実施例 第1図a〜hば、本発明の一実施例によるMESFET
における低ゲート抵抗電極形成方法を示人の厚さに成長
させ、その上にポリメチルメタクリレート(PMMA 
)レジスト1oを厚さ5000人、スピンコード方法に
よって塗布する。PMAレジスト10を170℃で20
分間ベーキングし5、、−。
Function: With this configuration, it is possible to control the pattern width with high precision, and it is possible to form a low gate resistance electrode with good reproducibility and sufficient physical strength. , MESFET according to an embodiment of the present invention
The method for forming a low gate resistance electrode is shown in Figure 1.
) A resist 1o is applied to a thickness of 5,000 yen by a spin cord method. PMA resist 10 at 170℃
Bake for 5 minutes.

た後、第1図すに示すように、電子ビーム露光によって
露光量64μc/cniでゲートパターンを描画し、現
像液のメチルイソブチルケトン(MIBK)による4分
間の現像によってレジストゲートパターンを得る。PM
MAレジスト10をマスクとして、第1図Cに示すよう
にHFとNH4Fとの混合液によりS 102膜9をウ
ェットエツチングし、S i 02膜9の下面側の開口
幅が、PMMAレジスト1oの開ロバターンと同じ幅に
なるようにする。
After that, as shown in FIG. 1, a gate pattern is drawn by electron beam exposure at an exposure dose of 64 μc/cni, and a resist gate pattern is obtained by development for 4 minutes with a developer of methyl isobutyl ketone (MIBK). PM
Using the MA resist 10 as a mask, the S102 film 9 is wet-etched with a mixed solution of HF and NH4F as shown in FIG. Make it the same width as the donkey pattern.

第1図dに示すように紫外光によってSiO2膜上面側
の開口幅よりやや小さい幅をマスクによって一括露光し
、MIBKTPMMAL/シスト1oを再度4分間現像
し、第1図eに示すように、←開口拡張されたレジスト
開口部を得る。次に硫酸:過酸化水素:水−8:1:1
の混合液でGaAs活性層8を開口部から等方性エッチ
し、同開口部基板に食刻凹部(リセス)を形成すること
により第1図fに示す断面形状を得ることができる。そ
の後、第1図qに示すようにゲート金属のアルミニウム
膜(Al)11を蒸着し、最後に、第1図h61、7 に示すようにPMMAレジスト10をトリクロルエチレ
ンのボイルによって除去すること、いわゆる、リフトオ
フ技法で、SiO2膜9の逆台形開口部に支持された低
ゲート抵抗電極12を形成することができる。
As shown in Fig. 1 d, a width slightly smaller than the opening width on the upper surface side of the SiO2 film was exposed at once to ultraviolet light using a mask, and MIBKTPMMAL/cyst 1o was developed again for 4 minutes, as shown in Fig. 1 e. Obtain an expanded resist opening. Next, sulfuric acid: hydrogen peroxide: water - 8:1:1
By isotropically etching the GaAs active layer 8 from the opening with a mixed solution of the above and forming an etched recess in the substrate at the opening, the cross-sectional shape shown in FIG. 1F can be obtained. Thereafter, as shown in FIG. 1q, an aluminum film (Al) 11 as a gate metal is deposited, and finally, the PMMA resist 10 is removed by boiling trichlorethylene, as shown in FIG. The low gate resistance electrode 12 supported in the inverted trapezoidal opening of the SiO2 film 9 can be formed using a lift-off technique.

以上のように本実施例によれば、低ゲート抵抗電極の下
面側のパターン幅は、はじめに形成した絶縁膜の下面側
の開口幅により決定される。また、低ゲート抵抗電極上
面側のパターン幅は、2回目のリングラフィ工程により
決定される。従って上面側および下面側のパターン幅を
独立に、精度。
As described above, according to this embodiment, the pattern width on the lower surface side of the low gate resistance electrode is determined by the opening width on the lower surface side of the insulating film formed first. Further, the pattern width on the upper surface side of the low gate resistance electrode is determined by the second phosphorography process. Therefore, the pattern width on the top side and bottom side can be set independently and accurately.

再現性よく制御することができる。さらに低ゲート抵抗
電極は、絶縁性薄膜により支持されているので充分な物
理的強度を持っている。しかも、ゲート電極の上面部と
接触する絶縁性薄膜は、GaAs活性層のリセスエッチ
ングにより直接G a A s活性層と接触しない。従
って容量の増加を最小限におさえることができる。
It can be controlled with good reproducibility. Furthermore, since the low gate resistance electrode is supported by an insulating thin film, it has sufficient physical strength. Furthermore, the insulating thin film that contacts the upper surface of the gate electrode does not directly contact the GaAs active layer due to recess etching of the GaAs active layer. Therefore, the increase in capacity can be kept to a minimum.

発明の効果 以上のように本発明によれば、高精度のパターン幅制御
が可能であり、再現性がよく、しかも充分な物理的強度
を持つ、低ゲート抵抗電極を形成することができる。
Effects of the Invention As described above, according to the present invention, it is possible to control the pattern width with high accuracy, and to form a low gate resistance electrode with good reproducibility and sufficient physical strength.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図   は、本発明の一実施例によるMESFET
における低ゲート抵抗電極形成方法を示す工程順断面図
、第2図は従来法による低ゲート抵抗電極形成方法を示
す工程順断面図である。 1・・・・・・G a A s活性層、2・・・・・・
低感度ポジ形レジスト、3・・・・・・高感度ポジ形レ
ジスト、4・・・・・・電子ビーム、6・・・・・・断
面T字形レジスト開ロバターン、6・・・・・・ゲート
金属、7・・・・・・丁字形ゲート電極、8・・・・・
・G a A s活性層、9・・・・・・SiO2膜、
10・旧・・PMMAレジスト、11・・・・・・A1
112・山・・低ゲート抵抗電極。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名歌
FIG. 1 shows a MESFET according to an embodiment of the present invention.
FIG. 2 is a step-by-step sectional view showing a method for forming a low gate resistance electrode according to a conventional method. 1...G a As active layer, 2...
Low-sensitivity positive resist, 3... High-sensitivity positive resist, 4... Electron beam, 6... T-shaped cross-section resist open pattern, 6... Gate metal, 7... T-shaped gate electrode, 8...
・G a As active layer, 9...SiO2 film,
10. Old... PMMA resist, 11... A1
112・Mountain・・Low gate resistance electrode. Name of agent: Patent attorney Toshio Nakao and one other person

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上の絶縁膜に、レジストマスクを介し
て、断面逆台形の開口部を形成する工程、前記半導体基
板に、前記開口を通じて、食刻凹部を形成する工程、全
面に電極用金属を蒸着形成する工程、前記レジストマス
クと共に同上の前記電極用金属をリフトオフによって除
去し、金属電極を前記半導体基板の食刻凹部および前記
絶縁膜の断面逆台形開口部に被覆形成する工程をそなえ
た金属電極形成方法。
(1) A step of forming an opening with an inverted trapezoidal cross section in an insulating film on a semiconductor substrate through a resist mask, a step of forming an etched recess in the semiconductor substrate through the opening, and a step of forming an etched recess on the entire surface with metal for an electrode. the electrode metal is removed together with the resist mask by lift-off, and the etched recess of the semiconductor substrate and the inverted trapezoid cross-sectional opening of the insulating film are coated with the metal electrode. Metal electrode formation method.
JP17795985A 1985-08-13 1985-08-13 Metal-electrode forming method Pending JPS6237972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17795985A JPS6237972A (en) 1985-08-13 1985-08-13 Metal-electrode forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17795985A JPS6237972A (en) 1985-08-13 1985-08-13 Metal-electrode forming method

Publications (1)

Publication Number Publication Date
JPS6237972A true JPS6237972A (en) 1987-02-18

Family

ID=16040071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17795985A Pending JPS6237972A (en) 1985-08-13 1985-08-13 Metal-electrode forming method

Country Status (1)

Country Link
JP (1) JPS6237972A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63263770A (en) * 1987-04-20 1988-10-31 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Gaas mesfet and manufacture of the same
CN103721363A (en) * 2014-01-27 2014-04-16 济南同日数控设备有限公司 External fire-fighting multi-medium quick joint

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211785A (en) * 1981-06-23 1982-12-25 Sanyo Electric Co Ltd Electrode formation of semiconductor device
JPS6074579A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211785A (en) * 1981-06-23 1982-12-25 Sanyo Electric Co Ltd Electrode formation of semiconductor device
JPS6074579A (en) * 1983-09-30 1985-04-26 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63263770A (en) * 1987-04-20 1988-10-31 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Gaas mesfet and manufacture of the same
CN103721363A (en) * 2014-01-27 2014-04-16 济南同日数控设备有限公司 External fire-fighting multi-medium quick joint

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