JPS62250674A - Manufactire of semiconductor device - Google Patents
Manufactire of semiconductor deviceInfo
- Publication number
- JPS62250674A JPS62250674A JP9555586A JP9555586A JPS62250674A JP S62250674 A JPS62250674 A JP S62250674A JP 9555586 A JP9555586 A JP 9555586A JP 9555586 A JP9555586 A JP 9555586A JP S62250674 A JPS62250674 A JP S62250674A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- gate
- layer
- gaas
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000004090 dissolution Methods 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000001771 vacuum deposition Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000004528 spin coating Methods 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特にガリウムヒ素電界効果型ト
ランジスタ（ＧａＡｓ ＦＩＴ）のゲート電極の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a gate electrode of a semiconductor device, particularly a gallium arsenide field effect transistor (GaAs FIT).
従来、この桟の短ゲート長のゲートを有するＧａＡａ
ＦＥＴの製造方法は、一層のホトレジストをホトリソグ
ラフィーを用いてゲート形成予定地を開口し、ＧａＡｓ
表面を露出した後ゲート金属を被着し、リフトオフ法に
よりゲートを形成する方法が一般にとられている。Conventionally, GaAa having a gate with a short gate length on this crosspiece
The FET manufacturing method is to open a layer of photoresist using photolithography to form a gate, and then deposit GaAs.
Generally, a method is used in which a gate metal is deposited after exposing the surface and a gate is formed by a lift-off method.
上述した従来のゲート形成法では、以下の様な欠点があ
る。即ち、ゲート長短縮に伴うゲート抵抗の増大が、Ｇ
ａＡａ ＦＥＴの雑音特性等に悪影響を及ぼすことであ
る。例えばゲート断面が長方形と仮定した場合、ゲート
金属厚が同じであれば、ゲート長とゲート抵抗は反比例
の関係となる。The conventional gate forming method described above has the following drawbacks. In other words, the increase in gate resistance due to the shortening of the gate length
aAa This has an adverse effect on the noise characteristics of the FET. For example, assuming that the gate cross section is rectangular, the gate length and gate resistance are inversely proportional if the gate metal thickness is the same.
本発明によるゲート電極の製造方法は、半導体基板上に
絶縁膜を被着する工程と、さらにその上に上層のホトレ
ジストが、下層のホトレジストよりも現像液への溶解速
度が遅い、二層のホトレジストを被着し、その溶解速度
の違いにより、二層のホトレジスト膜の断面形状を逆階
段状にする工程と、絶縁膜をドライエッチによりエツチ
ング開口し、半導体表面を露出する工程と、さらに上層
のホトレジストを０２アッシャ−により除去し、しかる
後にゲート金属を全面に被着する工程を含むことを特徴
とし、下層のホトレジストと絶縁膜の断面形状が階段状
となるため、ゲート金属の断面形状がＴ型とすることが
でき、従ってゲート長を短かくなおかつゲート抵抗も小
さい半導体を提供することができる。The method for manufacturing a gate electrode according to the present invention includes the steps of depositing an insulating film on a semiconductor substrate, and further forming a two-layer photoresist layer on which the upper layer photoresist has a slower dissolution rate in a developer than the lower layer photoresist. The second step is to make the cross-sectional shape of the two-layer photoresist film into a reverse staircase shape due to the difference in dissolution rate, the second step is to dry-etch the insulating film to expose the semiconductor surface, and the second step is to make the upper layer The feature is that it includes a step of removing the photoresist using an 02 asher and then depositing the gate metal on the entire surface, and since the cross-sectional shape of the underlying photoresist and the insulating film is step-like, the cross-sectional shape of the gate metal is T. Therefore, it is possible to provide a semiconductor having a short gate length and low gate resistance.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
ＧａＡｓ基板上１に、シリコン酸化膜２をＣＶＤ法によ
り１，５００Ｘ被着する。次に、ポジ型ホトレジスト（
ＡＺ１３５０Ｊ）３をスピンコード法で約１．０ μｍ
被着し、フレオンガス及び水素ガスによるドライエッチ
を行うことでこのホトレジスト表面に変成層４を形成す
る。続いてポジ型ホトレジスト（ＡＺ２４００）５をス
ピンコード法で約０．５μｍ被着する（第２図）。その
後ゲート形成予定地６の露光を行い、ＡＺ２４０１ 現
像液で上層のホトレジスト（ＡＺ２４００）５を現像し
た後、酸素プラズマによりＡＺ１３５ＱＪ表面の変成層
４を除去する（第３図）さらにＡＺｆｌｌ像液により下
層のホトレジスト３（ＡＺ１３５０Ｊ）ｔ−現像した後
さらＫＡＺ２４０１ 現像液ニ浸ス。コノ時下層ノＡｚ
１３５０Ｊ３ノＡｚ２４０１現像液への溶解速度が速い
ため、シリコン酸化膜２ｇ出抜０ＡＺ１３５０Ｊ３ と
ＡＺ２４００５ （７）断面形状は第４図の如く逆階段
状となる（第４図）。しかる後７レオンガスと水素ガス
によるドライエッチにてシリコン酸化膜２をエツチング
開口し、ＧａＡｓ表面１を露出させる（第５図）。A silicon oxide film 2 is deposited at 1,500× on a GaAs substrate 1 by CVD. Next, apply a positive photoresist (
AZ1350J)3 to approximately 1.0 μm using spin code method
A metamorphic layer 4 is formed on the surface of the photoresist by dry etching using Freon gas and hydrogen gas. Subsequently, a positive photoresist (AZ2400) 5 is deposited to a thickness of about 0.5 μm using a spin code method (FIG. 2). Thereafter, the gate formation area 6 is exposed, and the upper layer photoresist (AZ2400) 5 is developed with an AZ2401 developer, and the metamorphic layer 4 on the AZ135QJ surface is removed using oxygen plasma (Fig. 3). After developing Photoresist 3 (AZ1350J), immerse it in KAZ2401 developer. Kono time lower layer Az
Since the rate of dissolution of 1350J3 into the AZ2401 developer is fast, the cross-sectional shape of the 2g silicon oxide film (0AZ1350J3 and AZ24005) becomes a reverse staircase shape as shown in FIG. 4 (FIG. 4). Thereafter, the silicon oxide film 2 is etched open by dry etching using 7 Leon gas and hydrogen gas, and the GaAs surface 1 is exposed (FIG. 5).
次［ｃＩＩ素プラズマにより上層レジス） （ＡＺ２４
００）５を除去した後全面にゲート金属としてアルミニ
ウム７を真空蒸着法によ＃）０．５μｍ被着する（第６
図）。Next [upper layer resist by cII elementary plasma] (AZ24
00) After removing 5, 0.5 μm of aluminum 7 is deposited as a gate metal on the entire surface by vacuum evaporation method (#6)
figure).
次に有機溶剤により下層レジストＡＺ１３５０Ｊ３を除
去することで余分なアルミニウムをリフトオフする（第
７図）。Next, excess aluminum is lifted off by removing the lower resist AZ1350J3 with an organic solvent (FIG. 7).
以上説明したように本発明によってゲート形成を行った
ＧａＡｓ ＦＥＴはゲート長も十分短く、しかもゲート
の断面積が広く従りてゲート抵抗も小さく、非常に良好
なＲＦ’特性を得ることができる。As explained above, the GaAs FET whose gate is formed according to the present invention has a sufficiently short gate length, a wide cross-sectional area of the gate, and a low gate resistance, and can obtain very good RF' characteristics.
以上本発明の実施例として特定な材料、特定の条件下で
説明したが、本技術思想からもこれらに限定される事な
く、例えばＧａＡｓに限らずシリコンや他の半導体の製
造方法にも適用されることは言うまでもない。Although the embodiments of the present invention have been described using specific materials and specific conditions, the technical concept of the present invention is not limited thereto, and can be applied to methods of manufacturing not only GaAs but also silicon and other semiconductors. Needless to say.
第１図は本発明によるゲート近傍の縦断面図、第２図乃
至第６図は本発明の一実施例の各工程断面図である。
ｌ・・・・・・ＱａＡｓ、２・・・・・・シリコン酸化
膜、３・・・・・・ＡＺ１３５０Ｊ、４ ・−・・−Ａ
Ｚ１３５０Ｊ’＆成ｍ、５ 、、・、、−ＡＺ２４００
．６・・・・・・ゲート形成予定地、７・・・・・・ア
ルミニウム。
代理人 弁理士 内 原 −１、日 、、
。
茅 ４Ｉ！１
斗 ５ 回
茅 ＡＩ！ｒFIG. 1 is a longitudinal cross-sectional view of the vicinity of the gate according to the present invention, and FIGS. 2 to 6 are cross-sectional views of each process in an embodiment of the present invention. 1...QaAs, 2...Silicon oxide film, 3...AZ1350J, 4...-A
Z1350J'& Narumi, 5,..., -AZ2400
．． 6... Planned site for gate formation, 7... Aluminum. Agent Patent Attorney Uchihara -1, Japan.
. Kaya 4I! 1 Do 5 Kaya AI! r
Claims (1)
に上層のホトレジストが、下層のホトレジストよりも現
像液への溶解速度が遅い、二層のホトレジスト膜を被着
し、その溶解速度の違いにより、該ホトレジスト膜の断
面形状を逆階段状にする工程と、絶縁膜をドライエッチ
によりエッチング開口し、半導体表面を露出する工程と
、さらに上層のホトレジストをＯ＿２アッシャーにより
除去し、しかる後にゲート金属を全面に被着する工程を
含むことを特徴とする半導体装置の製造方法。The process involves depositing an insulating film on the semiconductor substrate, and then depositing a two-layer photoresist film on top of which the upper photoresist has a slower dissolution rate in a developing solution than the lower photoresist. Depending on the difference, there is a step to make the cross-sectional shape of the photoresist film into a reverse step-like shape, a step to dry-etch the insulating film to expose the semiconductor surface, and a step to remove the upper layer of photoresist using O_2 asher, and then remove the gate. A method for manufacturing a semiconductor device, comprising a step of depositing metal on the entire surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9555586A JPS62250674A (en) | 1986-04-23 | 1986-04-23 | Manufactire of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9555586A JPS62250674A (en) | 1986-04-23 | 1986-04-23 | Manufactire of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62250674A true JPS62250674A (en) | 1987-10-31 |
Family
ID=14140825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9555586A Pending JPS62250674A (en) | 1986-04-23 | 1986-04-23 | Manufactire of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62250674A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110751A (en) * | 1990-02-26 | 1992-05-05 | Rohm Co., Ltd. | Method of manufacturing a compound semiconductor device |
| JPH0689907A (en) * | 1991-05-28 | 1994-03-29 | Hughes Aircraft Co | Method for formation of t-shaped gate structure on microelectronic-device substrate |
-
1986
- 1986-04-23 JP JP9555586A patent/JPS62250674A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5110751A (en) * | 1990-02-26 | 1992-05-05 | Rohm Co., Ltd. | Method of manufacturing a compound semiconductor device |
| JPH0689907A (en) * | 1991-05-28 | 1994-03-29 | Hughes Aircraft Co | Method for formation of t-shaped gate structure on microelectronic-device substrate |
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