JPH045834A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH045834A
JPH045834A JP10675390A JP10675390A JPH045834A JP H045834 A JPH045834 A JP H045834A JP 10675390 A JP10675390 A JP 10675390A JP 10675390 A JP10675390 A JP 10675390A JP H045834 A JPH045834 A JP H045834A
Authority
JP
Japan
Prior art keywords
thin film
organic thin
opening
forming
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10675390A
Other languages
Japanese (ja)
Inventor
Hiromitsu Aoki
青木 裕光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP10675390A priority Critical patent/JPH045834A/en
Publication of JPH045834A publication Critical patent/JPH045834A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain a T-shaped gate metal which does not cause a disconnection by a method wherein, when a gate metal is attached to a compound semiconductor device, a heat treatment is executed, a taper is formed only at a pattern by a second organic thin film, at the upper part, whose heat-treatment property is bad out of gate patterns by a first organic thin film and the second organic thin film and the pattern is expanded. CONSTITUTION:A resist thin film 2 which excels in a close contact property and a heat-resistance property is formed on an N-type active layer 1 of GaAs; a resist film 3 whose heat-resistant property is inferior to that of the film 2 is formed on it. Then, the resist films are simultaneously irradiated selectively with an electron beam; the film 3 is developed; an opening part 3a in a fine gate pattern is formed. After that, the layer 1 is wet-etched while an opening part 2a formed in the film 2 is used as a mask; an opening part 1a in an inverted mesa shape is formed; a heat treatment is executed; only the opening part 3a is expanded while a taper is being formed. Then, a gate metal 4 is applied to the whole surface while the opening part 1a is being filled; a photosensitive- resist thin film 5 in a prescribed shape is formed on it; a dry-etching operation is executed; only the metal 4 having a taper is left.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置、特に化合物半導体装置の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, particularly a compound semiconductor device.

従来の技術 近年、化合物半導体装置は化合物半導体か有する高い移
動度のためにコンピュータなとの高速演算素子や衛星放
送および衛星通信さらに自動車電話や携帯電話なとの移
動体通信に使用される高周波低雑音の送受信増幅素子と
して期待されている。
Background of the Invention In recent years, compound semiconductor devices have been used as high-speed arithmetic elements in computers, satellite broadcasting and satellite communications, and high-frequency and low-frequency devices used in mobile communications such as car phones and mobile phones, due to the high mobility of compound semiconductors. It is expected to be used as a noise transmission/reception amplification device.

以下、第2図に基づき従来の化合物半導体装置の製造方
法の一例について説明する。
An example of a conventional method for manufacturing a compound semiconductor device will be described below with reference to FIG.

第2図は従来の化合物半導体装置のゲートメタル形成工
程を示したちのである。第2図(a)において、Iはガ
リウムヒ素のn型活性層で、このn型活性層lの上には
ガリウムヒ素との密着性に優れ、300°Cまての耐熱
性に優れ、さらに電子ビームや近紫外線に感光するPM
G Iレジスト薄膜2か設けられている。このPMG 
Iレジスト薄膜2の上には150°Cまての耐熱性しか
有さない電子ビムや近紫外線に優れた感度を有し微細パ
ターンか形成てきるPMMAレジスト薄膜3が設けられ
ている。また、第2図(C)において、4はガリウムヒ
素のn型活性層1とショットキーゲートを形成するため
のゲートメタルである。第2図(d)において、5はゲ
ートメタル4の断面形状をT字型に加工するための感光
性レジスト薄膜である。
FIG. 2 shows the process of forming a gate metal of a conventional compound semiconductor device. In Figure 2 (a), I is an n-type active layer of gallium arsenide, and on top of this n-type active layer l is excellent adhesion with gallium arsenide, excellent heat resistance up to 300°C, and PM sensitive to electron beams and near ultraviolet rays
A GI resist thin film 2 is provided. This PMG
On the I resist thin film 2, there is provided a PMMA resist thin film 3 which has a heat resistance of only up to 150° C. and has excellent sensitivity to near ultraviolet light and can form fine patterns. Further, in FIG. 2(C), 4 is a gate metal for forming a Schottky gate with the n-type active layer 1 of gallium arsenide. In FIG. 2(d), 5 is a photosensitive resist thin film for processing the cross-sectional shape of the gate metal 4 into a T-shape.

次に1以上のように構成される化合物半導体装置のゲー
トメタル形成工程について説明する。
Next, a gate metal forming process for a compound semiconductor device having one or more structures will be described.

まず、第2図(a)において、ガリウムヒ素のn型活性
層lの上に密着性と耐熱性に優れたPMGIレジスト薄
膜2を回転塗布と250°C熱処理によって形成する。
First, in FIG. 2(a), a thin PMGI resist film 2 having excellent adhesion and heat resistance is formed on the n-type active layer l of gallium arsenide by spin coating and heat treatment at 250°C.

次に、前記PMCIレジスト薄膜2の上にPMMAレジ
スト薄膜3を回転塗布と120°C熱処理によって形成
する。次に、前記PMMAレジスト薄膜3とPMG I
レジスト薄膜2に電子ビームを用いた選択照射によって
同時露光を行なう。次に、前記PMMAレジスト薄膜3
を現像して微細なゲートパターンの開口部3aを形成す
る。次に、前記P M M Aレジスト薄膜3の開口部
3aをマススとして前記PMCIレジスト薄膜2を現像
して同一のゲートパターンの開口部2aを形成する。次
に、第2図(b)において、前記PMG Tレジスト薄
膜2の開口部2aをマスクとして前記ガリウムヒ素のn
型活性層lをウェットエツチングして逆メサ形状に開口
部1aを形成する。次に第2図(C)において、電子ビ
ーム蒸着法を用いてPMMAレジスト薄膜3の上から、
ゲートメタル4を全面蒸着する。次に、第2図(d)に
おいて、前記ゲートメタル4の上に回転塗布と120°
C熱処理によって感光性レジスト薄膜5を形成する。次
に、選択露光と現像によって前記PMM△レジスト薄膜
3のゲートパターンの開口部3aよりも大きいゲートの
残しパターンを形成する。次に、第2図(e)において
、前記感光性レジスト薄膜5のゲート残しパターンを用
いて前記ゲートメタル4をドライエツチングして前記感
光性レジスト薄膜5と同一の形状を形成する。最後に第
2図(f)において、前記感光性レジスト薄膜5とPM
MAレジスト薄膜3およびPMG Iレジスト薄膜2を
す、べて有機溶剤に溶解させて除去する。
Next, a PMMA resist thin film 3 is formed on the PMCI resist thin film 2 by spin coating and heat treatment at 120°C. Next, the PMMA resist thin film 3 and PMG I
Simultaneous exposure is performed on the resist thin film 2 by selective irradiation using an electron beam. Next, the PMMA resist thin film 3
is developed to form a fine gate pattern opening 3a. Next, the PMCI resist thin film 2 is developed using the opening 3a of the PMMA resist thin film 3 as a mass to form an opening 2a having the same gate pattern. Next, in FIG. 2(b), using the opening 2a of the PMG T resist thin film 2 as a mask, the n of the gallium arsenide is removed.
The mold active layer 1 is wet-etched to form an opening 1a in the shape of an inverted mesa. Next, in FIG. 2(C), from above the PMMA resist thin film 3 using the electron beam evaporation method,
Gate metal 4 is deposited on the entire surface. Next, in FIG. 2(d), spin coating is performed on the gate metal 4 at 120°.
A photosensitive resist thin film 5 is formed by C heat treatment. Next, a remaining gate pattern larger than the opening 3a of the gate pattern of the PMMΔ resist thin film 3 is formed by selective exposure and development. Next, in FIG. 2(e), the gate metal 4 is dry etched using the gate remaining pattern of the photosensitive resist thin film 5 to form the same shape as the photosensitive resist thin film 5. Finally, in FIG. 2(f), the photosensitive resist thin film 5 and the PM
The MA resist thin film 3 and the PMG I resist thin film 2 are all dissolved in an organic solvent and removed.

発明か解決しようとする課題 しかしなから、上記のような構成では第2図(f)に示
すように感光性レジスト薄膜5とPMMAレジスト薄膜
3及びPMCIレジスト薄膜2をすべて有機溶剤に溶解
させて除去するときに、PMMAレジスト薄膜2の上の
ゲートメタル4が一緒にリフトオンされてしまい、T字
型のゲート構造を形成することかできないといった問題
を有していた。
However, in the above structure, as shown in FIG. 2(f), the photosensitive resist thin film 5, the PMMA resist thin film 3, and the PMCI resist thin film 2 are all dissolved in an organic solvent. When removing the PMMA resist thin film 2, the gate metal 4 on top of the PMMA resist thin film 2 is lifted on together with the PMMA resist thin film 2, resulting in a problem that a T-shaped gate structure cannot be formed.

本発明は、このような課題を解決するもので、ガリウム
ヒ素のn型活性層をウェットエツチングして逆メサ形状
に形成した後、熱処理をしてPMMAレジスト薄膜のゲ
ートパターンのみを拡げることによって断線のないT字
型のゲート構造を形成てきる半導体装置の製造方法を提
供することを目的とするものである。
The present invention solves these problems by wet-etching the n-type active layer of gallium arsenide to form an inverted mesa shape, and then heat-treating it to expand only the gate pattern of the PMMA resist thin film, thereby preventing disconnection. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a T-shaped gate structure without a gate structure.

課題を解決するための手段 この課題を解決するために本発明は、半導体基板の上に
電子ビームあるいは近紫外線に感光する第1の有機薄膜
を形成する工程と、前記第1の有機薄膜の上に電子ビー
ムあるいは近紫外線に感光しかつ前記第1の有機薄膜よ
り耐熱性か悪く熱処理によって形状変化を起こす第2の
有機薄膜を形成する工程と、前記第2および第1の有機
薄膜に電子ビームの選択照射あるいは近紫外線の選択露
光を行なう工程と、現像によって前記第2の有機薄膜に
第1の開口部を形成する工程と、前記第1の開口部をマ
スクとして現像によって前記第1の有機薄膜に第2の開
口部を形成する工程と、前記第2の開口部をマスクとし
てエツチングにより前記半導体基板に第3の開口部を形
成する工程と、熱処理によって前記第1の開口部に傾斜
を付けて前記第1の開口部を拡げる工程と、前記第2の
有機薄膜の上からメタルを全面蒸着する工程と、前記メ
タルの上に感光性を有しかつ耐腐食性に優れた第3の有
機薄膜を形成する工程と、前記第3の有機薄膜に選択露
光と現像を行なって前記第1の開口部より大きな残しパ
ターンを形成する工程と、前記第3の有機薄膜の残しパ
ターンをマスクとして前記メタルをエツチングする工程
と、前記第1、第2、第3の有機薄膜を有機溶剤を用い
てすべて除去して前記第3の開口部上にT字型のメタル
を形成する工程とからなるものである。
Means for Solving the Problems In order to solve the problems, the present invention includes a step of forming a first organic thin film sensitive to electron beams or near ultraviolet light on a semiconductor substrate, and forming a first organic thin film on the first organic thin film. forming a second organic thin film that is sensitive to electron beams or near ultraviolet rays and has poorer heat resistance than the first organic thin film and undergoes shape change upon heat treatment; a step of performing selective irradiation or selective exposure to near ultraviolet rays; a step of forming a first opening in the second organic thin film by development; and a step of forming a first opening in the second organic thin film by development using the first opening as a mask. forming a second opening in the thin film; forming a third opening in the semiconductor substrate by etching using the second opening as a mask; and forming a slope in the first opening by heat treatment. a step of depositing a metal on the entire surface from above the second organic thin film; and a step of depositing a third film having photosensitivity and excellent corrosion resistance on the metal. a step of forming an organic thin film, a step of selectively exposing and developing the third organic thin film to form a remaining pattern larger than the first opening, and using the remaining pattern of the third organic thin film as a mask. The method includes etching the metal, and removing all the first, second, and third organic thin films using an organic solvent to form a T-shaped metal on the third opening. It is something.

作  用 この構成により、断線のないT字型のゲートメタルを形
成でき、シートメタルのシート抵抗を大幅に低減できる
Function: With this configuration, a T-shaped gate metal without disconnection can be formed, and the sheet resistance of the sheet metal can be significantly reduced.

実施例 以下、本発明の一実施例について、図面(第1図)に基
づいて説明する。なお図中、従来例と同一符号は同一部
材を示す。
EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings (FIG. 1). In the drawings, the same reference numerals as in the conventional example indicate the same members.

図中、1〜5の部材者は前記従来例と同しであるため、
その説明は省略し、以下に化合物半導体装置のゲートメ
タル形成工程に!いて説明する。
In the figure, members 1 to 5 are the same as those in the conventional example, so
The explanation will be omitted and the following will explain the gate metal formation process of compound semiconductor devices! I will explain.

まず、第1図(a)において、ガリウムヒ素のn型活性
層1の上に密着性と耐熱性に優れたPMGIレジスト薄
膜2を回転塗布と250°C熱処理によって形成する。
First, in FIG. 1(a), a PMGI resist thin film 2 having excellent adhesion and heat resistance is formed on an n-type active layer 1 of gallium arsenide by spin coating and heat treatment at 250°C.

次に、前記PMG Tレジスト薄膜2の上にPMG I
レジスト薄膜2よりも耐熱性か悪いPMMAレジスト薄
膜3を回転塗布と 120°C熱処理によって形成する
。次に、前記PMMAレジスト薄膜3とPMG Iレジ
スト薄膜2に電子ビームを用いた選択照射によって同時
露光を行なう。
Next, PMG I is deposited on the PMG T resist thin film 2.
A PMMA resist thin film 3 having worse heat resistance than the resist thin film 2 is formed by spin coating and 120°C heat treatment. Next, the PMMA resist thin film 3 and the PMG I resist thin film 2 are simultaneously exposed by selective irradiation using an electron beam.

次に、前記PMMAレジスト薄膜3を現像して微細なゲ
ートパターンの開口部3aを形成す名。次に、前記PM
MAレジスト薄膜3の開口部3aをマスクとして前記P
MG Iレジスト薄膜2を現像して同一のゲートパター
ンの開口部2aを形成する。次に、第1図(b)におい
て、前記PMG Iレジスト薄膜2の開口部2aをマス
クとして前記ガリウムヒ素のn型活性層lをウェットエ
ツチングして逆メサ形状に開口部1aを形成する。次に
、第1図(C)において、200°Cの熱処理を施して
前記PMMAレジスト薄膜3のゲートパターンの開口部
3aのみにテーパーを付は拡大する。次に、第1図(d
)において、電子ビーム蒸着法を用いてPMMAレジス
ト薄膜3の上からゲートメタル4を全面蒸着する。次に
、第1図(e)において、前記ゲートメタル4の上に回
転塗布と120°C熱処理によって耐腐食性に優れた感
光性レジスト薄膜5を形成する。次に、選択露光と現像
によって前記PMMAレジスト薄膜3のゲートパターン
の開口部3aよりも大きいゲートの残しパターンを形成
する。次に、第1図(f)において、前記感光性レジス
ト薄膜5のゲート残しパターンを用いて前記ゲートメタ
ル4をドライエツチングして前記感光性レジスト薄膜5
と同一の形状を形成する。最後に、第1図(g)におい
て、前記感光性レジスト薄膜5とPMMAレジスト薄膜
3およびPMCIレジスト薄膜2をすへて有機溶剤に溶
解させて除去し、ガリウムヒ素のn型活性層1の逆メサ
形状の開口部1aにT字型のゲートメタル4を形成する
Next, the PMMA resist thin film 3 is developed to form a fine gate pattern opening 3a. Next, the PM
Using the opening 3a of the MA resist thin film 3 as a mask, the P
The MGI resist thin film 2 is developed to form an opening 2a having the same gate pattern. Next, in FIG. 1(b), using the opening 2a of the PMG I resist thin film 2 as a mask, the n-type active layer 1 of gallium arsenide is wet-etched to form an opening 1a in the shape of an inverted mesa. Next, in FIG. 1(C), heat treatment is performed at 200° C. so that only the opening 3a of the gate pattern of the PMMA resist thin film 3 is tapered or enlarged. Next, Figure 1 (d
), a gate metal 4 is deposited over the entire surface of the PMMA resist thin film 3 using an electron beam evaporation method. Next, in FIG. 1(e), a photosensitive resist thin film 5 having excellent corrosion resistance is formed on the gate metal 4 by spin coating and heat treatment at 120°C. Next, a remaining gate pattern larger than the opening 3a of the gate pattern of the PMMA resist thin film 3 is formed by selective exposure and development. Next, in FIG. 1(f), the gate metal 4 is dry-etched using the gate leaving pattern of the photosensitive resist thin film 5, and the photosensitive resist thin film 5 is etched by dry etching.
form the same shape as. Finally, in FIG. 1(g), the photosensitive resist thin film 5, PMMA resist thin film 3, and PMCI resist thin film 2 are completely dissolved in an organic solvent and removed, and the n-type active layer 1 of gallium arsenide is inverted. A T-shaped gate metal 4 is formed in the mesa-shaped opening 1a.

以上のように本実施例によれば、第1図(C)に示すよ
うにガリウムヒ素のn型活性層1を逆メサ形状に形成し
た後、200°Cの熱処理を施すことによってPMMA
レジスト薄膜3のゲートパターンにテーパーか付きゲー
トパターンか拡がることによって、第1図(d)に示す
ように全面蒸着したゲートメタル4がゲートパターン部
分て断線することなくゲートパターンの奥深くまでつな
がっていく。このようにして断線を防止したことによっ
て、第1図(g)に示すようにすべてのレジストを有機
溶剤で除去した後、ガリウムヒ素のn型活性層1の逆メ
サ形状の開口部1aにシート抵抗を低減できるT字型の
ゲートメタル4を形成てきる。
As described above, according to this embodiment, after the n-type active layer 1 of gallium arsenide is formed into an inverted mesa shape as shown in FIG.
By tapering the gate pattern of the resist thin film 3 and expanding the gate pattern, the gate metal 4 deposited on the entire surface is connected deep into the gate pattern without disconnection at the gate pattern portion, as shown in FIG. 1(d). . By preventing wire breakage in this way, after removing all the resist with an organic solvent as shown in FIG. A T-shaped gate metal 4 that can reduce resistance is formed.

なお、実施例では、ガリウムヒ素のn型活性層lを用い
たが、活性層はガリウムヒ素に限定されるものではなく
、半導体であれば何でもよい。例えばガリウムヒ素/ア
ルミニウムガリウムヒ素などのヘテロ接合を用いたHE
MTなどが考えられる。また、活性層を逆メサ形状に形
成した後に熱処理を施してPMMAレジスト薄膜3にテ
ーパーを付けたか、先に熱処理を施してPMMAレジス
ト薄膜3にテーパーを付け、その後活性層を逆メサ形状
に形成してもよい。
In the embodiment, an n-type active layer l of gallium arsenide was used, but the active layer is not limited to gallium arsenide, and may be any semiconductor. HE using heterojunctions such as gallium arsenide/aluminum gallium arsenide
MT etc. can be considered. Alternatively, after forming the active layer in an inverted mesa shape, heat treatment is performed to make the PMMA resist thin film 3 taper, or heat treatment is first performed to make the PMMA resist thin film 3 taper, and then the active layer is formed in an inverted mesa shape. You may.

発明の効果 以上のように本発明によれば、熱処理を施して第1の有
機薄膜、第2の有機薄膜のゲートパターンの中て耐熱性
の悪い上側の第2の有機薄膜のゲートパターンのみにテ
ーパーを付けてゲートパターンを拡げることによって断
線のないT字型のゲートメタルを形成でき、このT字型
形状によってゲートメタルのンート抵抗を大幅に低減で
き、その実用的効果は大なるものがある。
Effects of the Invention As described above, according to the present invention, heat treatment is applied to only the gate pattern of the upper second organic thin film, which has poor heat resistance, among the gate patterns of the first organic thin film and the second organic thin film. By tapering and widening the gate pattern, it is possible to form a T-shaped gate metal with no disconnection, and this T-shaped shape can significantly reduce the gate resistance of the gate metal, which has great practical effects. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(g)は本発明の一実施例における化合
物半導体装置のゲートメタル形成工程図、第2図(a)
〜(f)は従来の化合物半導体装置のゲートメタル形成
工程図である。 1・・・ガリウムヒ素のn型活性層、1a・・・開口部
、2・・・PMG Iレジスト薄膜、2a・・・開口部
、3・・・PMMAレジスト薄膜、3a・・・開口部、
4・・・ゲートメタル、5・・・感光性レジスト薄膜。
FIGS. 1(a) to (g) are process diagrams for forming gate metal of a compound semiconductor device according to an embodiment of the present invention, and FIG. 2(a) is
-(f) are process diagrams for forming gate metal of a conventional compound semiconductor device. DESCRIPTION OF SYMBOLS 1... N-type active layer of gallium arsenide, 1a... Opening part, 2... PMG I resist thin film, 2a... Opening part, 3... PMMA resist thin film, 3a... Opening part,
4...Gate metal, 5...Photosensitive resist thin film.

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板の上に電子ビームあるいは近紫外線に感
光する第1の有機薄膜を形成する工程と、前記第1の有
機薄膜の上に電子ビームあるいは近紫外線に感光しかつ
前記第1の有機薄膜より耐熱性か悪く熱処理によって形
状変化を起こす第2の有機薄膜を形成する工程と、前記
第2の有機薄膜および前記第1の有機薄膜に電子ビーム
の選択照射あるいは近紫外線の選択露光を行なう工程と
、現像によって前記第2の有機薄膜に第1の開口部を形
成する工程と、前記第1の開口部をマスクとして現像に
よって前記第1の有機薄膜に第2の開口部を形成する工
程と、前記第2の開口部をマスクとしてエッチングによ
り前記半導体基板に第3の開口部を形成する工程と、熱
処理によって前記第1の開口部に傾斜を付けて前記第1
の開口部を拡げる工程と、前記第2の有機薄膜の上から
メタルを、全面蒸着する工程と、前記メタルの上に感光
性を有しかつ耐腐食性に優れた第3の有機薄膜を形成す
る工程と、前記第3の有機薄膜に選択露光と現像を行な
って前記第1の開口部より大きな残しパターンを形成す
る工程と、前記第3の有機薄膜の残しパターンをマスク
として前記メタルをエッチングする工程と、前記第1、
第2、第3の有機薄膜を有機溶剤を用いてすべて除去し
て前記第3の開口部上にT字型のメタルを形成する工程
とからなる半導体装置の製造方法。
1. forming a first organic thin film sensitive to electron beams or near ultraviolet rays on a semiconductor substrate; and forming a first organic thin film sensitive to electron beams or near ultraviolet rays on the first organic thin film; a step of forming a second organic thin film that is less heat resistant and undergoes shape change upon heat treatment, and a step of selectively irradiating the second organic thin film and the first organic thin film with an electron beam or selectively exposing near ultraviolet rays. a step of forming a first opening in the second organic thin film by development; and a step of forming a second opening in the first organic thin film by development using the first opening as a mask. forming a third opening in the semiconductor substrate by etching using the second opening as a mask;
a step of enlarging the opening of the second organic thin film, a step of evaporating a metal over the entire surface of the second organic thin film, and forming a third organic thin film having photosensitivity and excellent corrosion resistance on the metal. a step of selectively exposing and developing the third organic thin film to form a remaining pattern larger than the first opening; and etching the metal using the remaining pattern of the third organic thin film as a mask. the first step;
A method for manufacturing a semiconductor device comprising the step of removing all the second and third organic thin films using an organic solvent and forming a T-shaped metal over the third opening.
JP10675390A 1990-04-23 1990-04-23 Manufacture of semiconductor device Pending JPH045834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10675390A JPH045834A (en) 1990-04-23 1990-04-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10675390A JPH045834A (en) 1990-04-23 1990-04-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH045834A true JPH045834A (en) 1992-01-09

Family

ID=14441674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10675390A Pending JPH045834A (en) 1990-04-23 1990-04-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH045834A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855863A (en) * 1994-08-15 1996-02-27 Nec Corp Manufacture of field-effect semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855863A (en) * 1994-08-15 1996-02-27 Nec Corp Manufacture of field-effect semiconductor device

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