KR100203296B1 - Manufacturing method of the mos transistor - Google Patents
Manufacturing method of the mos transistor Download PDFInfo
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- KR100203296B1 KR100203296B1 KR1019940036213A KR19940036213A KR100203296B1 KR 100203296 B1 KR100203296 B1 KR 100203296B1 KR 1019940036213 A KR1019940036213 A KR 1019940036213A KR 19940036213 A KR19940036213 A KR 19940036213A KR 100203296 B1 KR100203296 B1 KR 100203296B1
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- Prior art keywords
- gate
- gate electrode
- mos transistor
- oxide film
- manufacturing
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 210000003323 beak Anatomy 0.000 abstract description 7
- 238000010405 reoxidation reaction Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 230000002411 adverse Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000012544 monitoring process Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
고집적 반도체 소자 제조방법.Highly integrated semiconductor device manufacturing method.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
T자형 게이트 전극을 가진 모스(MOS) 트랜지스터 제조시, 게이트 산화막(2)의 재산화 공정을 이용하면 게이트 전극(5)의 하부 모서리에 게이트 버즈 비크(GATE BIRD'S BEAK)가 형성되게 되는데, 이와 같은 게이트 버즈 비크를 이용하는 경우에는 공정 및 모니터링의 한계로 인해 소자의 프로파일의 확인이 불확실하게 이루어질 뿐만 아니라, 게이트 버즈 비크를 정확하게 조절하지 못하게 되면 게이트의 모양도 T자형이 아닌 역사다리꼴이 되기 때문에 오리려 소자의 특성이 열화되는 등의 역효과가 발생할 수도 있다는 문제점을 해결하고자 함.When manufacturing a MOS transistor having a T-shaped gate electrode, using a reoxidation process of the gate oxide film 2, a gate buzz beak is formed in the lower corner of the gate electrode 5. When using a gate buzz beak, not only is the profile of the device uncertain due to process and monitoring limitations, but also the gate shape becomes an inverted trapezoid rather than a T-shape if the gate buzz beak cannot be adjusted accurately. It is intended to solve the problem of adverse effects such as deterioration of device characteristics.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
종래의 재산화 공정에 의한 게이트 버즈 비크를 이용하지 않고 게이트 산화막을 이중으로 형성하는 공정을 이용하여 T자형 게이트 전극을 직접 패터닝하여 형성하므로서 양호한 특성을 가진 T-게이트 MOS 트랜지스터를 제고하고자 함.In order to improve the T-gate MOS transistor having good characteristics by directly patterning the T-shaped gate electrode using a process of forming a gate oxide film in a double manner without using the gate buzz beak according to the conventional reoxidation process.
4. 발명의 중용한 용도4. Significant use of the invention
고집적 반도체 소자, 특히 MOS 트랜지스터제조에 이용됨.Used in the manufacture of highly integrated semiconductor devices, especially MOS transistors.
Description
제1a도 내지 제1e도는 종래 기술에 따라 MOS 트랜지스터의 T자형 게이트 전극을 형성하는 방법의 공정도.1A-1E are process diagrams of a method of forming a T-shaped gate electrode of a MOS transistor according to the prior art.
제2a도 내지 제2g도는 본 발명에 따라 MOS 트랜지스터의 T자형 게이트 전극을 형성하는 방법의 공정도.2A-2G are process diagrams of a method of forming a T-shaped gate electrode of a MOS transistor in accordance with the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 제 1 산화막11 semiconductor substrate 12 first oxide film
13, 16 : 포토레지스트 14 : 제 2 산화막13, 16: photoresist 14: second oxide film
15 : 폴리실리콘 17 : 게이트 전극15 polysilicon 17 gate electrode
본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서, 특히 T자형 게이트 전극을 가진 MOS 트랜지스터를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a MOS transistor having a T-shaped gate electrode.
트랜지스터의 신뢰성 및 특성 개선을 위해 여러 가지 구조의 MOS 트랜지스터가 개발되었으며, 그중 하나가 T자형 게이트 전극을 가진 MOS 트랜지스터로서, 오프 전류 감소 및 핫 캐리어 감소로 인해 소자의 신뢰성이 향상되고, 소비 전력이 낮고, 속도를 증가시킬 수 있다는 여러 가지 장점이 있는 것으로 알려져 있지만, 공정상의 어려움으로 인하여 실제적으로는 거의 적용되지 못하고 있는 실정이다.In order to improve the reliability and characteristics of transistors, various structures of MOS transistors have been developed, and one of them is a MOS transistor having a T-shaped gate electrode, which increases the reliability of the device due to reduced off current and reduced hot carrier, Although it is known that there are various advantages of low speed and increase, it is practically hardly applied due to process difficulties.
종래 기술에 의한 T자형 게이트 전극을 가진 MOS 트랜지스터 제조 공정을 제1a도 내지 제1e도를 참조하여 살펴보면 다음과 같다.A process of fabricating a MOS transistor having a T-shaped gate electrode according to the prior art will now be described with reference to FIGS. 1A through 1E.
먼저, 제1a도에 도시된 바와같이, 반도체 기판(1)상에 게이트 산화막(2)을 증착한 다음, 제1b도에 도시된 바와같이, 폴리실리콘(3)을 증착한다. 다음에 제1c도에 도시된 바와같이, 전체 구조상부에 포토레지스트를 도포한 다음 포토마스크를 이용하여 게이트 전극 형성을 위한 마스크 패턴(4)을 형성하고, 제1d도에 도시된 바와같이 상기 마스크 패턴을 이용하여 상기 폴리실리리콘층(3)의 식각 공정을 수행한다. 다음에 제1e도에 도시된 바와같이, 게이트 산화막(2)의 재산화 공정을 수행하면 게이트 전극(5)의 하부 모서리에 게이트 비즈비크(GATE BIRD'S BEAK)가 형성되게 된다. 그러나, 이와같은 게이트 버즈 버크를 이용하는 경우에는 공정 및 모니터링 한계로 인해 소자의 프로파일의 확인이 불확실하게 이루어질 뿐만 아니라, 게이트 버즈 비크를 정확하게 조절하기가 어려워 게이트의 모양도 T자형이 아닌 역사다리꼴이 되기 때문에 오히려 소자의 특성이 열화되는 등의 역효과가 발생할 수도 있었다.First, as shown in FIG. 1A, a gate oxide film 2 is deposited on the semiconductor substrate 1, and then polysilicon 3 is deposited as shown in FIG. 1B. Next, as shown in FIG. 1C, a photoresist is applied over the entire structure, and then a mask pattern 4 for forming a gate electrode is formed by using a photomask, and the mask as shown in FIG. 1D. An etching process of the polysilicon layer 3 is performed using a pattern. Next, as shown in FIG. 1E, when the reoxidation process of the gate oxide film 2 is performed, a gate bid'S BEAK is formed at the lower edge of the gate electrode 5. However, in the case of using such gate buzz bucks, not only is the profile of the device uncertain due to process and monitoring limitations, but also it is difficult to accurately control the gate buzz beak so that the shape of the gate becomes an inverted trapezoid rather than a T-shape. Therefore, adverse effects such as deterioration of device characteristics could occur.
따라서 전술한 문제점을 해결하기 위해 안출된 본 발명은 종래의 재산화 공정에 의한 게이트 버즈 비크를 이용하지 않고 게이트 산화막의 이중 형성 공정을 이용하여 T자형 게이트 전극을 직접 패터닝하여 형성하므로서 양호한 특성을 가진 T-게이트 MOS 트랜지스터를 제조하는 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention devised to solve the above-described problem has a good characteristic by forming the T-shaped gate electrode directly by using a double-forming process of the gate oxide film without using the gate buzz beak by the conventional reoxidation process It is an object to provide a method of manufacturing a T-gate MOS transistor.
본 발명에 따른 MOS 트랜지스터 제조 방법은, 반도체 기판상에 제 1 산화막을 증착하고, 그 위에 포토레지스트를 도포하는 단계와, 게이트 전극이 형성될 부위가 오픈되도록 마스크 패턴을 형성하는 단계와, 상기 마스크 패턴을 이용하여 상기 제 1 산화막의 식각 공정을 실시하고 잔류 포토레지스트를 제거하는 단계와, 전체 구조 상부에 제 2 산화막을 증착하고, 그 위에 폴리실리콘을 증착하는 단계와, 전체 구조 상부에 포토레지스트를 도포한 후, 게이트 전극 형성을 위한 포토레지스트 마스크 패턴을 형성하고, 상기 폴리실리콘층과 상기 제 2 및 제 1 산화막을 차례로 식각하는 단계 및, 잔류 포토레지스트를 제거하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a MOS transistor according to the present invention includes depositing a first oxide film on a semiconductor substrate, applying a photoresist thereon, forming a mask pattern to open a portion where a gate electrode is to be formed, and forming the mask. Etching the first oxide film using a pattern to remove residual photoresist; depositing a second oxide film over the entire structure; and depositing polysilicon thereon; and photoresist over the entire structure Forming a photoresist mask pattern for forming a gate electrode, sequentially etching the polysilicon layer and the second and first oxide layers, and removing residual photoresist; do.
이제 본 MOS 트랜지스터 제조 방법의 한 실시예에 대하여 첨부 도면을 참조하여 보다 상세하게 설명하게 된다. 먼저, 제2a도에 도시된 바와 같이, 반도체 기판(11)상에 제 1 산화막(12)을 증착하고, 그 위에 포토레지스트(13)를 도포한다. 다음에 제2b도에 도시된 바와 같이, 게이트 전극이 형성될 부위가 오픈되도록 마스크 패턴(13)을 형성하고, 제2c도에 도시된 바와 같이, 상기 마스크 패턴을 이용하여 식각 공정을 실시하고 잔류 포토레지스트를 제거한다. 다음에는, 제2d도에 도시된 바와 같이, 제 2 산화막(14)을 100Å 내지 300Å 정도 증착하고, 그 위에 게이트 전극 형성을 위한 폴릴실리콘(15)을 증착하면 제2e도에 도시된 바와 같은 모양으로 형성된다. 다음에 제2f도에 도시된 바와 같이, 포토레지스트를 이용하여 게이트 전극 형성을 위한 포토레지스트 마스크 패턴(16)을 형성하고, 상기 폴리실리콘층(15)과 산화막(14,12)을 차례로 식각하면, 제2g도에 도시된 바와 같은 T자형 게이트 전극(17)이 형성되게 된다.One embodiment of the present MOS transistor manufacturing method will now be described in more detail with reference to the accompanying drawings. First, as shown in FIG. 2A, the first oxide film 12 is deposited on the semiconductor substrate 11, and the photoresist 13 is applied thereon. Next, as shown in FIG. 2B, a mask pattern 13 is formed to open a portion where the gate electrode is to be formed, and as shown in FIG. 2C, an etching process is performed using the mask pattern and the residue is left. Remove the photoresist. Next, as shown in FIG. 2d, when the second oxide film 14 is deposited to about 100 to 300 mW, and the polysilicon 15 for forming the gate electrode is deposited thereon, the shape as shown in FIG. 2e is shown. Is formed. Next, as shown in FIG. 2F, when the photoresist mask pattern 16 for forming the gate electrode is formed using the photoresist, the polysilicon layer 15 and the oxide layers 14 and 12 are sequentially etched. The T-shaped gate electrode 17 as shown in FIG. 2G is formed.
반도체 소자 제조시, 전술한 바와같은 본 발명에 따라 모스(MOS) 트랜지스터를 제조하므로서, 오프 전류 감소 및 핫 캐리어 효과의 감소로 인해 소자의 신뢰성이 향상되고, 소비 전력이 낮고, 속도를 증가시킬 수 있는 T-게이트 MOS 트랜지스터를 간단한 공정으로 제조할 수 있다는 장점이 있다.In manufacturing a semiconductor device, by manufacturing the MOS transistor according to the present invention as described above, the reliability of the device can be improved, the power consumption is low, and the speed can be increased due to the reduction of the off current and the reduction of the hot carrier effect. The advantage is that T-gate MOS transistors can be manufactured in a simple process.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940036213A KR100203296B1 (en) | 1994-12-23 | 1994-12-23 | Manufacturing method of the mos transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940036213A KR100203296B1 (en) | 1994-12-23 | 1994-12-23 | Manufacturing method of the mos transistor |
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| Publication Number | Publication Date |
|---|---|
| KR960026756A KR960026756A (en) | 1996-07-22 |
| KR100203296B1 true KR100203296B1 (en) | 1999-06-15 |
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| KR1019940036213A KR100203296B1 (en) | 1994-12-23 | 1994-12-23 | Manufacturing method of the mos transistor |
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| KR (1) | KR100203296B1 (en) |
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1994
- 1994-12-23 KR KR1019940036213A patent/KR100203296B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR960026756A (en) | 1996-07-22 |
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