JP3165712B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate of a field effect GaAs transistor having a recess gate structure.

[0002]

2. Description of the Related Art Field effect type G having a recess gate structure
As a conventional example of an aAs transistor, HEMT (High E
Electron Mobility Transistor, a high electron mobility transistor), and the related art will be described with reference to the drawings.

FIG. 7 is a cross-sectional view of a HEMT device in a manufacturing process immediately after lift etching after recess etching (recess etching).
In FIG. 1, a buffer layer 2, a secondary electron supply layer 3, and cap layers 4d and 4s are formed on a GaAs substrate 1 by an epitaxial growth method. Cap layers 4d and 4
A drain electrode 6d and a source electrode 6s that are in ohmic contact with each other are formed at s. Gate metals 7 and 7 g are laminated on the resist film 5 including the opening 9.

Next, a first conventional example of the gate forming method, that is, a case where the side wall of the opening 9 of the resist has a vertical shape will be described below with reference to FIGS. FIG.
1A, a buffer layer 2, 2 on a GaAs substrate 1 is formed.
A substrate in which the next electron supply layer 3 and the cap layer 4 are stacked by an epitaxial growth method is prepared. Next, after applying the positive resist film 5, a fine line pattern for forming a gate is drawn on the resist film 5 by an electron beam exposure apparatus. Next, development is performed to obtain an opening 9 whose side wall is substantially perpendicular to the resist film 5. In FIG. 8B, the cap layer 4 and the secondary electron supply layer 3 are etched using the resist as a mask. This etching is called recess etching, and is usually performed by a drain electrode 6d and a source electrode 6s (FIG. 7).
2), a current is supplied, and the secondary electron supply layer 3 is etched while checking the current. Next, as shown in FIG. 9A, a gate metal 7 is formed on the resist film 5 including the opening 9.
And 7 g are deposited. The gate metal 7g may be called a gate electrode. Next, as shown in FIG. 9B, the gate metal 7 on the resist film 5 is removed by a lift-off method to form a gate electrode 7g.

As shown in FIGS. 8 and 9, when the side wall of the opening 9 has a vertical shape, a gate can be formed without increasing the bottom width of the gate electrode 7g. However, when the oblique component of the incident direction of the gate metal to be deposited becomes large due to the condition of the metal deposition apparatus, the metal may adhere to the side wall of the opening, and burrs 8 may be generated on the gate electrode 7g after lift-off. Also, in the recess etching, even if the side etching is performed, a side etching distance equivalent to the depth direction can be obtained because of the wet etching process. Therefore, recess etching end 12
And a sufficient distance from the gate metal end 11 cannot be obtained, the drain breakdown voltage does not increase in the HEMT characteristics, and other DC characteristics tend to deteriorate.

Next, a second conventional example of a gate forming method which solves the above problem will be described with reference to FIGS. In this method, the resist film has a two-layer structure,
The side wall of the opening is formed in an overhang shape to facilitate the lift-off of the metal and to obtain a sufficient space between the recess etching end and the gate metal end.

In FIG. 10 (a), as in the first method, a laminated substrate having a buffer layer 2, a secondary electron supply layer 3 and a cap layer 4 formed on a GaAs substrate 1 is prepared, and a lower resist film 15 is formed. , And an upper resist film 16 is further applied thereon. Next, by an electron beam exposure device,
A fine line pattern for a gate is drawn on the upper resist film 16 and then developed to form an opening 10a. Next, as shown in FIG. 10B, the lower resist 15 is exposed and developed to form an overhang-shaped opening 10. Next, in FIG.
After the recess etching is performed using the layer resist film as a mask, as shown in FIG. 11B, gate metals 7 and 7g are laminated on the entire surface. Next, as shown in FIG. 12, the gate metal 7 on the resist is removed by a lift-off method,
A gate electrode 7g is obtained. In this case, the width of the bottom surface of the gate metal 7g is substantially equal to the width of the opening 10a of the upper resist film 16. Therefore, a sufficient space can be provided between the recess etching end and the end of the gate metal 7g, and the occurrence of burrs as in the first conventional example is reduced. Thereby, the drain withstand voltage can be increased. However 2
Due to the layered resist structure, steps such as resist application, drawing, and development are increased, so that the formation time of the resist pattern is longer than in the single-layered resist step.

The problems caused by the shape of the opening of the resist pattern have been described above in the first and second conventional examples. At present, however, the developing method also has the following problems. That is, regarding formation of a resist pattern, 1
There is a problem in that the size of the opening is increased if the formation is completed only by performing the development process twice. This is because when the resist is exposed by the electron beam, the electron beam is affected by the foreground scatter when entering the resist and the backscatter when the resist is transmitted through the resist film and collides with the GaAs substrate surface. The scattered electrons are generated, so that the resist is exposed over a predetermined scanning width of the electron beam, that is, a width larger than the design dimension d _{0 of the} opening. FIG. 5 is a schematic sectional view of the resist film 43 for explaining this state. In the figure, a positive resist film 43 laminated on a GaAs substrate 40 is exposed by an electron beam 41. Reference numeral 44 denotes a resist area exposed by an electron beam spread by a forescatter or the like, and reference numeral 45 denotes a resist area exposed by an electron beam spread by a backscatter or the like. In the case of a single development process, the width of the opening 46 is increased as shown in FIG. 6A in order to develop all of the exposed resist in the conventional method.

[0009]

As described above, an electric field of an HEMT or the like having a recess gate structure (a structure in which a portion immediately below a gate electrode of an operation layer of an FET is removed by etching to obtain a desired operation layer thickness). In the formation of the gate of the effect transistor, as in the first conventional example,
When the side wall of the opening of the resist film has a vertical shape, it is necessary to obtain a sufficient width of the bottom surface of the opening after the recess etching, that is, a sufficient distance between the recess etching end and the gate metal end laminated on the bottom of the opening. However, there is a problem that the drain withstand voltage does not increase and burrs occur in the gate metal after lift-off. Further, the problem of the first conventional example can be improved to some extent by forming the resist film into a two-layer structure as in the second conventional example, but the number of steps becomes longer and there is a problem in dimensional control.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to form a resist film for forming a recess gate into a single-layer structure, to stably control a recess etching dimension at the bottom of an opening, A method of manufacturing a semiconductor device, in which a distance between an etched end and a gate metal end laminated on the bottom of an opening can be made sufficiently large, whereby lift-off can be easily performed and characteristics such as drain withstand voltage of an element can be improved. It is to provide.

[0011]

According to the present invention, there is provided a method of manufacturing a field effect transistor having a recess gate structure, comprising: (a) applying a novolak-based positive resist on a semiconductor substrate; Process and
(B) a step of drawing a gate pattern on the positive resist film by an electron beam exposure apparatus; and (c) a first resist treatment comprising development, washing and drying on the positive resist film on which the gate pattern has been drawn. After performing the steps, a resist processing step including development, washing, and drying is further performed in one step.
Forming an opening in the positive resist film, the angle of the side wall being reverse tapered and reaching the substrate surface, and (d) recess etching using the positive resist film as a mask, Stacking a gate metal and removing the metal on the resist by lift-off.

When a gate pattern (usually a linear pattern, the line width of which is called a gate electrode width or a gate metal width) is drawn on a novolak-based positive resist by an electron beam, the resist area exposed by the electron beam is scattered. As a result, the line width becomes wider than the design dimension d ₀ (see FIG. 5). When such a photosensitive resist is subjected to the development processing described in the above item (c), that is, step development, an opening having a side wall having an inversely tapered shape can be formed.
That is, the width of the bottom surface of the opening is larger than the width of the top surface of the opening. When recess etching is performed using this resist as a mask, the width of the bottom surface of the opening is further increased by the side etch. When a gate metal is laminated on a resist having such an opening, the width of the gate metal laminated on the bottom of the opening is substantially equal to the width of the top surface of the opening. Thereby, the distance between the recess etching end on the bottom of the opening and the end of the gate metal laminated on the bottom of the opening can be stably set to a sufficiently large distance.

According to a second aspect of the present invention, the thickness of the resist is made larger than the thickness of the gate metal so that the gate metal on the resist can be reliably lifted off.
The development time of the second resist process is 30 seconds to 60 seconds.
This is a manufacturing method that can ensure that the angle of the side wall is inversely tapered in seconds.

According to a third aspect of the present invention, in the manufacturing method of the first aspect, after the first resist processing step, the developing time in the processing step performed once or repeatedly is set to 30 seconds or less. Is required to control the desired reverse tapered shape.

[0015]

FIG. 1 is a sectional view of a HEMT device formed by applying the manufacturing method of the present invention, immediately after lift-off of a gate metal after recess etching. A novolak-based positive resist 25 is applied on a laminated substrate composed of a GaAs substrate 1 or the like. An opening 26 having a side wall 27 having an inversely tapered angle is formed in the resist 25.
In FIG. 1, the same reference numerals as those in FIG. 7 represent the same or corresponding parts, and thus the description thereof will be omitted.

Next, a method of manufacturing the HEMT device will be described with reference to FIGS. As shown in FIG. 2A, a buffer layer 2, a secondary electron supply layer 3, and a cap layer 4 are stacked on a GaAs substrate 1 by an epitaxial growth method. A novolak-based positive resist film 25 is applied thereon by spin coating. As a resist, a novolak-based positive resist MP-2400 (Shipley) was used. Further, the thickness of the resist film needs to be larger than the thickness of a gate metal described later. Generally 5
It is set to about 00 nm to 1000 nm. Next, a fine gate pattern is drawn on the positive resist film 25 by an electron beam exposure apparatus.

Next, the positive resist film on which the gate pattern has been drawn is subjected to a first resist processing step including development, washing and drying. MP2401 was used as a developer. The temperature of the developer is preferably 23 ° C. to 25 ° C., and the developing time is 30 seconds to 60 seconds, which is determined by trial. FIG. 2A is a cross-sectional view after the first resist process is performed, in which a concave portion 26a is formed.

Next, using the same developer again, development is performed for 30 seconds, washing with water and drying are performed to obtain an opening 26b reaching the substrate surface as shown in FIG. 2 (b). One more time,
Using the same developing solution, development is performed for 30 seconds, and washing and drying are performed to obtain an opening 26c having an inverted tapered side wall 27 as shown in FIG. The angle of the side wall of the opening 26c is
It is desirable that the angle be 70 degrees to 80 degrees. In this embodiment, the total development time is 90 seconds in three resist processing steps, but generally the total development time is 90 to 12 seconds.
The time is about 0 second, and development is performed, for example, four times depending on the profile of the opening side wall.

After completion of the formation of the resist pattern, FIG.
As shown in (b), the cap layer 4 and the secondary electron supply layer 3 of the substrate are recess-etched with a phosphoric acid-based etchant using the resist film 25 as a mask. Next, FIG.
As shown in FIG. 3A, Al or Au gate metals 7 and 7 g are deposited on the entire surface of the substrate on which the resist film 25 is laminated. Next, the unnecessary gate metal 7 on the resist film 25 is removed by a lift-off method, and a gate electrode film 7g is obtained as shown in FIG.

In the above-described manufacturing method, the problem that the resist pattern formation takes too much time in the second conventional example, in which the resist film for forming the gate has a single-layer structure and the two-layer resist structure, is solved. You.

In the prior art, a resist pattern is formed by a single development, whereas in the manufacturing method described above, the resist pattern is formed by a step development. The difference between the two methods will be described with reference to FIGS. In FIG. 5, a novolak-based positive resist film 4 applied on a GaAs substrate 40 is formed.
3, when drawing a gate pattern by the electron beam 41, the resist region sensitized by electron beam, the line width increases from the design size d _0. In other words, the photosensitive region is extended to the outer periphery only by the region 44 exposed by the electron beam spread by the forescatter or the like and the region 45 exposed by the electron beam spread by the backscatter or the like.

FIG. 6A shows a case where the substrate of FIG. 5 is subjected to the conventional method, that is, once continuous development for 120 seconds, and FIG.
When the resist process of development for 30 seconds, washing with water, and drying is repeated twice after developing for 0 seconds, washing with water, and drying, the shape of the opening in each case is shown. In the case of developing number once, photosensitive resist as seen in FIG. 6 (a) all developed, thus opening size d ₁ of the opening 46 is larger than the design dimension d _0. On the other hand, in the case of the step development, as shown in FIG. 6B, the opening dimension has a value of d ₀ which is almost close to the design dimension. In a resist treatment including development, washing, and drying, a hardly soluble resist layer is formed in the washing and drying process of the developed resist and remains on the resist surface. The hardly soluble layer slows down the subsequent resist processing speed.
In the step development, each time the resist process is repeated, the hardly soluble layer of the resist is laminated, a hardly soluble layer 47 is formed as shown in FIG. 6B, the increase in the opening size is prevented, and the side wall of the reverse taper is removed. Can be formed.

The width w of the top of the opening 26 shown in FIG.
_{On the} other hand, the width w ₂ of the bottom of the opening 26 satisfies w ₂ > w ₁ because the side wall has an inverse taper. The reverse taper shape is
It is stable because it is sufficiently controlled by step development. Further, the width w _{3 of the} recessed portion is formed through the recess etching.
Can be controlled. The width w ₄ of the gate metal 7g shown in FIG. 4 (a), since substantially equal to the width w ₁ of the top of the opening, the distance between the recess etching end and gate metal edge as a result (w ₃ -w ₄₎ / 2 can be made sufficiently large, and the DC characteristics of the element such as the drain withstand voltage can be improved. In addition, because of the inverse tapered shape, lift-off can be easily performed.

In the above embodiment, the HEMT device has been described. However, the present invention relates to an MMT having a recess gate structure.
The present invention can be applied to a method for manufacturing other field effect transistors such as an ESFET.

[0025]

As described above, according to the present invention, the resist film for forming the recess gate has a single layer structure, the side wall of the opening of the resist pattern has an inverted tapered structure, and the recess etching dimension of the bottom of the opening is reduced. Stable control became possible. As a result, the present invention can sufficiently increase the distance between the gate metal end laminated on the bottom surface of the opening and the recess etching end, facilitate lift-off, and improve characteristics such as drain withstand voltage of the element. A method for manufacturing the obtained semiconductor device could be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a HEMT device to which the present invention is applied, immediately before lift-off of a gate metal.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing step following that of FIG. 2 of the semiconductor device of the present invention;

FIG. 4 is a cross-sectional view showing a manufacturing step following that of FIG. 3 of the semiconductor device of the present invention;

FIG. 5 is a cross-sectional view for explaining a resist region exposed by an electron beam.

6A is a cross-sectional view showing the shape of an opening when the photosensitive resist of FIG. 5 is subjected to conventional development and FIG. 6B is subjected to step development of the present invention.

FIG. 7 is a cross-sectional view of a conventional HEMT device immediately before lift-off of a gate metal.

FIG. 8 is a cross-sectional view showing a manufacturing process of the first conventional example.

FIG. 9 is a cross-sectional view showing a manufacturing step subsequent to FIG. 8 of the first conventional example.

FIG. 10 is a sectional view showing a manufacturing process of a second conventional example.

FIG. 11 is a cross-sectional view showing a manufacturing step following that of FIG. 10 of the second conventional example.

FIG. 12 is a cross-sectional view showing a manufacturing step following FIG. 11 of the second conventional example.

[Description of Signs] 1 GaAs substrate 2 buffer layer 3 secondary electron supply layer 4 cap layer 5 resist film 7 gate metal 7g gate metal (gate electrode) 15 resist film 25 novolak-based positive resist film 26 opening

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-233530 (JP, A) JP-A-1-165126 (JP, A) JP-A-2-214126 (JP, A) JP-A-2- 303117 (JP, A) JP-A-2-208934 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/027 G03B 27/32 G03F 7/16 G03F 7/20 521

Claims (3)

(57) [Claims] 1. A method of manufacturing a field-effect transistor having a recess gate structure, comprising: (a) applying a novolak-based positive resist on a semiconductor substrate; and (b) applying a gate pattern to the positive resist film by an electron beam. (C) performing a first resist processing step including development, washing and drying on the positive resist film on which the gate pattern has been drawn, and further developing, washing and drying. Repeating the resist processing step once or a plurality of times to form an opening in the positive resist film having an inversely tapered side wall and reaching the substrate surface; and (d) using the positive resist film as a mask. Stacking the gate metal after the recess etching, and removing the metal on the resist by lift-off. The method of manufacturing a semiconductor device according to claim. 2. The semiconductor device according to claim 1, wherein the novolak-based positive resist is formed with a thickness exceeding the thickness of the gate metal, and the developing time in the first resist processing step is 30 seconds to 60 seconds. Production method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a development time of said resist processing step repeated once or plural times does not exceed 30 seconds.