JPH0529213A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate a lift-off method, and to improve the characteristics such as drain breakdown strength and the like by a method wherein a gate pattern is drawn by projecting an electron beam on a novolac positive resist, and the side wall of the aperture part of the resist pattern is formed into an inverted taper-shaped structure. CONSTITUTION:A buffer layer 2, a secondary electron feeding layer 3, and a cap layer 4 are laminated on a substrate 1, and a novolac positive type resist film 25 is provided thereon. The thickness of the resist film should be thicker than a gate metal film. Then, a microscopic gate pattern is drawn on the positive type resist film 25 by an electron beam exposing device. A resist treatment, consisting of developing, washing and drying operations, is conducted several times on the drawn positive type resist film 25, and an aperture part 26, having the inverted taper-shaped side wall 27, is obtained. A recess etching treatment is conducted using the resist film 25 as a mask, then, gate metals 7 and 7g are laminated, the unnecessitated gate metal 7 is removed by a lift-off method, and a gate electrode 7 is formed. As a result, a lift-off treatment can be facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate of a field effect GaAs transistor having a recess gate structure.

[0002].

2. Description of the Related Art Field effect type G having a recess gate structure
As a conventional example of the aAs transistor, HEMT (High E
lectron Mobility Transistor, a high electron mobility transistor), and the related art will be described with reference to the drawings.

FIG. 7 is a cross-sectional view of a HEMT device during a manufacturing process, after recess etching (recess etching) and immediately before lift-off.
In the figure, a buffer layer 2, a secondary electron supply layer 3 and cap layers 4d and 4s are formed on a GaAs substrate 1 by an epitaxial growth method. Cap layers 4d and 4
At s, a drain electrode 6d and a source electrode 6s, which are in ohmic contact with each other, are formed. Gate metals 7 and 7g are laminated on the resist film 5 including the opening 9.

Next, a first conventional example of the gate forming method, that is, a case where the side wall of the opening 9 of the resist has a vertical shape will be described below with reference to FIGS. Figure 8
In (a), the buffer layers 2, 2 are formed on the GaAs substrate 1.
A substrate in which the secondary electron supply layer 3 and the cap layer 4 are laminated by an epitaxial growth method is prepared. Next, after applying the positive resist film 5, a fine line pattern for forming a gate is drawn on the resist film 5 by an electron beam exposure apparatus. Next, development is performed to obtain an opening 9 whose side wall is substantially vertical to the resist film 5. In FIG. 8B, the cap layer 4 and the secondary electron supply layer 3 are etched using the resist as a mask. This etching is called recess etching, and is usually a drain electrode 6d and a source electrode 6s (see FIG. 7).
(Refer to FIG. 3), an electric current is passed between them, and the secondary electron supply layer 3 is etched while checking the electric current. Next, as shown in FIG. 9A, the gate metal 7 is formed on the resist film 5 including the opening 9.
And 7 g are deposited. The gate metal 7g may also be called a gate electrode. Next, as shown in FIG. 9B, the gate metal 7 on the resist film 5 is removed by a lift-off method to form a gate electrode 7g.

As shown in FIGS. 8 and 9, when the side wall of the opening 9 has a vertical shape, it is possible to form a gate in which the bottom width of the gate electrode 7g does not become large. However, when the oblique component in the incident direction of the gate metal to be vapor-deposited becomes large due to the condition of the metal vapor deposition apparatus, the metal adheres to the side wall of the opening and may cause burrs 8 on the gate electrode 7g after lift-off. Further, in the recess etching, even if the side etching is performed, the side etching distance equivalent to the depth direction can be obtained because of the wet etching process. Therefore, the recess etching end 12
Then, a sufficient distance cannot be obtained from the gate metal end 11, the drain breakdown voltage does not increase due to the HEMT characteristics, and other DC characteristics tend to deteriorate.

Next, a second conventional example of a gate forming method that solves the above problems will be described with reference to FIGS. In this method, the resist film has a two-layer structure,
The sidewall of the opening is formed in an overhang shape to facilitate lift-off of metal and to obtain a sufficient distance between the recess etching end and the gate metal end.

In FIG. 10A, similarly to the first method, a laminated substrate in which the buffer layer 2, the secondary electron supply layer 3 and the cap layer 4 are formed on the GaAs substrate 1 is prepared, and the lower resist film 15 is formed. Is further applied, and an upper resist film 16 is further applied thereon. Next, with an electron beam exposure device,
A fine line pattern for a gate is drawn on the upper resist film 16 and then developed to form an opening 10a. Next, as shown in FIG. 10B, the lower layer resist 15 is exposed and developed to form the overhang-shaped opening 10. Next, referring to FIG. 11A, 2 having an opening 10 is formed.
After performing the recess etching using the layer resist film as a mask, gate metals 7 and 7g are laminated on the entire surface as shown in FIG. 11 (b). Next, as shown in FIG. 12, the gate metal 7 on the resist is removed by a lift-off method,
A gate electrode 7g is obtained. In this case, the width of the bottom surface of the gate metal 7g is substantially equal to the width of the opening 10a of the upper resist film 16. Therefore, a sufficient space can be provided between the recess etching end and the gate metal 7g end, and the occurrence of burrs as in the first conventional example is reduced. This can increase the drain breakdown voltage. However 2
Because of the layered resist structure, steps such as resist application, drawing, and development are increased, so that the formation time of the resist pattern becomes longer than that in the single layer resist step.

The problems caused by the shape of the opening of the resist pattern have been described above separately for the first and second conventional examples, but at present, the development processing method also has the following problems. That is, regarding resist pattern formation, 1
There is a problem that the size of the opening becomes large if the formation is to be completed by only one developing process. This is because when the resist is exposed by the electron beam, the electron beam is affected by the foreground scatter when entering the resist and the back scatter when passing through the resist film and colliding with the GaAs substrate surface. Scattered electrons are generated, whereby the resist is exposed to light over a predetermined scanning width of the electron beam, that is, a width larger than the design dimension d _{0 of the} opening. FIG. 5 is a schematic cross-sectional view of the resist film 43 for explaining this state. In the figure, the positive type resist film 43 laminated on the GaAs substrate 40 is exposed by the electron beam 41. Reference numeral 44 is a resist region exposed by the electron beam spread by a forescatter or the like, and 45 is a resist region exposed by the electron beam spread by a backscatter or the like. In the case of the development process performed only once, in the conventional method, all the exposed resist is developed, so that the width of the opening 46 also becomes wide as shown in FIG. 6A.

[0009]

As described above, an electric field of a HEMT or the like having a recess gate structure (a structure in which a portion just below a gate electrode of an operating layer of an FET is removed by etching to obtain a desired operating layer thickness). In the gate formation of the effect transistor, as in the first conventional example,
When the side wall of the opening of the resist film has a vertical shape, a sufficient width can be obtained between the width of the bottom surface of the opening after recess etching, that is, the recess etching end and the gate metal end stacked on the bottom surface of the opening. There are problems that it is difficult, the drain breakdown voltage does not increase, and burr is generated on the gate metal after lift-off. As in the case of the second conventional example, the problem of the first conventional example is improved to some extent by forming the resist film into a two-layer structure, but there are problems in that the number of steps is lengthened and the dimension is controlled.

The present invention has been made in view of the above problems, and an object thereof is to make a resist film for forming a recess gate a single layer structure and to stably control the recess etching size at the bottom of the opening. A method of manufacturing a semiconductor device in which a distance between an etching end and an end of a gate metal layer stacked on the bottom surface of an opening can be made sufficiently large, whereby lift-off can be easily performed and characteristics such as drain withstand voltage of an element can be improved. Is to provide.

[0011]

According to the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a field effect transistor having a recess gate structure, (a) a novolac-based positive resist is applied onto a semiconductor substrate. Process,
(B) a step of drawing a gate pattern on the positive resist film with an electron beam exposure apparatus; and (c) a first resist treatment of developing, washing and drying the positive resist film on which the gate pattern is drawn. After performing the steps, a resist treatment step including development, washing with water and drying
A plurality of times or a plurality of times, forming an opening in the positive resist film, the sidewall angle of which is inversely tapered and reaching the substrate surface, and (d) after the recess etching using the positive resist film as a mask, A step of stacking the gate metal and removing the metal on the resist by lift-off.

When a gate pattern (usually a line pattern, the line width of which is called a gate electrode width or a gate metal width) is drawn on a novolac-based positive resist by an electron beam, the resist region exposed by the electron beam is scattered by a scatterer or the like. As a result, the line width becomes wider than the design dimension d ₀ (see FIG. 5). When such a photosensitive resist is subjected to the developing treatment described in the item (c), that is, step development, an opening having a side wall with an inverse taper can be formed.
That is, the width of the bottom surface of the opening is larger than the width of the top surface of the opening. When recess etching is performed using this resist as a mask, the width of the bottom surface of the opening becomes larger by the side etch. When a gate metal is laminated on a resist having such an opening, the width of the gate metal laminated on the bottom surface of the opening is almost equal to the width of the top surface of the opening. Accordingly, the distance between the recess etching end on the bottom surface of the opening and the end of the gate metal layer stacked on the bottom surface of the opening can be stably set to a sufficiently large distance.

According to another aspect of the manufacturing method of the present invention, the thickness of the resist is made thicker than the thickness of the gate metal so that the gate metal on the resist can be reliably lifted off.
The development time of the second resist processing step is 30 seconds to 60 seconds.
Seconds is a manufacturing method that can surely make the angle of the side wall an inverse taper.

According to the third aspect of the present invention, after the first resist treatment step, the developing time in the treatment step performed once or repeatedly is within 30 seconds. The resist profile on the side wall of the opening is set. Is required to control the desired inverse taper shape.

[0015]

EXAMPLE FIG. 1 is a cross-sectional view of a HEMT device formed by applying the manufacturing method of the present invention after recess etching and immediately before lift-off of a gate metal. A novolac-based positive resist 25 is applied on a laminated substrate composed of the GaAs substrate 1 and the like. The resist 25 is formed with an opening 26 having a side wall 27 whose angle is inversely tapered.
In FIG. 1, the same reference numerals as those in FIG. 7 represent the same parts or corresponding parts, and therefore description thereof will be omitted.

Next, a method for manufacturing the HEMT device will be described with reference to FIGS. As shown in FIG. 2A, the buffer layer 2, the secondary electron supply layer 3, and the cap layer 4 are laminated on the GaAs substrate 1 by the epitaxial growth method. A novolac-based positive resist film 25 is applied thereon by spin coating. As the resist, a novolac-based positive resist MP-2400 (Chipley Company) was used. Further, the layer thickness of the resist film needs to be thicker than the film thickness of the gate metal described later. Generally 5
It is about 00 nm to 1000 nm. Next, a fine gate pattern is drawn on the positive resist film 25 with an electron beam exposure apparatus.

Next, the positive resist film having the gate pattern drawn is subjected to a first resist treatment process including development, washing with water and drying. MP2401 was used as the developing solution. The liquid temperature of the developing solution is preferably 23 ° C. to 25 ° C., and the developing time is 30 seconds to 60 seconds, which is determined by trial. FIG. 2A is a cross-sectional view after the first resist process is performed, and the recess 26a is formed.

Next, using the same developing solution again, development is carried out for 30 seconds, followed by washing with water and drying to obtain an opening 26b reaching the substrate surface as shown in FIG. 2 (b). Once again,
The same developing solution is used, development is performed for 30 seconds, washing with water and drying are performed to obtain an opening 26c having a side wall 27 with an inverted taper shape as shown in FIG. 3 (a). The angle of the side wall of the opening 26c is
It is desirable that the angle is 70 to 80 degrees. In this embodiment, the total developing time is 90 seconds in three resist processing steps, but in general, the total developing time is 90 to 12
It takes about 0 seconds, and depending on the profile of the side wall of the opening, the development is performed, for example, four times.

After the formation of the resist pattern is completed, FIG.
As shown in (b), recess etching of the cap layer 4 and the secondary electron supply layer 3 of the substrate is performed with a phosphoric acid-based etching solution using the resist film 25 as a mask. Next in FIG.
As shown in (a), Al-based or Au-based gate metals 7 and 7g are deposited on the entire surface of the substrate on which the resist film 25 is laminated. Next, the unnecessary gate metal 7 on the resist film 25 is removed by the lift-off method, and the gate electrode film 7g is obtained as shown in FIG. 4B.

In the above-described manufacturing method, the resist film for forming the gate has a single-layer structure, and in the second conventional example having a two-layer resist structure, the problem that the resist pattern formation takes too long is solved. It

In the prior art, a resist pattern is formed by one-time development, whereas in the above manufacturing method, it is formed by step development. The difference between the two methods will be described with reference to FIGS. 5 and 6. In FIG. 5, the novolac-based positive resist film 4 applied on the GaAs substrate 40.
When the gate pattern is drawn by the electron beam 41 in FIG. 3, the line width of the resist region exposed by the electron beam becomes wider than the design dimension d ₀ . That is, the photosensitive area is expanded to the outer periphery only by the area 44 exposed by the electron beam expanded by the fore scatter or the like and the area 45 exposed by the electron beam expanded by the back scatter or the like.

FIG. 6A shows the substrate of FIG. 5 in the conventional method, that is, when the development is continuously performed once for 120 seconds, and FIG. 6B shows the step development of the present invention, that is, the first development 6
When the resist treatments of 0 second development, water washing and drying, and then 30 second development and water washing and drying are repeated twice, the shape of the opening in each is shown. When the number of times of development is one, as shown in FIG. 6A, the exposed resist is all developed, so that the opening dimension d ₁ of the opening 46 becomes larger than the design dimension d ₀ . On the other hand, in the case of step development, as shown in FIG. 6B, the opening size has a value of d ₀ which is almost close to the design size. In the resist treatment consisting of development, washing with water and drying, a hardly soluble resist layer is formed and remains on the resist surface in the course of washing and drying the developed resist. The refractory layer slows the subsequent resist processing speed.
In the step development, each time the resist treatment is repeated, the refractory layer of the resist is laminated, the refractory layer 47 is formed as shown in FIG. 6B, the increase of the opening size is prevented, and the side wall of the reverse taper is removed. Can be formed.

Width w of the top of the opening 26 shown in FIG. 3 (b)
_In contrast to ₁ , the width w ₂ of the bottom of the opening 26 is w ₂ > w ₁ because the side walls are inversely tapered. The reverse taper shape is
It is stable because it is well controlled by step development. In addition, the width w _{3 of the} recess portion is formed through the recess etching.
Can be controlled. Further, the width w ₄ of the gate metal 7g shown in FIG. 4A is substantially equal to the width w ₁ of the top of the opening, and as a result, the distance (w ₃ −w ₄ ) between the recess etching end and the gate metal end. / 2 can be made sufficiently large, and the DC characteristics of the device such as drain withstand voltage can be improved. Further, since it has a reverse taper shape, lift-off can be easily performed.

Although the HEMT device has been described in the above embodiment, the present invention is not limited to the M type having the recess gate structure.
It can also be applied to the manufacturing method of other field effect transistors such as ESFET.

[0025]

As described above, according to the present invention, the resist film for forming the recess gate has a single-layer structure, the side wall of the opening of the resist pattern has an inverse taper structure, and the recess etching size of the bottom of the opening is reduced. Stable control is now possible. As a result, the present invention can sufficiently increase the distance between the edge of the gate metal laminated on the bottom surface of the opening and the edge of the recess etching, facilitate lift-off, and improve the characteristics such as the drain breakdown voltage of the device. It was possible to provide a method for manufacturing the obtained semiconductor device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a HEMT device to which the present invention is applied just before lift-off of gate metal.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device of the present invention following FIG.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device of the present invention following that of FIG. 3;

FIG. 5 is a cross-sectional view for explaining a resist region exposed by an electron beam.

FIG. 6 is a sectional view showing the shape of an opening when the photosensitive resist of FIG. 5 is subjected to conventional development and FIG. 6 (b) is subjected to step development of the present invention.

FIG. 7 is a cross-sectional view of a conventional HEMT device immediately before lift-off of gate metal.

FIG. 8 is a cross-sectional view showing a manufacturing process of a first conventional example.

FIG. 9 is a cross-sectional view showing a manufacturing process that follows FIG. 8 of the first conventional example.

FIG. 10 is a cross-sectional view showing a manufacturing process of a second conventional example.

FIG. 11 is a cross-sectional view showing a manufacturing process that follows FIG. 10 of the second conventional example.

FIG. 12 is a cross-sectional view showing a manufacturing process that follows FIG. 11 of the second conventional example.

[Explanation of symbols]

1 GaAs substrate 2 buffer layers 3 Secondary electron supply layer 4 Cap layer 5 Resist film 7 Gate metal 7g Gate metal (gate electrode) 15 Resist film 25 Novolac positive resist film 26 opening

Claims (3)

[Claims] 1. A method of manufacturing a field effect transistor having a recess gate structure, comprising: (a) applying a novolac-based positive resist on a semiconductor substrate; and (b) forming a gate pattern on the positive resist film with an electron beam. A step of drawing with an exposure device, and (c) the positive resist film having a gate pattern drawn thereon is subjected to a first resist treatment step of development, washing and drying, and then development, washing and drying. Repeating the resist treatment step once or a plurality of times to form an opening in the positive resist film, the sidewall angle being inversely tapered and reaching the substrate surface; and (d) using the positive resist film as a mask. Stacking gate metal after recess etching, and removing the metal on the resist by lift-off. The method of manufacturing a semiconductor device according to claim. 2. The semiconductor device according to claim 1, wherein the novolac-based positive resist is formed to have a film thickness exceeding the film thickness of the gate metal, and the developing time in the first resist processing step is 30 seconds to 60 seconds. Production method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a developing time of the resist processing step repeated once or a plurality of times does not exceed 30 seconds.