JPH03171741A - Manufacture of gaas fet - Google Patents

Abstract

PURPOSE:To obtain a highly reliable high-frequency and low-noise amplification GaAs FET without using an electronic ray exposure device by utilizing the overhang of a photoresist layer and by forming an insulation layer with a narrower opening pattern than an opening pattern width of the photoresist layer on the bottom of an open recess by a skew deposition of the insulation film. CONSTITUTION:After a source electrode 2 and a drain electrode 3 are formed at a GaAs operation layer 1, a photoresist layer 4 with an opening pattern in a specified width is formed at a gate region. With this photoresist layer 4 as a mask, recess etching is made to the GaAs operation layer 1 of the gate region and then an insulation film 5 is formed at a recess opening bottom 6 by a skew deposition of the insulation film. Then, a first-layer gate metal 7 is deposited from directly above and then a second-layer gate metal 8 is deposited. The insulation film 5 which is deposited onto the photoresist layer 4, the first-layer gate metal 7, and a second-layer gate metal 8 are lifted off the deposition part on a recess opening bottom 6. When a photoresist layer 4 is eliminated, only the gate part in overlay structure on the recess opening bottom 6 remains.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for manufacturing a GaAsFET for high-frequency, low-noise amplification in which the gate length is shortened in order to exhibit low-noise characteristics even in the high frequency band of the microwave band. Regarding. [Prior Art] Unlike the surface of silicon, GaAs cannot be heat-treated in oxygen to form a durable oxide, so it is impossible to form a MOS gate.
AsFET uses a surface barrier type (Schottky type barrier) gate structure. Figure 2 shows a conventional GaAsFE with a gate length of 0.25 μm.
An example of a method for manufacturing T is shown below.

First, ions are implanted into the GaAs active layer to form a layer for preventing bunch-through, and after forming the source electrode 2 and drain electrode 3 on the GaAs active layer 1 [Figure (a)], electron beam exposure technology is used to By stepwise exposure, a resist layer 14 with a two-step structure in which the lower part is 0.25μ step wide and the upper part is wider is formed at the opening (Figure (b)), and this resist layer 14 is used as a mask to form a resist layer 14. Perform etching [Figure (
C)) (Some products do not have a horizontal recessed structure.) Next, the first layer of gate metal 7 is deposited from directly above, and the second layer of gate metal 8 is deposited on top of the first layer of gate metal 7. Vapor deposition (Figure (d)). The gate metal 7 deposited on the surface of the resist layer l4 and the gate metal 8 deposited on the gate metal 7 are the same as the gate metal 7 deposited on the surface of the recess opening bottom 6 and the gate metal 7 deposited on the gate metal 7. When lifted off from metal 8 and removing resist layer l4,
The deposited metal other than the gate portion is removed to form a gate.

[Problem that the invention seeks to solve]

The conventional manufacturing method described above requires a very expensive electron beam exposure system to form a resist layer pattern with a 0.25μ-wide opening, and since the electron beam exposure system is used, batch processing is not required. Can not.

Furthermore, due to the space between the eaves of the resist layer 14 created by recess etching and the bottom of the recess opening 6, wraparound occurs during gate metal deposition, and the actual gate length becomes wider than the resist layer pattern width.

In addition, in the case of a multilayer gate metal, due to the effect of the above-mentioned metal wrapping around, the second and third layer metals are exposed to Ga on the side of the gate.
There was a problem of contact with the As layer.

The present invention was made in view of the above problems, and
It is an object of the present invention to provide a manufacturing method for manufacturing a highly reliable GaAs FET for high frequency, low noise amplification without using an electron beam exposure device.

[Means to solve the problem]

In the manufacturing method of the present invention, after forming source and drain electrodes on the GaAs active layer, a photoresist layer having an open pattern of a predetermined width is formed in the gate region by a normal deep ultraviolet exposure method. Recess etching is performed on the mask, and an insulating film having an opening pattern narrower than the opening pattern width of the photoresist layer is formed at the bottom of the recess opening by diagonal vapor deposition of an insulating film using the eaves of the photoresist layer. By vapor deposition of gate metal,
A gate with an overlay structure is formed within the lobe pattern between the insulating films and connected to the GaAs active layer.

〔Example〕

FIG. 1 shows an embodiment of the invention.

GaAs operation! After forming a source electrode 2 and a drain electrode 3 on the gate region 1 (Fig. (a)), a photoresist layer 4 having an opening pattern of a predetermined width is formed in the gate region by a conventional deep ultraviolet exposure method (Fig. (b)). ), using the photoresist layer 4 as a mask, the GaAs active layer 1 in the gate region is recessed and etched (Fig. (Cl)). Next, using the eaves of the photoresist layer 4, an insulating film is diagonally deposited to form a 0.00000000000000000000000 in the bottom of the recess opening 6. 2
An insulating film 5 having an open pattern with a width of 5μ is formed [
Figure (d)].

Next, a first layer of gate metal 7 is deposited from directly above, and then a second layer of gate metal 8 is deposited [Figure (e)
].

The insulating film 5 deposited on the photoresist l-Jid, the first layer gate metal 7 deposited on this insulating film 5, and the second layer gate metal 8 deposited on this gate metal 7 are as follows. , is lifted off from the deposited portion on the recess opening bottom 6, and when the photoresist layer 4 is removed, the recess opening bottom 6
Only the gate part of the overlay structure above remains [Figure (r
)) - According to the above method, there is no need to make the opening pattern of the photoresist layer 4 finer, and even if the width can be easily formed by deep ultraviolet exposure, the opening width of the insulating film 5 can be reduced to 0. 25μ can be set to one, gate length 0.25μ-
A gate with an overlay structure is obtained.

Since there is no space between the insulating film 5 of the opening width 0.25μ pattern and the recess opening bottom 6, the actual gate length falls within 0.25μ.

〔Effect of the invention〕

As explained above, according to the present invention, GaAsFE for high frequency, low noise amplification can be used without using an electron beam exposure device.
This method has the advantage that it is possible to manufacture T, and gate metals such as the second and third layers do not come into contact with the GaAs layer.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing an example of a conventional method for manufacturing a GaAsFET with a gate length of 0.25 μm. l...GaAs operating layer, 2...source electrode, 3...
- Drain electrode, 4... Photoresist layer, 5...
Insulating film, 6... Recess opening bottom, 7, 8... Gate metal. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] After forming source and drain electrodes on the GaAs active layer,
forming a photoresist layer having an opening pattern of a predetermined width in the gate region, and performing recess etching of the GaAs active layer in the gate region using the photoresist layer as a mask;
After recess etching, an insulating film having an opening pattern narrower than the opening pattern width of the photoresist layer is formed at the bottom of the recess opening by diagonal vapor deposition of an insulating film using the eaves of the photoresist layer, and the gate metal is applied from directly above. vapor deposited,
A method for manufacturing a GaAs FET, characterized in that lift-off is performed using the photoresist layer, and a gate having an overlay structure is formed at the bottom of the recess opening to be bonded to the GaAs active layer using the opening pattern of the insulating film.