JPH02165639A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH02165639A JPH02165639A JP63319371A JP31937188A JPH02165639A JP H02165639 A JPH02165639 A JP H02165639A JP 63319371 A JP63319371 A JP 63319371A JP 31937188 A JP31937188 A JP 31937188A JP H02165639 A JPH02165639 A JP H02165639A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- resist
- gate electrode
- gate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000004380 ashing Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は１例えば、マイクロ波帯での増幅用に使用する
ＧａＡｓＦＥＴのように、高ｇｍの実現のために。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to the realization of high gm, such as GaAs FETs used for amplification in the microwave band.
ゲート電極をマスクに高濃度にイオン注入してソース、
ドレインを形成する方法を採る半導体素子の製造方法に
関する。Using the gate electrode as a mask, ions are implanted at high concentration to form the source,
The present invention relates to a method of manufacturing a semiconductor device that employs a method of forming a drain.
マイクロ波帯での増幅に使用するＧａＡｓＦＥＴでは。 In GaAsFETs used for amplification in the microwave band.
相互コンダクタンスｇｍの増大が要求される。高ｇｍの
実現には、ソース・ｆｆ−）間の直列抵抗Ｒｓの低減が
重要で、 Ｒｓの低減のために、ソース、ドレインに高
濃度のイオン注入を行う構造のものがある。An increase in mutual conductance gm is required. In order to achieve a high gm, it is important to reduce the series resistance Rs between the source and ff-), and in order to reduce Rs, there are structures in which high concentration ions are implanted into the source and drain.
第２図は従来のこの種半導体素子の製造方法の−例を示
す。FIG. 2 shows an example of a conventional method for manufacturing this type of semiconductor device.
ｎアクティブ層を有するＧａＡｓ基板１にリフトオフ法
などによシグート電極５を形成し〔図（ａ） ） 。A Sigut electrode 5 is formed on a GaAs substrate 1 having an n-active layer by a lift-off method or the like [Figure (a)).
次に、ゲート電極５をマスクに高濃度のイオン注入を行
うことによシ、高不純物濃度層（ｎ）６のソース、ドレ
イン６を形成する〔図（ｂ）〕。Next, by performing high concentration ion implantation using the gate electrode 5 as a mask, the source and drain 6 of the high impurity concentration layer (n) 6 are formed [FIG. (b)].
上記のような従来の方法では、ソース・ゲート間の直列
抵抗Ｒｓの低減は行なえるが、ｙ−ト電極５に接して高
不純物濃度層６が存在するため、十分なゲート耐圧が確
保できないという問題があった。Although the conventional method described above can reduce the series resistance Rs between the source and the gate, it is difficult to ensure a sufficient gate breakdown voltage due to the presence of the high impurity concentration layer 6 in contact with the Y-t electrode 5. There was a problem.
本発明は上記の問題を解消するためになされたもので、
直列抵抗Ｒ１１を低減できるとともに、十分なｒ−ト耐
圧を確保できる製造方法を提供することを目的とする。The present invention was made to solve the above problems.
It is an object of the present invention to provide a manufacturing method that can reduce the series resistance R11 and ensure sufficient r-to withstand voltage.
本発明の製造方法は、アクティブ層を有する基板表面の
ｒ−ト電極接合部に側面が逆チー／４’−状のレジスト
層を形成し、該レジスト層と基板表面を覆う絶縁膜を形
成し、該絶縁膜上にレジストを表面が平らになる厚さだ
塗布し、該レジストを上記レジスト層上部の絶縁膜表面
が露出するまで除去し、表面が露出した絶縁膜部分をエ
ツチングにより除去し、全てのレジストを除去して基板
表面にゲート・メタルを蒸着し、基板表面を覆う絶縁膜
に蒸着したゲート・メタルを絶縁膜をエツチング除去す
ることによシ除去して、側面が逆テーパー状のゲート電
極を形成し、該ゲート電極をマスクに高濃度のイオン注
入を行いソース、ドレインを形成するものである。The manufacturing method of the present invention includes forming a resist layer having an inverted chip/4'-shaped side surface at the r-to-electrode junction portion on the surface of a substrate having an active layer, and forming an insulating film covering the resist layer and the surface of the substrate. , Apply a resist on the insulating film to a thickness that makes the surface flat, remove the resist until the surface of the insulating film above the resist layer is exposed, and remove the exposed part of the insulating film by etching, The resist is removed and gate metal is deposited on the substrate surface, and the gate metal deposited on the insulating film covering the substrate surface is removed by etching the insulating film to form a gate with reverse tapered sides. An electrode is formed, and high concentration ions are implanted using the gate electrode as a mask to form a source and a drain.
上記の方法によると、イオン注入による高不純物濃度層
（ｎ＋）がｆ−）接合部から適当なスｄ−スｔおいて形
成され、直列抵抗の低減とゲート耐圧の向上を同時に計
ることができる。According to the above method, a high impurity concentration layer (n+) is formed by ion implantation at an appropriate distance from the f-) junction, and it is possible to reduce series resistance and improve gate breakdown voltage at the same time. .
第１図は本発明の一実施例を示す。 FIG. 1 shows an embodiment of the invention.
ｎアクティブ層を有するＧａＡｓ基板１表面に、リング
ラフィ法によシ、側面が逆テーパー状のレジスト・ぞタ
ーン２を形成し〔図（ａ）〕、プラズマＣＶＤ法などに
よりレジストパターン２と基板１表面を覆う絶縁膜３を
形成し〔図（ｂ） ）、この絶縁膜３上にレジスト４を
表面が平らになる厚さに塗布する〔図（Ｃ）〕。On the surface of the GaAs substrate 1 having the n-active layer, a resist pattern 2 with reversely tapered side surfaces is formed by phosphorography (Figure (a)), and then the resist pattern 2 and the substrate 1 are formed by plasma CVD or the like. An insulating film 3 is formed to cover the surface (FIG. (b)), and a resist 4 is coated on this insulating film 3 to a thickness that makes the surface flat [FIG. (C)].
次に、レジスト４を、アッシングなどにより、レジスト
パターン２上部の絶縁膜３０表面が露出する厚さにまで
除去し〔図（ｄ）〕、表面が露出した絶縁膜３をエッチ
ングにより除去し〔図（ｅｌ ］ 、アアラシンブナに
より、レジストパターン２とＰＲ膜３上に塗布したレジ
スト４を除去し〔図（ｆ）〕、基基板面にゲート電極と
なるゲート・メタル５を蒸着する。この場合、レジスト
パターン２の側面を覆っていた絶縁膜３により、上記絶
縁膜３の内の蒸着メタル５と基板表面を覆う絶縁膜３上
の蒸着メタル５はリフトオフされる〔図（ｇ）〕。Next, the resist 4 is removed by ashing or the like to a thickness that exposes the surface of the insulating film 30 above the resist pattern 2 [Figure (d)], and the exposed surface of the insulating film 3 is removed by etching [Figure (d)]. (el), remove the resist 4 coated on the resist pattern 2 and the PR film 3 using Aarashin Buna [Figure (f)], and deposit the gate metal 5 that will become the gate electrode on the base substrate surface. The insulating film 3 covering the side surface of the pattern 2 lifts off the vapor-deposited metal 5 in the insulating film 3 and the vapor-deposited metal 5 on the insulating film 3 covering the substrate surface [FIG. (g)].
次に、絶縁膜３をエツチングにより除去すると、基板表
面を覆う絶縁膜３上の蒸着メタル５が除去され、側面が
逆テーノや一状のゲート電極５のみが残る。Next, when the insulating film 3 is removed by etching, the vapor-deposited metal 5 on the insulating film 3 covering the substrate surface is removed, leaving only the gate electrode 5 whose side surfaces are inverted or straight.
このゲート電極５をマスクに高濃度のイオン注入を行う
と、ソース、ドレインの高不純物濃度層（ｎ＋）６はゲ
ート電極５接合部からｔの幅の低濃度層（ｎｏ）を隔て
て形成され〔図（ｉ） ］ 、十分なゲート耐圧が確保
される。When high-concentration ion implantation is performed using this gate electrode 5 as a mask, the high impurity concentration layer (n+) 6 of the source and drain is formed with a low concentration layer (no) having a width of t separated from the junction of the gate electrode 5. [Figure (i)] Sufficient gate breakdown voltage is ensured.
以上説明したように、本発明によれば、ソース。 As explained above, according to the present invention, the sauce.
ドレインの高不純物濃度層（ｎ ）がｆ−）電極接合部
ニジある幅の低濃度層（、）を挾んで形成されるため、
十分なゲート耐圧を保った状態で、ソース・ｒ−ト間の
直列抵抗を低減することができ、相互コンダクタンスｇ
ｍの増大が計れ、マイクロ波での増幅用素子として重要
な特性のＮ、Ｆ、（雑音指数）及びＧａ１ｎσＵ得）の
改善に寄与する効果が大である。Since the high impurity concentration layer (n) of the drain is formed sandwiching the low concentration layer (,) with a certain width at the f-) electrode junction,
While maintaining sufficient gate breakdown voltage, the series resistance between the source and r-t can be reduced, and the mutual conductance g
This has a significant effect of contributing to the improvement of N, F, (noise figure) and Ga1nσU gain, which are important characteristics for a microwave amplification element.
第１図は本費明の一実施例を示す説明図、第２図は従来
のこの種半導体素子の製造方法の一例を示す説明図であ
る。
１・・・ＧａＡｓ基板、２・・・レジストパターン、３
・・・絶縁膜、４・・・レジスト、５・・・ゲート・メ
タル、６・・・高不純物濃度層。
なお図中同一符号は同一または相当する部分を示す。FIG. 1 is an explanatory diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing an example of a conventional manufacturing method of this type of semiconductor device. 1...GaAs substrate, 2...Resist pattern, 3
...Insulating film, 4...Resist, 5...Gate metal, 6...High impurity concentration layer. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ドレインを形成する半導体素子の製造方法において、ア
クティブ層を有する基板表面のゲート電極接合部に側面
が逆テーパー状のレジスト層を形成する工程と、上記レ
ジスト層と基板表面を覆う絶縁膜を形成する工程と、上
記絶縁膜上にレジストを表面が平らになる厚さに塗布す
る工程と、上記絶縁膜上に塗布したレジストをゲート電
極接合部に形成した上記レジスト層上部の絶縁膜表面が
露出するまで除去する工程と、表面が露出した絶縁膜を
エッチングにより除去する工程と、上部の絶縁膜を除去
した上記レジスト層と基板表面を覆う絶縁膜上に塗布し
たレジストを全て除去する工程と、全てのレジストを除
去した基板表面にゲート・メタルを蒸着する工程と、基
板表面を覆う絶縁膜に蒸着したゲート・メタルを該絶縁
膜をエッチングにより除去することで除去する工程とに
より側面が逆テーパー状のゲート電極を形成し、該ゲー
ト電極をマスクに高濃度にイオン注入してソース、ドレ
インを形成することを特徴とする半導体素子の製造方法
。Using the gate electrode as a mask, ions are implanted at high concentration to form the source,
A method of manufacturing a semiconductor device forming a drain includes the steps of: forming a resist layer with reversely tapered sides at a gate electrode junction on a surface of a substrate having an active layer; and forming an insulating film covering the resist layer and the surface of the substrate. a step of applying a resist on the insulating film to a thickness that makes the surface flat; and a step of applying a resist on the insulating film to a thickness that makes the surface flat, and exposing the surface of the insulating film above the resist layer where the resist applied on the insulating film is formed at the gate electrode junction. a step of removing the insulating film whose surface is exposed by etching, a step of removing all the resist coated on the resist layer from which the upper insulating film has been removed and the insulating film covering the substrate surface; The sides are formed into a reverse tapered shape by the step of vapor depositing gate metal on the substrate surface from which the resist has been removed, and the step of removing the gate metal deposited on the insulating film covering the substrate surface by etching the insulating film. 1. A method of manufacturing a semiconductor device, comprising: forming a gate electrode; and using the gate electrode as a mask, ions are implanted at a high concentration to form a source and a drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63319371A JPH02165639A (en) | 1988-12-20 | 1988-12-20 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63319371A JPH02165639A (en) | 1988-12-20 | 1988-12-20 | Manufacture of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02165639A true JPH02165639A (en) | 1990-06-26 |
Family
ID=18109403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63319371A Pending JPH02165639A (en) | 1988-12-20 | 1988-12-20 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02165639A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468151A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for making metal gate electrode |
-
1988
- 1988-12-20 JP JP63319371A patent/JPH02165639A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468151A (en) * | 2010-11-19 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for making metal gate electrode |
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