JPS6020584A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6020584A JPS6020584A JP12766983A JP12766983A JPS6020584A JP S6020584 A JPS6020584 A JP S6020584A JP 12766983 A JP12766983 A JP 12766983A JP 12766983 A JP12766983 A JP 12766983A JP S6020584 A JPS6020584 A JP S6020584A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- pattern
- gaas
- ion implantation
- gate pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract 4
- 238000000576 coating method Methods 0.000 claims abstract 4
- 238000005121 nitriding Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000007789 gas Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 abstract 1
- 229910000070 arsenic hydride Inorganic materials 0.000 abstract 1
- 238000005259 measurement Methods 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置および集積回路等の製法に係り、特
にセルフアラインメントに好適な上記の製法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing semiconductor devices, integrated circuits, etc., and particularly to the above-mentioned manufacturing method suitable for self-alignment.
高速・高周波用の電界効果トランジスタ（ＦＥＴ）では
性能向上のため、ゲート長を短かくし、ゲートに近接す
るソース・ドレイン領域を設ける必要がある。この改善
策の１つとして、ゲートにソース・ドレインをセルフ・
アラインメント方式で形成する技術が使われている。In order to improve the performance of field effect transistors (FETs) for high speed and high frequency applications, it is necessary to shorten the gate length and provide source/drain regions close to the gate. One of the ways to improve this is to connect the source and drain to the gate using a self-contained structure.
A technology that uses an alignment method is used.
従来のセルフ・アラインメント方式は耐熱性の優れたゲ
ート金属（例えばＷやＷ８ｊｘなど）をＧ ａ Ａ ｓ
基板結晶上に形成したあと、上記ゲート金属なマスクに
して８ｉイオンを打込んでアニールし、高濃度（ｎｌ）
領域をゲート近傍に形成するものであった。その後、ソ
ース・ドレインのオーミック電極を通常のマスク合せに
ょシ上記ｎ゛領域上に形成していたが、” ＱａＡ８の
比抵抗は１０゛３Ω（７）とやや高く、ソース・ドレイ
ンのオーミック電極とゲート電学間の短離をさらに短か
くすることが望まれていた。In the conventional self-alignment method, a gate metal with excellent heat resistance (such as W or W8jx) is used as a gate metal.
After forming on the substrate crystal, 8i ions are implanted and annealed using the gate metal mask as described above to form a high concentration (nl)
The area was formed near the gate. After that, ohmic electrodes for the source and drain were formed on the above n' region using normal mask alignment. It has been desired to further shorten the distance between gate electronics.
本発明の目的はゲートに対して” ＧａＡｓ領域をセル
フ・アラインメントで形成し、さらにゲートに対してソ
ース・ドレインのオーミック電極をセルフ・、アライン
メントで形成する半導体装置の製法を提供することにあ
る。An object of the present invention is to provide a method for manufacturing a semiconductor device in which a GaAs region is formed in a self-aligned manner with respect to a gate, and ohmic electrodes for source and drain are formed in a self-aligned manner with respect to the gate.
本発明によるゲートパターンの構造は、少なくとも高耐
熱性金属とＳｉなどの２層以上に積層されたものから成
シ、上記金属層はＧ ａ Ａ ｓとショットキ接合を形
成し８００層以上のアニールに耐え、Ｂｉなどの層は酸
素プラズマ放電によって８１０２層に加工することによ
ってパターン寸法を増加させ、Ｔ形断面形状のゲートパ
ターンに変形させたあとソース・ドレイン電極をセルフ
・アインメントで形成することを特徴としている・
〔発明の実施例〕
以下、本発明の一実施例を第１図によシ説明する。第１
図はＧａＡｓ−ＦＥＴの製造工程を示したものである。The structure of the gate pattern according to the present invention is made of at least two or more laminated layers such as a high heat-resistant metal and Si, and the metal layer forms a Schottky junction with GaAs and is annealed for more than 800 layers. The pattern size is increased by processing the Bi and other layers into 8102 layers using oxygen plasma discharge, and after transforming the gate pattern into a T-shaped cross-sectional shape, the source and drain electrodes are formed by self-alignment. Features・ [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG. 1. 1st
The figure shows the manufacturing process of GaAs-FET.
半絶縁性ＧａＡｓ１にｎ形能動層２をイオン打込み／ア
ニール工程で形成し、蒸着又はスパッタによりＷ３（０
，３μｍｎ厚さ）と５ｉ４（０，３μｍ厚さ）を被着し
、ホトリソグラフィ工程によシゲートパターン５をＣＦ
４からなるプラズマのドライエッチで形成する。その後
、ゲートパターン７をマスクにしてＳｉイオンを〜２０
０ＫｅＶ、〜５Ｘ１０” ７ｃｍ”の条件で打込んで、
レジスト７を除去後、ＡＳＨ３ガス雰囲気のもとで５ｏ
ｏｔ：のアニールをして高濃度（ｎ”）ＧａＡｓ層６を
形成する（同図（ａ））。その後、酸素プラズマ放電に
よりＳｉ４パターンを酸化させて、５ｉ０２８とする。An n-type active layer 2 is formed on semi-insulating GaAs 1 by ion implantation/annealing process, and W3 (0
, 3 μm thick) and 5i4 (0.3 μm thick), and the siginate pattern 5 was formed using a photolithography process.
4 by plasma dry etching. After that, using the gate pattern 7 as a mask, ~20% of Si ions are applied.
Input under the conditions of 0KeV, ~5X10"7cm",
After removing the resist 7, it was heated at 5o under an ASH3 gas atmosphere.
ot: is annealed to form a high concentration (n'') GaAs layer 6 (FIG. 4(a)). Thereafter, the Si4 pattern is oxidized to 5i028 by oxygen plasma discharge.
この操作によってゲートパターン５０Ｂ４部分は処理時
間に比例して体積を増大させ、Ｗ３パターン長よ如りだ
け寸法が長くなる。このＤをここでは０．２μｍ程度と
した（同図（ｂ））。その後、ホトレジパターン９を形
成し、ＡｕＧｅを主体としたオーミック金属ｔｏ、ｉｉ
を約０゜２μｍの厚さに蒸着する。この蒸着操作は蒸着
源と半導体結晶を十分離して指向性で被着するようにし
ている。このとき５ｉ０２８パターンによってオーミン
ク電極１０゜１１とゲート電極３が分離される。（同図
（Ｃ））。By this operation, the volume of the gate pattern 50B4 portion increases in proportion to the processing time, and the dimension becomes longer by the length of the W3 pattern. Here, this D was set to about 0.2 μm (FIG. 6(b)). After that, a photoresist pattern 9 is formed, and an ohmic metal mainly composed of AuGe is formed.
is deposited to a thickness of approximately 0.2 μm. In this evaporation operation, the evaporation source and the semiconductor crystal are separated sufficiently to achieve directional deposition. At this time, the ohmink electrode 10°11 and the gate electrode 3 are separated by the 5i028 pattern. (Figure (C)).
その後、レジスト９を溶解し、レジスト上の不要のＡｕ
Ｇｅ系金属１２を除去（リフトオフ）する。After that, resist 9 is dissolved and unnecessary Au on the resist is dissolved.
The Ge-based metal 12 is removed (lifted off).
その後、この表面に層間絶縁膜を被着して、ソー ス・
ドレイン電極、及びゲート電極上にコンタクトホールを
形成しＩｉ’ Ｅ Ｔとその集積回路を形成する。After that, an interlayer insulating film is deposited on this surface, and the source
Contact holes are formed on the drain electrode and gate electrode to form Ii' ET and its integrated circuit.
第２図は他の実施例を説明するためでＧａＡｓＦＥＴの
製造工程を示す図である。第１図の（ａ）と同様にゲー
トパターン２５はｗｓｉｚａ（ｏ、ａμｍ厚さ）とｓ
ｉ２４ （０，３μｍ厚さ）の積層で形成、加工し、こ
のパターンをマスクに高濃度Ｓｉイオンを打込んで、つ
づいてキャップ材５ｊＮ２０その後、キャンプ材５ｉＮ
２０を異方性ドライエツチング（ＣＦ’、系几ＩＥ装置
）で除去してゲ第１図と第２図で述べたように本発明は
ゲートパターンを異方性となる条件で加工し、ゲート長
の寸法を正確に制御したのち、ゲート被覆材を太らせて
Ｔ形断面形状とすることを特徴としている。FIG. 2 is a diagram showing the manufacturing process of a GaAsFET for explaining another embodiment. As in FIG. 1(a), the gate pattern 25 has wsiza (o, aμm thickness) and s
i24 (0.3 μm thick) is formed and processed, using this pattern as a mask, high concentration Si ions are implanted, followed by cap material 5jN20, and then camping material 5iN.
As described in FIGS. 1 and 2, the present invention processes the gate pattern under conditions that make it anisotropic. It is characterized by accurately controlling the length dimension and then thickening the gate covering material to form a T-shaped cross-section.
Ｔ形断面形状を得るには異方性の条件でゲートパターン
を加工したあと、等方性となる条件でゲート金属をオー
バエツチング（サイドのみを削る）することも出来るが
、経験的にサイドエツチングの制御は悪く、ウェハ面内
分布とロット間ばらつきが大きいことが欠点であったの
で本発明ではこれを解決した。To obtain a T-shaped cross-sectional shape, it is possible to process the gate pattern under anisotropic conditions and then over-etch the gate metal (shaving off only the sides) under isotropic conditions, but from experience we found that side etching The drawbacks were poor control of the wafer and large in-wafer distribution and lot-to-lot variations, which were solved by the present invention.
本発明によれば、ゲート電極に対してｎ９高濃度層およ
びソース・ドレイン電極がセルフ・アラインメントされ
るので、直列抵抗が大幅に低減されＦＥＴの特性改善の
効果がある。ゲート長はゲートパターンの加工精度で決
められるので、寸法ばらつきはサイドエツチングする方
法よシ小さい。According to the present invention, since the n9 high concentration layer and the source/drain electrodes are self-aligned with respect to the gate electrode, the series resistance is significantly reduced and the characteristics of the FET are improved. Since the gate length is determined by the processing accuracy of the gate pattern, dimensional variations are smaller than with the side etching method.
Ｔ形断面形状は上述したようにソース・ドレイン電極を
セルフアラインメントで形成するためにショート金防ぐ
目的で必要である。０３層のイオン打込みにはこのひさ
しが無いほうが集子の性能向上に優れ、イオン打込み後
にこのひさしをｆｌｉｌＪ ＸＩして加工する方法を本
発明の特徴としている。このためひさしとなる拐質には
実施例で述べたＳｉの他ＡｔＮｂなどもよく限定するも
のでない。また酸化または窒化゛の方法は、実施例で述
べたプラズマ中の陽極酸化の他に、例えばＡｔを水やア
ルカリ溶液中でＡｔ２０３にする方法もあることを附言
する。The T-shaped cross-sectional shape is necessary for the purpose of preventing short circuits in order to form the source/drain electrodes in self-alignment as described above. In the ion implantation of the 03 layer, the performance of the collector is better when the eaves are not provided, and the present invention is characterized by a method in which the eaves are processed by flilJ XI after ion implantation. For this reason, the material for forming the eaves is not limited to AtNb or the like other than Si as described in the embodiment. It should be added that the oxidation or nitridation method includes, for example, a method of converting At into At203 in water or an alkaline solution, in addition to the anodic oxidation in plasma described in the embodiment.
第１図と第２図は本発明のそれぞれ１実施例の工程別の
断面図である。
１・・・半導体基板結晶、３．２３・・・高耐熱性金属
（ゲート電極）、４，２４・・・ゲート被覆材、８゜２
８・・・酸化したゲート材、１０，１００・・・ソース
％１ 図FIGS. 1 and 2 are cross-sectional views of each process of an embodiment of the present invention. 1...Semiconductor substrate crystal, 3.23...High heat-resistant metal (gate electrode), 4,24...Gate covering material, 8゜2
8... Oxidized gate material, 10,100... Source%1 Figure
Claims (1)
ら成るゲートパターンを用い、高ドーズのイオン打込み
をゲートパターンを覆い囲むが如くおこない、アニール
を行う工程と、上記ゲート被覆材を酸化もしくは窒化処
理によって体積を増化せしめる工程と、上記変形させた
ゲートパターンによってゲート金属にソース・ドレイン
電極をセルフ・アラインメントする工程とから成ること
を特徴とする半導体装置の製法。1. Using a gate pattern consisting of at least a two-layer structure of gate metal and gate coating material, performing high-dose ion implantation so as to cover and surround the gate pattern, and annealing the gate coating material, and oxidizing or nitriding the gate coating material. A method for manufacturing a semiconductor device comprising the steps of: increasing the volume by using the deformed gate pattern; and self-aligning source and drain electrodes to the gate metal using the deformed gate pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12766983A JPS6020584A (en) | 1983-07-15 | 1983-07-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12766983A JPS6020584A (en) | 1983-07-15 | 1983-07-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6020584A true JPS6020584A (en) | 1985-02-01 |
Family
ID=14965787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12766983A Pending JPS6020584A (en) | 1983-07-15 | 1983-07-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020584A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4770143A (en) * | 1986-02-14 | 1988-09-13 | Nissan Motor Company, Limited | System and method for controlling ignition timing for an internal combustion engine |
| JPS6424163A (en) * | 1987-07-20 | 1989-01-26 | Mitsubishi Motors Corp | Knock control device |
| JPH021139A (en) * | 1988-01-08 | 1990-01-05 | Toshiba Corp | Compound semiconductor device and its manufacture |
-
1983
- 1983-07-15 JP JP12766983A patent/JPS6020584A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4770143A (en) * | 1986-02-14 | 1988-09-13 | Nissan Motor Company, Limited | System and method for controlling ignition timing for an internal combustion engine |
| JPS6424163A (en) * | 1987-07-20 | 1989-01-26 | Mitsubishi Motors Corp | Knock control device |
| JPH021139A (en) * | 1988-01-08 | 1990-01-05 | Toshiba Corp | Compound semiconductor device and its manufacture |
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